JPS62179211A - Digital graphic equalizer - Google Patents

Abstract

PURPOSE:To obtain natural listening sense by bringing plural coefficients of a digital filter attended with an equalizer characteristic variable operation into a coefficient of an intermediate characteristic once and switching them into a coefficient of a designated characteristic. CONSTITUTION:An intermediate characteristic coefficient selection section 35 selects a coefficient data having a characteristic between a characteristic before the characteristic change and that changed and designated. Coefficient set sections 6L, 6R set coefficient data corresponding respectively to plural coefficients a1-an of a digital filter in response to the information from the characteristic input section 12 and the intermediate characteristic coefficient selection section 35. Coefficient set means DSP 3L, 3R are provided with rewritable coefficient memories 13L, 13R corresponding to the plural coefficients of the digital filter, the incoming digital signal is operated by the coefficient of the coefficient memories 13L, 13R and the result is extracted. A CPU 9 and the memory control sections 5L, 5R rewrite once a data from the coefficient setting means into the coefficient of the intermediate characteristic into the coefficient memories 13L, 13R once and rewrite it into the data of the characteristic subject to change designation.

Description

[Detailed Description of the Invention] The present invention relates to a digital graphic equalizer,
The present invention relates to a graphic equalizer that outputs a digital audio signal such as a PCM audio signal by varying the level for each frequency band.

2. Description of the Related Art In recent years, digital signal processors (hereinafter referred to as DSPs)
A digital graphic equalizer has been developed using By using a programmable arithmetic processor such as a DSP, high-speed arithmetic is possible, and
High-precision calculations are possible due to its extensive multiplication functions.

Conventional digital graphic equalizers using DSP require, for example, a CPU
The entire program or the entire coefficients of the digital filter can be switched to specified characteristics at once by switching pages of the memory controlled by the controller.

Problems to be Solved by the Invention The above-mentioned conventional apparatus has the problem of generating buzz noise, which is unpleasant to the ears, because program switching or coefficient switching is performed at the same time.

The present invention provides a digital
The purpose of the present invention is to provide a digital graphic equalizer that does not generate buzz noise and can provide a natural hearing sensation by first converting multiple coefficients of a filter into coefficients with intermediate characteristics and then switching them to coefficients with specified characteristics. do.

Means for Solving the Problems In FIG. 1, the intermediate characteristic coefficient selection section 35 is
The coefficient setting units 6L and 6R are means for selecting coefficient data of an intermediate characteristic between the characteristic before the characteristic change and the characteristic specified to be changed, based on the characteristic change information from the characteristic input unit 12 and the intermediate characteristic coefficient selection unit 35. Coefficient setting means for setting coefficient data corresponding to a plurality of coefficients al-afi of a digital filter according to information of the digital filter; 13R is provided, the incoming digital signal 2) is memorized as a coefficient 'J13, and the digital signal 'g4 is calculated and extracted using the coefficient of 13p, the CPU9
, memory control ff15L, 5p, 4yo14 sex person horn 51
Corresponding to the equalizer characteristic specified in 12, data from the coefficient setting means is rewritten to coefficient memo 1 to 13, 13rq to a coefficient of intermediate characteristic, and further changes! 3A and 3B are examples of rewriting III control means for rewriting data with specified characteristics.

Coefficient setting units 6L, 6R force 1 to DSP 3L correspond to the equalizer characteristics designated by the action characteristic input unit 12.

The coefficient memories 13L and 13R of 3R are once rewritten with coefficients of intermediate characteristics, and then rewritten with coefficients of specified characteristics.

.

Embodiment FIG. 1 shows a block diagram of an embodiment of the equalizer of the present invention. In the same figure, 12 & 1 is a characteristic input section, 15 is a display section, and as shown in FIG. 2, characteristic variable switches SW1. SW
2, . . . SWM, a flat switch SW0, and display element groups 151, 152° . . . 15M are provided. 3L and 3R are DSP for L channel and R channel 1?
This is a DSP for digital filtering that performs digital filter calculations to achieve the equalizer characteristics set in the characteristic input section 12, and has internal coefficient memories 13L, 13R, program ROM 14, 14R, etc.

FIG. 3 shows a concrete block system diagram of DSP3L and 3R. In the figure, the multiplexer (MLJX) program counter (PC>, stack, data memory page
The pointer (OP), auxiliary register, auxiliary register pointer (ARP), shift circuit, etc. are not directly related to the present invention (1), so a detailed explanation will be omitted. The performance speed is approximately 10 to 100 times that of the CPU.Part of the calculation is performed using an FIR digital filter.
(: ~ There are about 100 steps, and the number of steps is not limited to 1 non-circle WJ (1/44.1 kHz2423iis), so high-speed calculation is possible.
f It can be effectively used as an FIR digital filter with a fixed number of taps (n) having the configuration shown in FIG.

In FIG. 3, a program to be executed by the program ROM 14 & the DSP and data such as the multiplication coefficients at to a1 are stored in advance, and these data are transmitted via the program bus 26 to the controller 27 and the program bus 2.
6 and the data node 28 to the multiplier 24 and the like. Further, the controller 27 is supplied with a clock signal (CLKIN>) from an external oscillator (not shown) 1.

Returning to FIG. 1 again, the same signal processing is performed on the digital audio signals of the left and right channels, so the first channel will be mainly explained.

The sample 1 input to the input terminal 1 is arranged alternately for each non-period, and the digital audio signal of each channel 1 of R (a (Fig. 5 (A)) & Niche circuit 2, 2R (Fig. 6) ) while r timing control c, d
((C) ID in the same figure)) is supplied to the latch circuits 2L and 2R. As a result, 1 latch circuit 2L (2R
)4, digital audio signal a/)X, L (R) Channel 11 only digital audio signals are extracted and output.

On the other hand, the interrupt circuits 16L and 16R (Fig. 7) are connected to the DSP3
This is a circuit for setting data transfer timing to L and 3R. That is, DSP3L.

The sampling frequency of the digital audio signal taken into 3R is 44.1 kHz, while DSP3L.

Since the machine cycle of 3R is approximately 20MHz, the interrupt circuits 16L and 16R interrupt the DSP3L.

DSP3L at a convenient timing for 3R.

Data is being imported into 3R.

The interrupt circuits 16L and 16R are as shown in FIG.
It is composed of a NOR circuit 29 and a D flip 70 tube 30.31. Here, a reset signal (πMeishin@) generated by turning on a reset switch (not shown) (usually shared with a power switch) is connected to one input terminal of the NOR circuit 29 via a terminal 32. will be supplied.

This reset signal is a signal for returning the D flip 70 knob 30 to its initial state. Further, the other input terminal of the NOR circuit 29 receives a data enable signal (DEN signal @) e as shown in FIG. 5(E) or (F) output from the controller 27 shown in FIG. , f
is supplied.

The D flip-flop 30 has its data input terminal (D terminal) grounded, and its clear (CL) terminal is supplied with the output signal of the NOR circuit 29. Further, the signal C or d is supplied to the clock (CK) terminal. Therefore, a signal synchronized with the signal C or d is output from the Q terminal of the flip-flop 30, and the flip-flop 31
is supplied to the data input terminal (D terminal) of.

The D flip-flop 31 receives a clock signal (C
LKOUT signal) is supplied. Therefore, D flip 7
QQ of 0 Tsubu 31? The I10 branch control signal (810 signal) output to the controller 27 in the DSP3L, 3R is synchronized with the above CLKOUT signal, and an interrupt occurs at the falling time of the CLKOUT signal, while an 810 signal is output at the falling time of the DEN signal. The signal is reset (ie, becomes high level).

As shown in FIG. 6, the latch circuits 2L and 2R include D flip-flops FIs to FII6. It is composed of inverters 11 and 12 and gate circuits GI+ to GIIG. here,
Each bit of the 16-bit digital audio signal a supplied from the input terminal 1 is input to the D flip 70 tube FI+-.
It is separately supplied to the D terminal of FI+s. On the other hand, the signal C or d is inputted via the inverter 11 to the respective G terminals of the D flip 7O tubes FI+ to FII6. As a result, the Q output terminal of the D flip-flop FI+ and FIz
~ From each extension output terminal of FI+6 as described above or R
Only the digital audio signal of one of the channels is extracted and supplied to the input terminals of the gate circuits GI+ to GI+s.

The DEN signal e or f is supplied as a gate signal to the other input terminal of the gate circuit G1+=Gly6 via the inverter I2. Therefore, at the falling time tl, ts, etc. of the DEN signal e, the latch circuit 2L to the DSP 3
The L channel digital audio signal is output to the L channel, and the R channel digital audio signal is output from the latch circuit 2R to the DSP 3R at the fall time of the DEN signal f, such as 'j3.17. Note that only the most significant bit (MSB) of the 16-bit digital audio signal is inverted and
is converted to the complement form and output.

The digital audio signal of the L channel is fetched and stored at a predetermined address in the coefficient memory 13 shown in FIG. 3 at time t1. Thereafter, a multiplier 24 uses the digital audio data and the multiplication coefficients a and X set in the coefficient memory 13.
aT+ is multiplied and the result is sent to the logic operation circuit (ALtJ) 33 and accumulator (ACC) shown in the third figure.
)34.

Next, switching of equalizer characteristics will be explained. When switching the equalizer characteristics, the coefficient data corresponding to the coefficients a1 to aTl of the digital filters that substantially constitute the DSPs 3L and 3R are switched, and this switching operation is controlled by the CPU 9r and C in the control D18.
PU9 is ROM10. It is configured to operate according to the flowchart shown in FIG. 8 based on the control signal from RΔM11.

A case where the equalizer characteristic shown in FIG. 9 is changed from + to 2 by operating a predetermined switch of the characteristic input section 12 will be described. In the characteristic, 1 is a coefficient of the FIR digital filter shown in FIG. 4, as shown in FIG.

The memory map of 6R is as shown in FIG. 11(A), and the characteristics of 2 are as shown in FIG. 10(B) and FIG. 11(B). Assuming that the predetermined period is one sampling period, the coefficient data a1 (6-1) at address O shown in FIG. Then, the coefficient data is once rewritten to coefficient data having an intermediate characteristic according to the level difference between characteristic 1 and characteristic 2, and is stored in the coefficient memories 13L and 13R of the DSPs 3L and 3R. Similarly, in the next sampling, the coefficient data a2 (6-2) changes to the characteristic +
The coefficient data a2 (132) having an intermediate characteristic corresponding to the level difference between the coefficient data aTl and the coefficient data aTl is subsequently rewritten by 1 at a predetermined period.

The intermediate characteristic is set according to the level difference. For example, if the characteristic between 1 and 2 is 9", the first intermediate characteristic is 6cE, and the second intermediate characteristic is 3". For example, if the number is 12, the first intermediate characteristic is 9d3. The second intermediate characteristic is set to 6 outputs, and the third intermediate characteristic is set to 3 cE, each of which is divided into four characteristics.

Finally, the coefficient data a shown in Figure 11 (B) of 2 in the characteristic
+ (13-1) to ay+ (13Tl).

In this case, in FIG. 12, the memory control units (address counters) 5L and 5R are
R to decoder 17.1B, gate 19.20 (or 2
1) and the control signal from the intermediate characteristic coefficient selection unit 35, the coefficient data al,
a2.

...al is sequentially rewritten. Gate 20 or 21 is selected by the MSB output of memory control section 5L (5R). In this way, the coefficient data a, Xa, are sequentially rewritten in the coefficient memory 13L (13R), and the areas 13-1 to 13-n of the common coefficient memory 13L (13R) where one gram is being executed are Intermediate characteristic data can be easily rewritten once or multiple times.

When the sampling frequency is 44.1 kHz, one sample weighs about 22.7 g, and when there are 100 samples at one time, switching is performed quickly as 22.7 JlsX 100=2.2713.

The characteristics are then switched during each switching section.

In this case, the flat switch 5 of the characteristic input section 12
It is detected that Wo (sets the level display to zero) is not pressed (step 100 in Figure 8), and band I (second
In the figure, the coefficient setting values in the M band configuration of I=1 to M are read from bands 1 to M, and the coefficients are rewritten (steps 101 to 104).

Here, when it is detected that the switches SW + to SWM have been newly operated (step 105), a coefficient corresponding to this is calculated or selected from the ROM 10 (
Step 106), and the intermediate characteristic coefficient selection unit 35 selects the coefficient data of the intermediate characteristic according to the level difference between 1 and 2 for the characteristic (Step 107), and as described above, the coefficient data of the intermediate characteristic is selected as the coefficient. The coefficients are written into the setting sections 6L and 6R (step 108). In this case, the characteristic has 1
If the difference between Six coefficient data of intermediate characteristics are extracted and written to the coefficient setting section 6L (6R) (step 108
). Next, the number of times flag is set to “1” (step 1
09), return to step 100 again, and step 100~
The same operation as above is performed up to step 105, and it is determined that the previous characteristic change has not been completed yet (step 11).
0), 3 dB coefficient data of the second intermediate characteristic is written (step 108), then the number of times flag is set to "2" (step 109), and the process returns to step 100 again to perform the same operation as above. is performed, and finally coefficient data of "O" is written (step 108), and the number of times flag becomes "3".
” and the process ends (step 109).

In this way, when switching from characteristic 1 to characteristic 2, it changes to characteristic 1, changes to characteristic 2 after passing through the intermediate characteristic, so the change in the output signal is small, and there is no buzz noise when switching. Moreover, a natural hearing sensation can be obtained.

On the other hand, if the flat switch SWo is pressed (steps 100 and 111), a flat coefficient is selected (step 112) and written to the coefficient setting sections 6L and 6R (
Step 113).

In this way, when the equalizer characteristics are set in the characteristic input section 12, the coefficients a, to aTl of the digital filters are sequentially switched at a predetermined period, and the DSP 3L.

In the multiplier 24 in 3R, the digital audio signal data coefficients a1 to an are multiplied by δ1.

The operation result data is supplied to latch circuits 4L and 4R (FIG. 13). Latch circuits 4L and 4R are output data memories 22L and 22R, and output timing adjustment memory 23.
It is composed of L and 23R. Output data memory 2
2L is a D flip 70 tube FL+ as shown in Figure 13.
~FL+s and an inverter IL+. Here, each bit of the above-mentioned 16-bit calculation result data is supplied to the 0 terminals of the D flip 70 blocks FL+ to FLI6, respectively, and the CKra child is supplied with the data from the controller 27 in DSPaL as shown in FIG. 5(G). The octopus write enable signal (WE multiplication signal g is supplied via the inverter IL+. Therefore, the above calculation result data is output to the D flip 70 tubes FL+ to F at time t6 when the WE multiplication signal rises.
It is taken into LI6 and output from its Q terminal.

The output timing adjustment memory 23L has 70 D flips, 7FOL+-FOL+6. Invar 91L2.1L3
and gate circuits GL+-GL+s.

Here, the calculation result data is the D flip-flop FL.
+- D flip-flop F from each Q terminal of FLI6
OL+ is supplied to the respective D terminals of -FOl and +6.

On the other hand, the output timing adjustment pulse b as shown in FIG.
Supplied to each GK terminal of OL+~FOL+s,
And gate circuits GL+ to G via inverter IL3
It is supplied to one input terminal of L16. The above calculation result data i (FIG. 5(I)) is applied to the D flip-flop GL+ after the falling time of the signal S (time ts shown in FIG. 5).
are outputted from the output terminal 7 from the Q terminal of and the σ terminal of GL2 to GLI6 via gate circuits GL+ to GL+s, respectively.

In this way, the DSP3L takes in data at time 1+, outputs the calculation result of the previous data at time t2 immediately after that, takes in the next data at the next time t5, and
At falling time t6 of the E times signal, the calculation result of the data taken in at time t1 is written into the output data memory 22L, and the calculation result data is outputted from the terminal 7 at timing t9 synchronized with the subsequent signal a. Ru.

On the other hand, the R channel digital audio signal is also processed in the same way as above in the DSP 3R, the output data memory 22R, and the output timing adjustment memory 23R. This operation is easier to understand than the operation of the L channel, so its explanation will be omitted.

Note that the DSP is an embodiment of a programmable digital signal calculation means.

Further, the digital filter is not limited to an FIR digital filter, but may be an IIR digital filter or a composite filter of an FIR digital filter and an IIR digital filter.

Furthermore, switching the characteristics of the digital filter is also effective between different programs. For example, switching between configurations with different tap numbers n of FIR filters,
It is also useful in switching from a filter to an IIR filter and vice versa, and also in switching between different types of characteristics in an IIR filter. Furthermore, the channel configuration is not limited to two channels.

In addition, although the digital input and digital output systems have been described, the system is not limited to this.
Of course, by using a D converter and a DA converter for output, an analog input and analog output system can be constructed.

Effects of the Invention According to the digital graphic equalizer of the present invention, the plurality of coefficients of the digital filter are once changed to coefficients of an intermediate characteristic and then further switched to coefficients of a designated characteristic in accordance with the equalizer characteristic variable operation. , compared to conventional systems in which the entire program or coefficients are switched at once by switching pages, there is no buzz noise.
It has features such as being able to provide a natural hearing sensation.

[Brief explanation of drawings]

1 and 2 are block system diagrams and partial schematic diagrams of an embodiment of the equalizer of the present invention, respectively. FIG. 3 is a block system diagram of a DSP used for the equalizer of the present invention.・A schematic diagram of the filter, FIG. 5 is a flowchart for explaining the operation of the equalizer of the present invention, and FIGS. 6 and 7 are
The figure is a specific circuit diagram of a part of the equalizer of the present invention, Figure 8 is a flow chart for explaining the operation of the CPU used in the equalizer of the present invention, Figure 9 is an equalizer characteristic diagram, and Figure 10 is an FIR
Diagram for explaining coefficients of a digital filter, No. 11
The figure shows the memory map of the coefficient setting section and coefficient memory, 12th
The figure is a specific block diagram of the vicinity of the coefficient setting section and the memory control section, and FIG. 13 is a specific circuit diagram of a part of the equalizer of the present invention. 1...Digital audio signal input terminal, 2L, 2R. 4L, 4R...Latch circuit, 3L, 3R...DSP
, 5L, 5R...Memory control unit, 6L, 6R...Coefficient setting unit, 7...Output terminal, 8...Control unit, 9...
・CPU, 12...Characteristics input section, SW + ~ SWM
, SWo... switch, 13L, 13R... coefficient memory, 14L. 14R...Program ROM, 15...Display section, 3
5... Intermediate characteristic coefficient selection section. Patent applicant: Victor Japan Co., Ltd. Figure 3 Figure 4 Figure 5 □ Hsu Ming

Claims (1)

[Claims] A characteristic input section for specifying a desired equalizer characteristic; and an intermediate characteristic for selecting coefficient data of an equalizer characteristic intermediate between the equalizer characteristic before characteristic change and the equalizer characteristic specified for change, based on characteristic change information from the characteristic input section. coefficient selection means; coefficient setting means for setting coefficient data corresponding to each of the plurality of coefficients of the digital filter according to information from the characteristic input section and the intermediate characteristic coefficient selection means; A rewritable coefficient memory corresponding to the coefficient is provided, a digital signal calculation means for calculating and extracting an incoming digital signal using the coefficient of the coefficient memory, and a digital signal calculation means for calculating and extracting an incoming digital signal using the coefficient of the coefficient memory, and a digital signal calculation means for calculating and extracting an incoming digital signal using the coefficient of the coefficient memory, and a digital signal calculation means for calculating and extracting an incoming digital signal with the coefficient of the coefficient memory, and a digital signal calculation means for calculating and extracting the incoming digital signal using the coefficient of the coefficient memory. Correspondingly, the digital apparatus further comprises a rewriting control means for once rewriting the coefficient data from the coefficient setting means to the coefficient memory with the coefficient data of the intermediate equalizer characteristic, and then rewriting the coefficient data with the characteristic specified for change.・
Graphic equalizer.