JPH04216126A - Serial-parallel multiplier - Google Patents

Abstract

PURPOSE:To make the hardware constitution of a serial-parallel multiplier simply expandable even when the bit numbers of a multiplier and multiplicand increase. CONSTITUTION:By providing (m+1)-stage arithmetic units UO-Um of the same constitution and a control circuit C and only setting the gate Gi of the arithmetic unit Ui of the i-th stage to an open state, the product of A and B respectively expressed by A=A0+A1X2<n>+...+AmX2<mn> and B=B0+B1X2<n>+...BmX2<mn> is obtained in such a way that partial products of the A0, A1,..., Am and Bi are computed by means of the multipliers Mo-Mm and, after holding the partial products in intermediate registers RMO-RMm and the sum of the partial products in output registers RCO-RCm, the arithmetic operation and holding are successively executed on each i=0-m.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a series-parallel multiplier.

0002

2. Description of the Related Art Multipliers include parallel types, series types, and series-parallel types.

Parallel multipliers can perform multiplication at high speed in one cycle, but the circuit size becomes large. On the other hand, although the serial multiplier has a smaller circuit scale, it requires shifting the multiplier by one bit, cumulatively adding the partial products, and repeating this process for all bits of the multiplier, so the multiplication speed is slow.

On the other hand, a series-parallel type multiplier has the advantage that its circuit scale is smaller than that of a parallel type, and its multiplication speed is faster than that of a serial type.

[0005]

However, the hardware configuration of conventional serial, parallel, and series-parallel multipliers cannot be simply expanded when the number of bits of the multiplier and multiplicand increases.

SUMMARY OF THE INVENTION In view of these problems, an object of the present invention is to provide a series-parallel multiplier whose hardware configuration can be simply expanded even when the number of bits of the multiplier and multiplicand increases. be.

[0007]

[Means for Solving the Problems and Their Effects] FIG. 1 shows the basic configuration of a series-parallel multiplier. This series-parallel multiplier has A0, A1, ..., Am and B0, B1, ...,
Bm is each represented by n bits, A=A0+A1×
2n +...+Am×2mn, B=B0+B1×2n
It calculates the product of A and B expressed as +...+Bm×2mn, and includes m+1 stages of arithmetic units U0 to Um of the same configuration and a control circuit C, and Operate as digits.

The i-th stage arithmetic unit Ui includes an n-bit first input register RAi in which Ai is stored, an n-bit second input register (RBi) in which Bi is stored,
A gate Gi is opened or closed in response to an opening/closing control signal, and one input terminal is connected to the output terminal of a first input register RAi via the gate Gi, and the other input terminal is connected to a second input register RBi. a multiplier Mi to which the output terminal of is connected and calculates the product of the values supplied to both input terminals;
A 2n-bit intermediate register RMi that is connected to the output terminal of the multiplier Mi and holds the product as a partial product in response to a first holding control signal, and a value shifted from the arithmetic unit in the previous stage and the intermediate register. A digit addition circuit ADi that calculates the sum of partial products of the same digit with respect to the value held in RMi, and shifts the value of a digit different from that digit to the next stage of the calculation unit.
and an output register RCi that holds the sum of the partial products in response to a second holding control signal.

Further, the one input terminals of the multipliers of each arithmetic unit are connected to each other, and the digit addition circuit is connected between the arithmetic units so that the carry is performed.

The control circuit C supplies opening/closing signals to the gates G0 to Gm to open only the gate Gi of the i-th stage arithmetic unit Ui, thereby controlling A0, A1, . . .
Let the multipliers M0 to Mm calculate the partial products of Am and Bi,
A first holding control signal is supplied to intermediate registers RM0 to RMm to cause the intermediate registers RM0 to RMm to hold the partial products, and a second holding control signal is supplied to output registers RC0 to RCm to store the sum of the partial products. The output registers RC0 to RCm are held, and the calculation and the holding are performed sequentially for each of i=0 to m.

According to the serial-parallel multiplier having the above configuration, in order to increase the number of bits of the multiplier and the multiplicand, it is sufficient to simply increase the number of stages of arithmetic units having the same configuration, so the hardware configuration can be simply expanded. be able to. In addition, instead of performing a shift operation in 1-bit units like a serial multiplier, n
Since shift (parallel data transfer) is performed between arithmetic units on a bit-by-bit basis, high-speed arithmetic is possible.

In the series-parallel multiplier having the above configuration, for example, the a side terminal is connected to the multiplier side terminal of the gate, the b side terminal is connected to the terminal for outputting the shift signal, and the common terminal is connected to the multiplier side terminal of the gate. A changeover switch means is connected to the multiplier side terminal of the gate of the next-stage arithmetic unit and connects the common terminal to either the a-side terminal or the b-side terminal in accordance with a switching control signal SC. , the control circuit C supplies the changeover control signal to the changeover switch means to calculate the partial product with the changeover switch means set to the a side, and supplies the changeover control signal to the changeover switch means. Then, with the changeover switch means set to the b side, the sum of the partial products is calculated and the shift is performed.

In this configuration, the connection between the terminals of each gate Gi on the multiplier Mi side and the connection between the digit adder circuits can be combined into one connection between the arithmetic units, so that the connection between the arithmetic units becomes easier.

The digit addition circuit ADi includes, for example, a first adder that calculates the sum of the value of the upper n bits of the intermediate register and the digit of the next higher digit from the arithmetic unit; and a second adder that calculates the sum of the value of the lower n bits of and the contents of the output register, the output of the first adder is held in the output register, and the second
The output of the adder is configured to be supplied as a carry to the next stage arithmetic unit.

In this configuration, one digit is n bits and m
The upper m+1 digits of the product of A and B, which are +1 digits, can be computed at the highest speed by a series-parallel multiplier using the smallest number of m+1 stages of arithmetic units. This configuration is primarily used for floating point multiplication.

The digit addition circuit ADi includes, for example, a first adder that calculates the sum of the value of the lower n bits of the intermediate register and the carry of the next lower digit from the arithmetic unit; and a second adder that calculates the sum of the value of the upper n bits of and the contents of the output register, the output of the first adder is held in the output register, and the second
The output of the adder is configured to be supplied as a carry to the arithmetic unit at the next stage.

In this configuration, one digit is n bits and m
The lower m+1 digits of the product of A and B, which are +1 digits, can be computed at the highest speed by a series-parallel multiplier using the smallest number of m+1 stage arithmetic units. This configuration is mainly used when the values of A and B are relatively small.

[0018]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 2 shows a total of 3 bytes of values stored in registers 1, 2, and 3 of 1 byte each, and a total of 3 bytes of values stored in registers A, B, and C of 1 byte each. FIG. 3 is an explanatory diagram of a multiplication method, showing the relationship between a partial product that is a product in bytes and a product obtained by adding the partial products with each byte as one digit. In the figure, for example, 3CH indicates the upper 8 bits of the product of the value stored in register 3 and the value stored in register C, and 3CL indicates the lower 8 bits of this product. The same applies to other partial products.

The first embodiment below shows a series-parallel multiplier that calculates the upper three bytes of a product, and the second embodiment shows a series-parallel multiplier that calculates the lower three bytes of a product. The first embodiment is mainly used for multiplication of floating point numbers, and the second embodiment is used to obtain the lower three bytes of the product of 1 to 3 bytes x 1 to 3 bytes.

(1) First Embodiment FIGS. 3 to 9 show the state of the serial-parallel multiplier in each clock cycle. FIG. 10 is a timing chart showing the operation of this series-parallel multiplier.

In this serial-parallel multiplier, three arithmetic units 10, 20, and 30 having the same configuration are arranged side by side, and adjacent arithmetic units are connected by a 1-byte data bus.

The arithmetic unit 10 includes the registers 1 and A described above, and components 11-17. register 1
is connected to one input terminal of the multiplier 11 via the gate 12, and the register A is connected to the other input terminal of the multiplier 11. The output terminal of the multiplier 11 is connected to the input terminal of a 2-byte register 13. The register 13 consists of an upper byte register 13H and a lower byte register 13L. The output terminal of the upper byte register 13H is connected to one input terminal of the adder 14, and the other input terminal of the adder 14 is connected to the terminal of the gate 12 on the multiplier 11 side. The output terminal of the adder 14 is connected to one input terminal of the adder 16 via the register 15, and the other input terminal of the adder 16 is connected to the output terminal of the lower byte register 13L. Adder 16
The output terminal of is connected to the b-side terminal of the bidirectional selector 17. The bidirectional selector 17 switches and connects the common terminal to the a side or the b side, and its a side terminal is connected to the terminal of the gate 12 on the multiplier 11 side.

The carry output terminal of the adder 16 is connected to the carry input terminal of the adder 14.
A carry C11 is supplied to the adder 14 from the adder 14.

Further, the gate 12 is controlled to open and close by an open/close signal S1, and the bidirectional selector 17 is controlled to switch by a switching signal SC. Register 13 holds input data at the rising timing of clock φ1, and register 15 holds input data at the rising timing of clock φ0.

Component 2i (i=1
~7, and so on. ) and component 3 of the arithmetic unit 30
i corresponds to the component 1i of the arithmetic unit 10. Furthermore, the open/close signal S2 and carry C21 in the arithmetic unit 20 and the open/close signal S3 and carry C31 in the arithmetic unit 30 correspond to the open/close signal S1 and carry C11 in the arithmetic unit 10, respectively.

Between the arithmetic unit 10 and the arithmetic unit 20, a common terminal of a bidirectional selector 17 is connected to an a-side terminal of a bidirectional selector 27. Further, the carry output terminal of the adder 24 is connected to the first input terminal of the adder 14.
carry C22 from adder 24
is supplied to the adder 14. Between the arithmetic unit 20 and the arithmetic unit 30, a common terminal of a bidirectional selector 27 is connected to an a-side terminal of a bidirectional selector 37. Further, between the arithmetic unit 30 and the arithmetic unit 10, the carry output terminal of the adder 34 is connected to the carry input terminal of the adder 16, and the carry C3 from the adder 34 is connected to the carry output terminal of the adder 34.
2 is provided to adder 16.

Next, the operation of the series-parallel multiplier constructed as described above will be explained.

As shown in FIG. 10, the time from the rise of clock φ0 to the rise of the next clock φ1 is referred to as clock cycles 1a, 2a, 3a, and 4a, and the time from the rise of clock φ1 to the rise of the next clock φ0 Let these be clock cycles 1b, 2b, and 3b. FIGS. 3 to 9 show clock cycles 1a,
The conditions at 1b, 2a, 2b, 3a, 3b and 4a are shown.

■Clock cycle 1a (FIG. 3) The gates 12 and 22 are closed by the open/close signals S1 and S2, the gate 32 is opened by the open/close signal S3, and the bidirectional selector 17, 27 and 37 are switched to the a side, and registers 15, 25, and 35 are cleared by a clear signal (not shown).

As a result, the contents of register 3 are supplied to one input terminal of multiplier 31, and the contents of register 3 are supplied to one input terminal of multiplier 31.
and is supplied to one input terminal of the multiplier 21 via the bidirectional selector 27, and further supplied to one input terminal of the multiplier 11 via the bidirectional selector 17. Then, the product of the contents of register 3 and the contents of register C is multiplier 31
The multiplier 21 calculates the product of the contents of register 3 and the contents of register B, and the multiplier 11 calculates the product of the contents of register 3 and the contents of register A.

■Clock cycle 1b (Fig. 4) The calculation results of multipliers 11, 21, and 31 are held in registers 13, 23, and 33, respectively, at the rising timing of clock φ1, and gate 32 is closed by opening/closing signal S3. be put into a state. Further, the bidirectional selectors 17, 27, and 37 are switched to the b side by the switching signal SC.

As a result, the sum of the content 3AH of the upper byte register 13H, the carry C11, and the carry C22 is calculated by the adder 14, and the sum of the content 3AL of the lower byte register 13L, the content 0 of the register 15, and the carry C32 is calculated. The adder 16 calculates the result, and the adder 24 calculates the sum of this calculation result, the contents 3BH of the upper byte register 23H, and the carry C21. Also, lower byte register 2
The sum of the content 3BL of 3L and the content 0 of the register 25 is calculated by the adder 26, and the sum of this calculation result, the content 3CH of the upper byte register 33H, and the carry C31 is calculated by the adder 3.
4, the contents of the lower byte register 33L 3CL
The adder 36 calculates the sum of 0 and the content 0 of the register 35.

(2) Clock cycle 2a (FIG. 5) The calculation results of adders 14, 24 and 34 are held in registers 15, 25 and 35, respectively, at the rising edge of clock φ0. Also, the gate 2 is activated by the open/close signal S2.
2 is opened, and the bidirectional selectors 17, 27, and 37 are switched to the a side by the switching signal SC.

As a result, the contents of register 2 are supplied to one input terminal of multiplier 21 via gate 22, and are also supplied to one input terminal of multiplier 11 via gate 22 and bidirectional selector 17. The signal is supplied to one input terminal of the multiplier 31 via the gate 22 and the bidirectional selector 27. Then, the multiplier 11 calculates the product of the contents of register 2 and the contents of register A, the product of the contents of register 2 and the contents of register B is calculated by the multiplier 21, and the product of the contents of register 2 and the contents of register C is calculated. A multiplier 31 calculates the product with the contents.

■Clock cycle 2b (Fig. 6) The calculation results of multipliers 11, 21, and 31 are held in registers 13, 23, and 33, respectively, at the rising timing of clock φ1, and gate 22 is closed by opening/closing signal S2. be put into a state. Further, the bidirectional selectors 17, 27, and 37 are switched to the b side by the switching signal SC.

As a result, the sum of the content 2AH of the upper byte register 13H, the carry C11, and the carry C22 is calculated by the adder 14, and the sum of the content 2AL of the lower byte register 13L, the content 3AH of the register 15, and the carry C32 is calculated by the adder 14.
The adder 16 calculates the sum of this calculation result, the content 2BH of the upper byte register 23H, and the carry C21, and the adder 24 calculates the sum. In addition, the content 2BL of the lower byte register 23L and the content 3AL+3 of the register 25
The sum with BH is calculated by the adder 26, and this calculation result, the content 2CH of the upper byte register 33H, and the carry C31
The sum is calculated by the adder 34, and the lower byte register 3
Contents of 3L 2CL and contents of register 35 3BL + 3CH
The adder 36 calculates the sum.

(2) Clock cycle 3a (FIG. 7) The calculation results of adders 14, 24 and 34 are held in registers 15, 25 and 35, respectively, at the rising edge of clock φ0. Also, gate 1 is activated by opening/closing signal S1.
2 is opened, and the bidirectional selectors 17, 27, and 37 are switched to the a side by the switching signal SC.

As a result, the contents of register 1 are supplied to one input terminal of multiplier 11 via gate 12, and are also supplied to one input terminal of multiplier 21 via gate 12 and bidirectional selector 17. It is further supplied to one input terminal of the multiplier 31 via the bidirectional selector 27. Then, the product of the contents of register 1 and the contents of register A is calculated in multiplier 11, the product of the contents of register 1 and the contents of register B is calculated in multiplier 21, and the product of the contents of register 1 and register C is calculated. A multiplier 31 calculates the product with the contents.

■Clock cycle 3b (Fig. 8) The calculation results of multipliers 11, 21, and 31 are held in registers 13, 23, and 33, respectively, at the rising timing of clock φ1, and gate 12 is closed by opening/closing signal S1. be put into a state. Further, the bidirectional selectors 17, 27, and 37 are switched to the b side by the switching signal SC.

As a result, the sum of the content 1AH of the upper byte register 13H, the carry C11, and the carry C22 is calculated by the adder 14, and the sum of the content 1AL of the lower byte register 13L, the content 2AH of the register 15, and the carry C32 is calculated by the adder 14.
The adder 16 calculates the sum of this calculation result, the contents 1BH of the upper byte register 23H, and the carry C21, and the adder 24 calculates the sum. In addition, the content 1BL of the lower byte register 23L and the content 3AH+2 of the register 25
The sum of AL+2BH is calculated in the adder 26, and the sum of this calculation result, the content 1CH of the upper byte register 33H, and the carry C31 is calculated in the adder 34, and the sum of the content 1CH of the lower byte register 33L and the content 3AL of the register 35 is calculated.
The adder 36 calculates the sum of +3BH+2BL+2CH.

(2) Clock cycle 4a (FIG. 9) The calculation results of adders 14, 24 and 34 are held in registers 15, 25 and 35, respectively, at the rising edge of clock φ0.

In this way, the upper three bytes 1AH, 2 of the product of the three byte values stored in registers 1, 2, and 3 and the three byte values stored in registers A, B, and C are
AH+1AL+1BH, 3AH+2AL+2BH+1B
L+1CH are held in registers 15, 25 and 35, respectively.

(2) Second Embodiment FIGS. 11 to 17 show the state of the series-parallel multiplier in each clock cycle. FIG. 18 is a timing chart showing the operation of this series-parallel multiplier.

Similar to the first embodiment, this series-parallel multiplier includes three arithmetic units 10A and 20A having the same configuration.
and 30A are arranged side by side, and adjacent arithmetic units are connected by a 1-byte data bus.

The components in the arithmetic units 10A, 20A and 30A are respectively the arithmetic units 10, 2 in FIG.
It is arranged in a left-right mirror image relationship with the components in 0 and 30. That is, the arithmetic unit 10A has the following functions except that the output terminal of the lower byte register 13L is connected to one input terminal of the adder 14, and the output terminal of the upper byte register 13H is connected to one input terminal of the adder 14. , the same as the arithmetic unit 10. Arithmetic unit 20A, 30A
The same applies to

The carry output terminal of the adder 14 is connected to the carry input terminal of the adder 16.
A carry C11 is supplied to the adder 16 from the adder 16. Carry C21 in the arithmetic unit 20A and the arithmetic unit 30
Carry C31 in A corresponds to carry C11 in arithmetic unit 10A.

Arithmetic unit 10A and arithmetic unit 20A
Between the arithmetic unit 20A and the arithmetic unit 30A, the common terminal of the bidirectional selector 27 is connected to the a-side terminal of the bidirectional selector 17. Connected to the a side terminal. Further, between the arithmetic unit 30A and the arithmetic unit 10A, the carry output terminal of the adder 36 is connected to the carry input terminal of the adder 14, and the carry C32 from the adder 36 is supplied to the adder 14. .

Next, the operation of the series-parallel multiplier configured as described above will be explained.

As in the first embodiment, as shown in FIG. 18, the time from the rise of clock φ0 to the rise of the next clock φ1 is divided into clock cycles 1a, 2a, 3.
a, 4a, and the time from the rising edge of clock φ1 to the rising edge of the next clock φ0 is clock cycle 1.
b, 2b, and 3b. Figures 11 to 17 show clock cycles 1a, 1b, 2a, 2b, 3a, 3, respectively.
b and 4a are shown.

■Clock cycle 1a (FIG. 11) The gates 22 and 32 are closed by the open/close signals S2 and S3, the gate 12 is opened by the open/close signal S1, and the bidirectional selector 17, 27
and 37 are switched to the a side, and registers 15, 25 and 35 are cleared by a clear signal (not shown).

As a result, the contents of register 1 are supplied to one input terminal of multiplier 11, and the contents of register 1 are supplied to one input terminal of multiplier 11.
and is supplied to one input terminal of the multiplier 21 via the bidirectional selector 27, and further supplied to one input terminal of the multiplier 31 via the bidirectional selector 37. Then, the product of the contents of register 1 and the contents of register A is multiplier 11
The multiplier 21 calculates the product of the contents of register 1 and the contents of register B, and the multiplier 31 calculates the product of the contents of register 1 and the contents of register C.

■Clock cycle 1b (Fig. 12) The operation results of multipliers 11, 21, and 31 are stored in registers 13, 23, and 31, respectively, at the rising edge of clock φ1.
33, and the gate 32 is closed by the opening/closing signal S3. Further, the bidirectional selectors 17, 27, and 37 are switched to the b side by the switching signal SC.

As a result, the adder 34 calculates the sum of the contents 1CL and 0 of the lower byte register 33L, and the sum of the contents 1CH of the upper byte register 33H, the contents 0 of the register 35, and the carry C31 is calculated by the adder 36. The adder 24 calculates the sum of this calculation result and the content 1BL of the lower byte register 23L. Further, the sum of the content 1BH of the upper byte register 23H, the content 0 of the register 25, and the carry C21 is calculated by the adder 26, and the sum of this calculation result, the content 1AL of the lower byte register 13L, and the carry C32 is calculated by the adder 14. The adder 16 calculates the sum of the content 1AH of the upper byte register 13H, the content 0 of the register 15, and the carry C11.

(2) Clock cycle 2a (FIG. 13) The calculation results of adders 14, 24 and 34 are held in registers 15, 25 and 35, respectively, at the rising edge of clock φ0. Further, the gate 22 is opened by the opening/closing signal S2, and the bidirectional selectors 17, 27, and 37 are switched to the a side by the switching signal SC.

As a result, the contents of register 2 are supplied to one input terminal of multiplier 21 via gate 22, and are also supplied to one input terminal of multiplier 11 via gate 22 and bidirectional selector 27. The signal is supplied to one input terminal of the multiplier 31 via the gate 22 and the bidirectional selector 37. Then, the multiplier 11 calculates the product of the contents of register 2 and the contents of register A, the product of the contents of register 2 and the contents of register B is calculated by the multiplier 21, and the product of the contents of register 2 and the contents of register C is calculated. A multiplier 31 calculates the product with the contents.

■Clock cycle 2b (Fig. 14) The operation results of multipliers 11, 21, and 31 are stored in registers 13, 23, and 31, respectively, at the rising edge of clock φ1.
33, and the gate 22 is closed by the opening/closing signal S2. Further, the bidirectional selectors 17, 27, and 37 are switched to the b side by the switching signal SC.

As a result, the sum of the content 2CL of the lower byte register 33L and 0 is calculated in the adder 34, and the sum of the content 2CH of the upper byte register 33H, the content 1CL of the register 35, and the carry C31 is calculated in the adder 36. This calculation result and the contents 2B of the lower byte register 23L are
The sum with L is calculated by the adder 24. In addition, the content 2BH of the upper byte register 23H and the content 1B of the register 25
The adder 26 calculates the sum of L+1CH and the carry C21, and the adder 14 calculates the sum of this calculation result, the content 2BL of the lower byte register 13L, and the carry C32, and the sum of the content 2AH of the upper byte register 13H and the register 1.
The adder 16 calculates the sum of the contents 1AL+1BH of 5 and the carry C11.

(2) Clock cycle 3a (FIG. 15) The calculation results of adders 14, 24 and 34 are held in registers 15, 25 and 35, respectively, at the rising edge of clock φ0. Further, the gate 32 is opened by the opening/closing signal S3, and the bidirectional selectors 17, 27, and 37 are switched to the a side by the switching signal SC.

As a result, the contents of register 3 are supplied to one input terminal of multiplier 31, and the contents of register 3 are supplied to one input terminal of multiplier 31.
and is supplied to one input terminal of the multiplier 21 via the bidirectional selector 37, and further supplied to one input terminal of the multiplier 11 via the bidirectional selector 27. Then, the product of the contents of register 3 and the contents of register C is multiplier 31
The multiplier 21 calculates the product of the contents of register 3 and the contents of register B, and the multiplier 11 calculates the product of the contents of register 3 and the contents of register A.

■Clock cycle 3b (Fig. 16) The operation results of multipliers 11, 21, and 31 are stored in registers 13, 23, and 31, respectively, at the rising edge of clock φ1.
33, and the gate 32 is closed by the opening/closing signal S3. Further, the bidirectional selectors 17, 27, and 37 are switched to the b side by the switching signal SC.

As a result, the sum of the content 3CL of the lower byte register 33L and 0 is calculated by the adder 34, and the sum of the content 3CH of the upper byte register 33H, the content 2CL of the register 35, and the carry C31 is calculated by the adder 36. This calculation result and the contents 3B of the lower byte register 23L are calculated.
The sum with L is calculated by the adder 24. In addition, the content 3BH of the upper byte register 23H and the content 2B of the register 25
The sum of L+2CH+1CL and carry C21 is added to adder 2.
6, and the result of this operation and the lower byte register 13
Adder 14 calculates the sum of contents 3AL of L and carry C32, and adder 16 calculates the sum of contents 3AH of upper byte register 13H, contents 2AL+2BH+1BL+1CH of register 15, and carry C11.

(2) Clock cycle 4a (FIG. 17) The calculation results of adders 14, 24 and 34 are held in registers 15, 25 and 35, respectively, at the rising edge of clock φ0.

In this way, the lower 3 bytes of the product of the 3-byte values stored in registers 1, 2, and 3 and the 3-byte values stored in registers A, B, and C are obtained.
BH+2BL+2CH+1CL, 3BL+3CH+2C
L and 3CL are held in registers 15, 25 and 35, respectively.

Note that the present invention includes various other modifications.

For example, the configuration of the series-parallel multiplier of the first embodiment and the series-parallel multiplier of the second embodiment may be changed from one configuration to the other by switching and connecting the wiring. In this way, for example, all 6 bytes of the product of 3 bytes x 3 bytes can be obtained by the three arithmetic units 10A. In addition, even if the switching connection is not made, the 6
If one arithmetic unit 10A is used, all six bytes of this product can be obtained.

[0067]

As explained above, according to the series-parallel multiplier according to the present invention, the number of bits of the multiplier and multiplicand can be increased simply by increasing the number of stages of arithmetic units having the same configuration. This has an excellent effect in that the hardware configuration can be simply expanded. Furthermore, since shift operations (parallel data transfer) are performed between arithmetic units in units of n bits without performing shift operations in units of 1 bit as in serial multipliers, there is an effect that high-speed operations are possible.

[0068] Furthermore, if the above changeover switch means is provided,
Between the arithmetic units, the connection between the multiplier-side terminals of each gate and the connection between the digit adder circuits can be combined into one, resulting in the effect that the connection between the arithmetic units is simplified.

In addition, the digit addition circuit includes a first adder that calculates the sum of the value of the upper n bits of the intermediate register and the carry from the arithmetic unit of the next higher digit, and a The configuration includes a second adder that calculates the sum of the value and the contents of the output register, the output of the first adder is held in the output register, and the output of the second adder is used as a carry in the next stage calculation. If configured to be supplied to the unit, the upper m+1 digits of the product of A and B, where each digit is n bits and both are m+1 digits, are processed by a series-parallel multiplier using the smallest number of m+1 arithmetic units. , has the effect of being able to perform calculations at the highest speed.

In addition, the digit addition circuit includes a first adder that calculates the sum of the value of the lower n bits of the intermediate register and the carry from the arithmetic unit of the next lower digit, and a The configuration includes a second adder that calculates the sum of the value and the contents of the output register, the output of the first adder is held in the output register, and the output of the second adder is used as a carry to be used as a carry in the next stage calculation unit. If the configuration is such that the lower m+1 digits of the product of A and B, where each digit is n bits and each is m+1 digits, are supplied, the lower m+1 digits of the product of A and B are processed by the above series-parallel multiplier using the minimum number of m+1 arithmetic units. , has the effect of being able to perform calculations at the highest speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle configuration of a series-parallel multiplier according to the present invention.

[Figure 2] A total of 3 bytes of values stored in registers 1, 2, and 3 of 1 byte each, and register A of 1 byte each.
, B, and C with a total of 3 bytes.

3 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 1a shown in FIG. 10; FIG.

4 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 1b shown in FIG. 10; FIG.

5 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 2a shown in FIG. 10; FIG.

6 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 2b shown in FIG. 10; FIG.

7 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 3a shown in FIG. 10; FIG.

8 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 3b shown in FIG. 10; FIG.

9 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 4a shown in FIG. 10; FIG.

FIG. 10 is a timing chart showing the operation of a series-parallel multiplier.

11 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 1a shown in FIG. 18; FIG.

12 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 1b shown in FIG. 18; FIG.

13 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 2a shown in FIG. 18; FIG.

14 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 2b shown in FIG. 18; FIG.

15 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 3a shown in FIG. 18; FIG.

16 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 3b shown in FIG. 18; FIG.

17 is a circuit diagram of the series-parallel multiplier in the state of clock cycle 4a shown in FIG. 18; FIG.

FIG. 18 is a timing chart showing the operation of a series-parallel multiplier.

[Explanation of symbols]

1-3, A-C, 13, 23, 33, 15, 25, 35
Registers 10, 10A, 20, 20A, 30, 30A Arithmetic units 11, 21, 31 Multipliers 12, 22, 32 Gates 14, 24, 34, 16, 26, 36 Adder 17,
27, 37 Bidirectional selector

Claims (4)

[Claims] [Claim 1] A0, A1, ..., Am and B0,
B1, ..., Bm are each represented by n bits, and A
=A0+A1×2n +...+Am×2mn, B=B
In a series-parallel multiplier that calculates the product of A and B expressed as 0+B1×2n +...+Bm×2mn, m+1 stages of arithmetic units (U0 to Um) with the same configuration and a control circuit (C) are used. , where n bits are one digit, and the i-th stage arithmetic unit (Ui) has an n-bit first input register (RAi) in which the Ai is stored, and an n-bit first input register (RAi) in which the Bi is stored. a two-input register (RBi), a gate (Gi) that is turned into an open state or a closed state in response to an opening/closing control signal, and one input terminal of which the output terminal of the first input register is connected via the gate; The output terminal of the second input register is connected to the other input terminal, and the multiplier (Mi) calculates the product of the values supplied to both input terminals; A 2n-bit intermediate register (RM) holds the product as a partial product in response to a hold control signal.
i), the value shifted from the arithmetic unit in the previous stage, and the value held in the intermediate register, calculate the sum of partial products of the same digit, and calculate the value of the digit different from the digit in the next stage. It has a digit adder circuit (ADi) that shifts to the arithmetic unit, and an output register (RCi) that holds the sum of the partial products in response to a second holding control signal. The one input terminals are connected to each other, the digit addition circuit is connected between the arithmetic units so that the carry is performed, and the control circuit (C) sends the opening/closing signal to the gates (G0 to Gm). A0
, A1,..., the partial product of Am and Bi is calculated by the multiplier (M
0 to Mm), and the intermediate registers (RM0 to RM
m) supplies the first holding control signal to hold the partial product in the intermediate register, and outputs the output register (RC0 to RCm
) is supplied with the second holding control signal to hold the sum of the partial products in the output register, and the operation and holding are performed from i=0 to
A series-parallel multiplier characterized in that each of m is executed in turn. 2. An a-side terminal is connected to the multiplier-side terminal of the gate, a b-side terminal is connected to the terminal that outputs the shift signal, and a common terminal is connected to the multiplier-side terminal of the gate, and a common terminal is connected to the multiplier-side terminal of the gate, and the b-side terminal is connected to the terminal that outputs the shift signal. changeover switch means (17, 27) connected to the terminal on the multiplier side and for connecting the common terminal to either the a-side terminal or the b-side terminal according to a switching control signal (SC);
, 37), the control circuit (C) supplies the changeover control signal to the changeover switch means to calculate the partial product with the changeover switch means set to the a side, and 2. The series-parallel multiplication device according to claim 1, wherein the switching control signal is supplied to the converter to cause the sum of the partial products to be calculated and the shift to be performed while the changeover switch means is set to the b side. vessel. 3. The digit addition circuit (ADi) calculates the sum of the value of the upper n bits of the intermediate register (13, 23, 33) and the digit of the next higher digit from the arithmetic unit. the first adder (14, 24, 34), the value of the lower n bits of the intermediate register and the output register (15);
, 25, 35).
6, 26, 36), the output of the first adder is held in the output register, and the output of the second adder is supplied as a carry to the next-stage arithmetic unit. 3. A series-parallel multiplier according to claim 1 or 2. 4. The digit addition circuit (ADi) calculates the sum of the value of the lower n bits of the intermediate register (13, 23, 33) and the carry of the next lower digit from the arithmetic unit. the first adder (14, 24, 34), the value of the upper n bits of the intermediate register and the output register (15);
, 25, 35).
6, 26, 36), the output of the first adder is held in the output register, and the output of the second adder is supplied as a carry to the arithmetic unit at the next stage. 3. A series-parallel multiplier according to claim 1 or 2.