JPH02295213A - Notch filter - Google Patents

Abstract

PURPOSE:To obtain a notch frequency variable notch filter which can be mastered even by a beginner by delaying an input signal based on the set number of stages and the clock frequency and outputting an output signal obtained by performing the addition or the subtraction between the delayed input signal and a delay signal. CONSTITUTION:A clock generator 5 outputs a clock of a prescribed frequency fCL based on the control signal applied to a control terminal. A delay circuit 4 delays an input signal Si (t) received from an input terminal 1 by the delay time tau based on the frequency fCL and outputs a delayed signal Si (t-tau). A computing element 6 performs the addition or the subtraction between both signals Si (t) and Si (t-tau) and outputs an output signal through an output terminal 3. Thus plural notch frequencies are secured within a desired band based on the notch frequency by means of the characteristic of a comb-line filter. As a result, an entire part can be covered with the notch frequency within the desired band. Then even a beginner can easily eliminate the beat interference noises.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a notch filter used to remove beat interference in a radio receiver.

[Conventional technology]

Conventionally, this type of notch filter has been realized by a Wien bridge or the like or a twin T-type filter shown in FIG. These allow only one frequency to be removed, and the notch frequency is made variable over an audio frequency band (for example, 0.3 KHz to 3.4 KHz).

[Problem to be solved by the invention]

The above-mentioned conventional notch filter removes only one frequency, so if the notch filter has a high Q value and sharp characteristics, it has the disadvantage that the desired interfering beat sound cannot be removed unless the frequency is carefully varied. Furthermore, it is difficult for the general public to determine the frequency of the beat interfering sound, and therefore, even if a notch frequency scale is displayed, it is difficult for beginners to use it effectively.

[Means to solve the problem]

The notch filter of the present invention includes: a delay circuit whose number of stages is variable and whose delay time is variable based on a clock frequency; a clock generation circuit which changes the clock frequency based on a control signal and supplies the clock to the delay circuit; It has an arithmetic unit that receives an input signal and a delayed signal obtained by delaying the input signal by a delay circuit, performs specified addition or subtraction on both signals, and outputs the signal as an output signal, preferably with a delay time of 2. 0 0 msec to 10
After the delay time is determined once by changing it continuously up to about 0ISeC, the delay time is set such that one frequency among the plurality of notch frequencies becomes at least the lowest notch frequency except 0Hz. It has means for sequentially and discretely changing the clock frequency or the number of delay stages.

[Effect]

The delay circuit delays the input signal based on the set number of stages and clock frequency, and the arithmetic unit adds or subtracts the delayed signal from the input signal and the delay circuit and outputs it as an output signal, so it can be used as a notch filter with variable notch frequency. Operate.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Fig. 1 is a block diagram showing the first embodiment of the notch filter of the present invention, Fig. 2 is a diagram showing the frequency characteristics of the embodiment of Fig. 1, and Fig. 3 shows the state of the signal and beat interference sound. FIG. 4 is a diagram showing an example of FIG. 2.

The clock generator 5 outputs a clock at a predetermined frequency f CL based on the control signal applied to the control terminal 2 .

The delay circuit 4 converts the input signal s1(1) input from the input terminal 1 into a delay time τ based on the clock frequency fCL.
and outputs it as a delayed signal 3+ (t - τ). The arithmetic unit 6 adds (or subtracts) the input signal S([) and the delayed signal &(t-τ) to produce an output signal So(j).
It is output from output terminal 3 as

In this case, the delay time τ becomes N/f CL, which is the product of the number of stages N of signal delay means included in the delay circuit 4 and the reciprocal of the clock frequency f CL. Moreover, the output signal So(
The frequency characteristic G (f) of t) is expressed by equation (1), and is a so-called comb-shaped filter characteristic.

Therefore, at the frequency expressed by equation (2), equation (1)
becomes 0, and the output signal So(t) also becomes 0.

cos 2πfpnτ=壬1−...−(2) Furthermore,
To be more specific, when formula (3) is used, formula (2) is -1,
In the case of equation (4), equation (2) becomes +1.

However, n-0, ±1. ±2, ~ Expression (1) can be expressed graphically as shown in Figure 2. Generally, as shown in FIG. 3, the audio signal Sv often contains beat interference Sb, and if the characteristic shown in FIG. 2 is set with the delay time τ as shown in FIG. The beat disturbance Sb shown in the figure can be easily removed. That is, for example,
If the delay time τ is 100 msf3c, the notch points are 50 Hz, 150 Hz, 250 Hz, .
1950Hz, 2050Hz, -... roar. If the delay time τ is 105 +11SeC, the notch point is 4
7.5 11z, 143 Hz, 238 Hz, 1
Since the frequency changes to 857 Hz, 1952 Hz, . . . , it is clear that the beat disturbance Sb near 2000 Hz can be easily removed.

However, if the delay time is long, the sound quality will deteriorate slightly, so it is desirable to have as few unnecessary notch points as possible. In other words, it is desirable that the delay time be short.

As a second embodiment, by continuously varying the clock, as mentioned above, there is a means for continuously varying the delay time, and one of the notch frequencies is set to OH.
It has means for sequentially and discretely changing the clock frequency or the number of delay stages so that the delay time has the lowest notch frequency except for Z. This results in a frequency characteristic as shown in FIG. 5, making it possible to reduce deterioration in sound quality. As shown in FIG. 2, the first notch frequency is 0.5/r [NZ]. The second is 1. 5/
r[11Z] ,...n-th notch frequency is (n
−0.5)/τ [Hz]. Suppose that the current no-th notch frequency and the beat interference sound to be removed match, then (7)/y-th notch frequency is (no -0.5) /
r [Hz]. To make this the first notch frequency by varying τ, 0.5/τ1 (no −0.5 > /τ0...
... (3) should be satisfied. Therefore, it becomes 0.5 r-104ωto0・゜-゜゜- (4). By fixing τ0 and sequentially varying n from, for example, 40 to 1, it is possible to confirm τ that can eliminate the beat interference sound.

In equation (4), the easiest way to sequentially vary the delay time is to vary the number of delay stages.

It can also be realized by using PLL and multiplying the frequency to make the clock variable.

Note that the delay circuit line is A/D. One that uses a D/A converter and a shift register, BBD. Or COD
A charge transfer device such as the one described above can be used.

〔Effect of the invention〕

As explained above, the present invention makes use of the comb-shaped filter characteristics to create a plurality of notch frequencies based on the clock frequency within the required band. Since the entire band can be covered by the notch frequency, even beginners can easily remove the beat interference sound, and if the delay time is minimized, the above removal can be done with minimal deterioration in sound quality. There are some effects that can be done.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the first embodiment of the notch filter of the present invention, Fig. 2 is a diagram showing the frequency characteristics of the embodiment of Fig. 1, and Fig. 3 is a diagram showing the state of the signal and beat interference sound. , FIG. 4 is a diagram showing an example of FIG. 2, FIG. 5 is a diagram showing the characteristics of the notch filter of the second embodiment, and FIG. 6 is a circuit diagram showing a conventional example. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Control terminal, 3... Output terminal, 4... Delay circuit, 5... Clock generator, 6... Arithmetic unit. Figure 4

Claims (1)

[Claims] 1. A delay circuit whose number of stages is variable and whose delay time is variable based on a clock frequency; and a clock generation circuit which changes the clock frequency based on a control signal and supplies the clock to the delay circuit. , a notch filter 2 consisting of an arithmetic unit that inputs an input signal and a delayed signal obtained by delaying the input signal by a delay circuit, performs specified addition or subtraction between both signals, and outputs it as an output signal; After changing the delay time continuously from 200msec to about 100msec and determining the delay time once, one of the multiple notch frequencies becomes 0H.
2. The notch filter according to claim 1, further comprising means for sequentially and discretely changing the clock frequency or the number of delay stages so as to obtain a delay time that provides at least the lowest notch frequency except for z.