JPS59178808A - Digital equalizer amplifier for audio use - Google Patents

Abstract

PURPOSE:To attain broader dynamic range in comparison with that of an analog filter and to set a gain to a more minute frequency by replacing the analog filter into a digital filter in the constitution of the filter so as to set the frequency characteristic freely. CONSTITUTION:When a gain of 50 dB is desired for frequencies 0Hz-20kHz, 0 is inputted as frequency and 50 as the gain from a digital switch 10 and then 20,000 and 50 are inputted respectively as the frequency and the gain. Every time the frequency and gain are inputted in pairs from the switch 10, the data are given to a filter coefficient operating circuit 8 via a CPU9 for control. When the operation of a filter coefficient is finished, the operating circuit 8 stores the result to a filter coefficient storage memory 7 and informs the end of operation to the CPU9 for control. The CPU9 for control displays the end of operation of the filter coefficient to a panel 11. When the start of processing is commanded by the switch 10, the CPU9 for control receives the command and commands the start of processing to the digital filter circuit 4 and then the processing of the filter is started.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an audio denotal equalizer amplifier whose filter characteristics can be set arbitrarily.

(Background Art) Conventional audio equalizer amplifiers have been implemented in the analog domain, and are based on a combination circuit of analog filters with unstable filter characteristics. For this reason, there are restrictions on the settings of filter characteristics, and in order to set the filter characteristics in detail, many analog filters are required. Also, due to the nature of analog filters, the dynamics and crosstalk could not be set very wide. My father, in the past, it was extremely difficult to replace analog filters with digital filters. The reason is that the frequency band used for audio is from OH2 to 20 kHz, and the sampling interval is very short, so in order to perform an acyclic digital filter in these frequency bands, a very high-speed multiplier is required. This made me feel at ease.

(Problem to be solved by the invention) In recent years, with the advent of very high-speed multipliers, it has become possible to perform digital filtering using an acyclic digital filter in the audio frequency band. The present invention
The filter configuration is replaced from an analog filter to a digital filter, and the frequency characteristics can be set freely.The purpose of this is to eliminate the drawbacks of the analog filter described above, and will be described in detail below.

(Structure and operation of the invention) Figure 8g1 is an example of the present invention. Here, 1 is an analog filter, 2 is an A/D converter, 3 is a data circuit, 4 is a digital filter circuit, 5 is a D/Aim device, 6
1 is a sample clock oscillation circuit, 7 is a filter coefficient storage memory (random access memory), 8 is a filter coefficient calculation circuit, 9 is a control CPU, 10 is a switch, and 11 is a panel.

This device operates as follows. The operating procedure is shown in FIG. First, ten switches input data regarding the filter characteristics. For data regarding filter characteristics, input the necessary number of frequencies and gains for the frequencies. However, the number of frequencies that can be set is
It is limited by the order of convolution performed by an acyclic digital filter. Furthermore, the range of gains that can be set is also limited to the data pit length. For example, 16 binoto data can have a range of 96 dB.

As explained above, for example, if you want to increase the gain from QHz to 20kHz to 50dB, the switch of ]0.

Enter 0 for the frequency and 50 for the gain, then enter 20,000 for the frequency and 50 for the gain. As described above, each time the frequency and gain are input from the 10 switches, the data is given to the 8 filter coefficient calculation circuits via the 9 control CPUs. After setting the required number of frequencies and gains, all instructions for creating filter coefficients are issued using the 10 switches. The control CPU 9 receives the instruction to create filter coefficients and instructs the filter coefficient calculation circuit 8 to create filter coefficients. When the filter coefficient calculation circuit 8 receives an instruction to create a filter coefficient, it calculates in advance from 4 points),
This is an example of filter characteristics obtained by linear approximation. In this way, the filter coefficients are determined so as to have filter characteristics determined by linear approximation.

When the filter coefficient calculation circuit 8 completes the calculation of the filter coefficient, it stores it in the filter coefficient storage memory 7, and notifies the control CPU 9 of the completion of the calculation.

Next, the control CPU 9 displays on the panel 11 that the calculation of the filter coefficients has been completed. When the switch 10 instructs to start processing, the control CPU 9 receives the instruction and instructs the digital filter circuit 4 to start processing, thereby starting the filter processing.

As mentioned above, the 9:ij'l side I CPU, the 10 switch, the 11 7'? interface and 8
It serves as a controller for the filter coefficient calculation circuit of 4 and the digital filter circuit of 4.

Next, the process will be explained.

Input signal (is 1 low pass filter (LOW pASS FILTER) below 20 kHz f ways, 2
The A/D converter converts it into a digital value. The human input signal, which has become a digital value, is latched by the data latch circuit 3 using the sample clock output from the oscillator 6. The digital filter circuit 4 digitally filters this data, and finally the data is output as an analog value by the D/A controller 5.

Here, the processing method of the digital filter circuit No. 4 will be explained. The digital filter circuit 4 convolves the manually entered data with the filter coefficients manually entered in the filter coefficient storage memory 7 and outputs the data.

As described above, the first embodiment has the advantage that the filter characteristics can be set arbitrarily using the IO switch. Furthermore, by increasing the convolution order of the acyclic digital filter, the filter characteristics can be set more precisely. Furthermore, increasing the number of bits of the digital data on which the acyclic digital filter is applied has the advantage that the dynamic range becomes narrower.

In addition, in the first embodiment, the key for any frequency was set using 10 switches, or the key was set using 9 switches as shown in FIG.
] 12 I10 interface circuits are connected to your CPU, 14 magnetic teso readers (MT), 15 floppy disks (FDD), 16 paper teso readers (
PTR), the key for any frequency from each Ilo can be stored in the filter coefficient storage memory 7 through the 8 filter coefficient calculation circuits. or,
The filter coefficients can be directly stored in the filter coefficient storage memory 7.

Also, if the filter coefficients are fixed, the values in the 7 fill and coefficient storage memories are not used, and the 13 read-only memories (
The filter coefficient values written in the ROM can be used.

Further, in FIG. 1, each of the circuits has 11 digital circuits and 8 filter coefficient calculation circuits. However, the digital filter circuit No. 4 is also a mere calculation circuit, and can be shared with the filter coefficient calculation circuit No. 8, and can be combined into one circuit. The control CPU 90 can be used to switch whether the arithmetic circuit is to perform filter coefficient calculation or a digital filter.

(Effects of the Invention) The present invention has a denotal filter configuration and a filter coefficient calculation circuit, so compared to analog filters, the dynamic range is wider and the gain can be set for finer frequencies. Therefore, it is effective as an audio equalizer amplifier.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of its operation, FIG. 3 is a diagram showing an example of filter coefficients created by data (white dots) given by switch 10, FIG. 4 is a block diagram of another ρ embodiment of the present invention. 1. Analog filter, 2. A/D variable gain, 3.
Data latch circuit, 4... Digital filter circuit, 5
... D/A converter, 6... Sample clock generator,
7... Filter coefficient storage memory (random access memory), 8... Filter coefficient calculation circuit, 9... Control C
PU, 10...Switch, 11...Noya Nell, 12...
・I10 interface, 13...ROMX 14...
・MT '115...FDD,,16...P
T.R. #I (2)

Claims (1)

[Claims] means for converting an input analog signal into a digital signal; a digital filter for performing an acyclic filtering on the digital signal in the time domain; a means for converting the output into an analog signal and outputting it; and characteristics of the filter. and a means for calculating and storing coefficients of a filter according to the settings of the switch and applying the coefficients to the filter, and the filter characteristics can be set by the switch. equalizer amplifier.