JP2834746B2 - Digital signal processing device and address data generating method thereof - Google Patents

Description

The present invention relates to a digital signal processing apparatus that processes data input in time series based on a predetermined algorithm and outputs the data as time series data, and address data thereof. How to create.

(B) Conventional technology Generally, primitive information sources existing around us, such as voices and images, are often analog signals. Until now, this analog signal has been processed as it is, for example, amplification, filtering, etc.
With the advance of conversion technology and digital processing technology, a system for processing an analog signal by a digital method, that is, a digital signal processing device (DSP: digital signal processor) has been developed.

In addition, digital circuits are rapidly becoming LSIs, and DSPs can be easily implemented on one-chip semiconductors. Furthermore, high-precision processing can be performed compared to analog signal processing. Can be obtained stably,
There are features such as the possibility of no adjustment.

Further, in the audio field, as audio signals are digitized, such as CD (compact disc) players and DAT (digital audio tape) players, the audio signals are digitally processed.
DSP systems have been put into practical use.

Such a DSP is provided with a memory for storing digital data obtained by sampling an audio signal and operation result data generated by numerically calculating the data. The DSP can easily create a function to create reflected and reverberant sounds by digital processing using the data stored in the memory.

Therefore, a schematic diagram for creating reflected sound and reverberation sound is shown in FIG.
Shown in the figure. (1) is a memory, (2) is a multiplier, and (3) is an adder. The memory (1) stores digital data corresponding to an audio signal input for each sampling period, and stores an area A for creating a reflected sound and an area B for storing digital data for creating a reverberant sound. Divided. In the region A, the address for writing the digital data to be input to each sampling period as the WA _1,
RA ₁ an address for reading the digital data, RA _2, RA
₃ and RA ₄ , the write address WA ₁ and the read address RA ₁ , RA ₂ , RA ₃ , and RA ₄ are shifted by one address (increment or decrement) at each sampling period to perform writing and reading, thereby delaying. Digital data is obtained. Read address RA ₁ , RA
₂ , the delay data extracted from RA ₃ is multiplied by attenuation coefficients a, b, and c, and the result of the multiplication is added to the input digital data. The delay data retrieved from the read address RA _4, the attenuation coefficient d are multiplied, the multiplication result is added to the reverberation sound data produced by the area B, with written into the write address WA ₂ region B It is further added to the addition result of the reflected sound. Reverberation sound data is obtained by setting the read address RA ₅ that apart from the write address WA ₂ like the reflected sound. of course,
Area B write address WA ₂ and read address RA
₅ is incremented or decremented every sampling period. Note that writing and reading for creating the reflected sound are accessed by circulating through the area A.
Writing and reading for creating the reverberation are accessed by circling the area B.

FIG. 3 is an impulse response characteristic diagram of the system shown in FIG. The digital data D _IN input at the time t ₀ is read from the address RA _{1 at} the time t _{1 and} reproduced as the _first reflected sound D ₁ , and similarly, at the time t ₂ , from the address RA _{2 at} the time t _{2 3} the address RA _3, are read out from the time t ₄ the address RA _4, the second reflected sound D _2, third reflected sound D _3, fourth reflected sound D ₄ are reproduced. In addition, after time t _5, the reverberation that has been read from the address RA ₅ is repeated Kaee to play.

Here, delay times t ₁ −t ₀ , t ₂ −t ₀ , t ₃ −t ₀ , t ₄ −t ₀ , t ₅ −
t _4, when the sampling frequency is _{F SR t 1 -t 0 = (} RA 1 -WA 1) 1 / F SR t 2 -t 0 = (RA 2 -WA 1) 1 / F SR t 3 -t 0 _{= (RA 3 -WA 1) 1} / F SR t 4 -t 0 = (RA 4 -WA 1) 1 / F SR t 5 -t 4 = (RA 5 -WA 2) is expressed as 1 / F _SR.

(C) Problems to be solved by the invention By the way, the sampling frequency for converting an analog signal into a digital signal is currently 44.1 KHz for a CD and 48 KH for a DAT.
z, 32 kHz is standardized in the standard mode and the satellite broadcast A mode. Therefore, when the DSP is adapted to the above-described various systems, if the sampling frequency is different, the delay time differs in the system for creating the reflected sound and the reverberant sound.

Therefore, conventionally, the read address is set so that the delay times are equal according to the sampling frequencies of various types. That is, address data corresponding to the sampling frequency is stored therein. Therefore, there is a disadvantage that a memory area for storing the address data is increased and a large-capacity memory must be provided.

(D) Means for Solving the Problems The present invention has been made in view of the above points, and has a memory for storing digital data, and a memory for delaying and reading the digital data stored in the memory. Reference address holding means for holding a reference address, and in order to make the amount of delay constant according to different sampling frequencies,
Correction coefficient holding means for holding a coefficient for correcting the reference address, and address data generating means for multiplying the correction coefficient according to the sampling frequency by the reference address to generate actual read address data of a memory. With the provision, an object is to reduce a memory area for holding address data.

(E) Operation According to the above-described means, the correction coefficient can be expressed as a ratio between the sampling frequency that is the basis for setting the reference address and another sampling frequency. Becomes two correction coefficients. By multiplying the reference address data by this correction coefficient, read address data at different sampling frequencies can be obtained. The calculated address data is incremented or decremented for each sampling period, thereby accessing the memory circulating. Therefore, the memory area holding the address data only holds the reference address data and the correction coefficient.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
(4) DSP-LSI formed on the same semiconductor chip,
(5) Microcomputer connected to DSP-LSI (4), (6)
Is an external memory externally connected to the DSP-LSI (4).

The DSP-LIS (4) comprises a signal processing circuit (7), an external memory interface circuit (8), a microcomputer interface circuit (9), a control circuit (10), and a bus (11) connecting these circuits. You.

The signal processing circuit (7) is a circuit for processing digital data obtained by sampling an audio signal, and includes a constant RAM (12) for storing constant data and a data RAM (13) for storing digital data. And a multiplication and operation unit (14) for performing multiplication and operation. Typical processing of digital data includes filtering processing, which is performed by multiplying a filter constant stored in a constant RAM (12) in advance by digital data stored in a data RAM (13) to obtain a graphic equalizer. Function or tone control function. Further, the signal processing circuit (7) synthesizes the reflected sound and the reverberant sound by performing multiplication and addition, thereby realizing the system shown in FIG. In the case of stereo, since the audio signal includes a right channel and a left channel, a pair of signal processing circuits (7) may be provided so that digital data processing of the right channel and the left channel is performed independently.

Further, the multiplication of the signal processing circuit (7) and the creation of address data using the arithmetic unit (14) are also performed, and the signal processing circuit (7) is also used as address data creation means.
That is, by applying the address data, the correction coefficient, and the like to the multiplication and operation unit (14) via the bus (11), desired address data can be created. Also, constant RAM
(12) and the data RAM (13) are also used as a memory for address data and correction coefficients.

The external memory interface circuit (8) is a DSP-LSI
The external memory (6) connected to (4) and the internal bus (1
1), the address data sent to the bus (11) is applied to the external memory (6), and write / read data is sent / received.

The external memory (6) stores digital data input for each sampling period and stores digital data that has been subjected to calculation processing in order to generate reflected sound and reverberant sound, and creates delayed digital data. is there. For this purpose, the external memory (6) has an area A for producing a reflected sound and an area B for producing a reverberant sound, as shown in FIG.

The control circuit (10) controls the internal operation of the DSP-LSI (4), and includes a program memory for storing a program, an instruction decoder for decoding and executing an instruction code, and the like. Further, the control circuit (10) receives the sampling signal F _S, and performs an operation defined for each sampling period.

The microcomputer interface circuit (9) is a circuit for transmitting and receiving digital data, control data, or address data to and from an externally connected control microcomputer (5). It is arranged between the microcomputers (5). The microcomputer (5) is a DSP-LSI
The control of (4) is performed, and the internal
In the RAM (15), as shown in FIG. 2, an area for storing reference address data for accessing the external memory (6) and a correction coefficient is provided. The microcomputer (5)
The applied sampling signal F _S has been made program for control to DSP-LSI (4) for respective sampling period.

Incidentally, the reference address data stored in the internal RAM (15), upon a reference sampling frequency is e.g. 32KHz (referred to as F _SR), it is determined so that the delay amount of the reflected sound and the reverberation becomes proper . Specifically, has write address WA ₁ and region zero address (region A and the start address assigned region B the write address WA ₂ B in the area A to zero. Thus, the actual external memory (6) The address is obtained by adding the start address value of each area.)
_{RA 1, RA 2, RA 3} , sets the RA ₄ and RA _5.

For other sampling frequencies of 44.1 KHz and 48 KHz, a correction coefficient of F _S1 = 44.1 / 32 = 1.378 F _S2 = 48.0 / 32 = 1.500 is prepared.

That is, if the write addresses WA ₁ and WA ₂ are zero,
The read addresses RA ₁ , RA ₂ , RA ₃ , RA ₄ , and RA ₅ are addresses corresponding to the delay amount. Therefore, the read address _{RA 1, RA 2, RA 3} , RA 4, and, by multiplying the correction coefficient F _S1 or F _S2 to a value of RA _5, the address data unchanged delay amount in accordance with the sampling frequency is obtained Can be

Therefore, the microcomputer (5) Internal RAM (15) of advance, the reference address data _{RA 1, RA 2, RA 3} , RA 4, RA 5 and it is only allowed to hold the correction coefficient F _S1, F _S2 .

Next, a method of creating address data will be described with reference to the block diagram shown in FIG.

First, in the operation in the initial state, the microcomputer (5)
Reference address from the internal RAM (15) data _{RA 1, RA 2, RA 3} , R
And A _4, RA _5, the correction coefficient corresponding to a sampling frequency at that time, for example, reads the F _S1 when the sampling frequency is 44.1 KHz, via the microcomputer interface circuit of DSP-LSI (4) (9 ), Multiplication and operation unit (14)
Directly, or constant RAM (12) and data RAM (13)
To supply. DSP-LSI (4) is a multiplication and operation unit (14)
Accordingly, by multiplying the reference address data _{RA 1, RA 2, RA 3} , RA 4, RA 5 in the correction coefficient F _S1, and stores the result in a predetermined area of the data RAM (13). This multiplication result becomes address data corresponding to the sampling frequency of 44.1 KHz.

When DSP-LSI that (4) to create a reflected sound and reverberation, address data RA ₁ from the data _{RAM (13), RA 2,} RA 3, R
A ₄ and RA ₅ are taken out, sequentially applied to the external memory (6) via the external memory interface circuit (8), digital data is read out, and the digital data is added to the constant RAM (1).
The coefficients a, b, c, d, e, and f (multiplication coefficients shown in FIG. 2) stored in 2) are multiplied by the multiplication and operation unit (14), and the results are added. Further, the multiplication result of the data and the coefficient e read from the address data RA ₄ is added to the multiplication result of digital data and the coefficient f read from the address RA _5, the addition result is written in the address WA ₂ Then, the sum is added to the sum of the reflected sound and the input digital data and output.

When the creation of the reflected sound and the reverberation sound is completed, the corrected address data stored in the data RAM (13) becomes
Each is decremented (-1), and the result is stored again in a predetermined area of the data RAM (13). Of course, the write address WA ₁ and WA ₂ also decremented, is held in the data RAM (13). That is, the address data of the external memory (6) when the next digital data is input is created.

Further, as the other address data creation method, the read address from the write address WA ₁ region A RA _1, RA _2, R
Address difference between A ₃ and RA ₄ and write address of area B
Difference reference sampling frequency of the WA ₂ and the read address RA _5, for example, is stored in the internal memory (15) of the microcomputer (5) as a reference address data corresponding to 32KHz, this correction factor F _S1, F _S2 Is also available. In this case, the reference address data and the correction coefficient F _S1 or F _S2
The result of the multiplication to obtain the address _{RA 1, RA 2, RA 3} , RA 4, RA 5 is added to the write address WA ₁ and the write address WA _2. Others are the same as the above-mentioned method.

(G) Effect of the Invention As described above, according to the present invention, the reference address data having a delay amount corresponding to the reference sampling frequency is set, and a correction coefficient corresponding to the sampling frequency having a different frequency is created. The area of the memory for storing data can be reduced. In addition, since the multiplication of the reference address data and the correction coefficient uses a multiplier of a signal processing circuit that processes digital data, it is possible to create address data with a simple program.

Therefore, even if the sampling frequency is different, a digital signal processing device that can very easily create a reflected sound or a reverberant sound can be obtained, and the effect is great when used for audio.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a system for synthesizing a reflected sound and a reverberant sound, and FIG.
The figure is a characteristic diagram showing the impulse response of the system shown in FIG. (4) DSP-LSI, (5) microcomputer, (6)
External memory, (7) signal processing circuit, (8) external memory interface circuit, (9) microcomputer interface circuit, (10) control circuit, (11) bus.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G10K 15/12 G06F 12/02 550 G06F 15/31 H03H 17/00 621 H03H 17/02 635

Claims (2)

(57) [Claims] A digital signal processing device for inputting and processing a digital signal every sampling period, a memory for storing the digital signal, and a reference address holding means for holding a reference address.
Correction coefficient holding means (15) for holding a correction coefficient corresponding to the sampling cycle; multiplication means (14) for multiplying the correction coefficient corresponding to the input sampling cycle by the reference address to calculate a delay amount address; And a control means for generating a write address, generating a read address based on the write address and the delay amount address, and performing a write / read process of the memory (6). 2. A digital signal processing apparatus according to claim 1, wherein said multiplying means is used for processing a digital signal.