JP3277518B2 - Sound field processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DSP for signal processing.
The present invention relates to a sound field processing device suitable for use in a compact disc player on which a (digital signal processor) is mounted.

[0002]

2. Description of the Related Art A portable compact disk player equipped with an audio DSP is known. The DSP
It is a processor for performing digital signal processing, and can perform various signal processing by a program. For example,
When this DSP is mounted on a portable compact disc player, it is possible to perform processing such as raising a low frequency range to obtain a powerful reproduction sound, or making a low reproduction sound float and be heard.

As shown in FIG. 5, in a conventional compact disk player equipped with a DSP, a reproduced digital audio signal reproduced from a compact disk and decoded is supplied from an input terminal 101 to an audio DSP 102.
Supplied to The audio DSP 102 can be set to three modes, for example, a normal mode, a DBB mode for emphasizing low frequencies, and a DSS mode for raising small signals. The audio DSP 102 performs necessary signal processing on the reproduced digital audio signal. The digital audio signal thus processed is supplied to the D / A converter 104 via the digital filter 103. D / A converter 104
Thus, the digital audio signal is converted into an analog audio signal. The output of the D / A converter 104 is output to the output terminal 1 via the analog amplifiers 105A and 105B.
It is output from 06A and 106B.

[0004]

However, in the conventional portable compact disk player equipped with the audio DSP 102 as described above, there is a problem that the dynamic range and the distortion factor are deteriorated during normal reproduction. This is because the input signal level to the audio DSP 102 is attenuated so that the audio DSP 102 does not overflow.

That is, the audio DSP 102 is conventionally provided with an attenuator 110 of, for example, about -10 dB at the input stage as shown in FIG. 6, and thereafter, required signal processing is performed by the signal processing circuit 111. No overflows occur. In the normal mode, the audio DSP 102 has a buffer configuration. And the analog amplifiers 105A and 105B
Thus, the attenuated portion is compensated. However, when the input signal is attenuated in this manner, the number of bits is reduced, so that the dynamic range is reduced and the quantization distortion is increased.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a sound field processing apparatus in which signal deterioration due to attenuation of an input stage does not occur.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a sound field processing device for performing sound field processing using a digital signal processing device. The sound field processing device controls the input level of a digital signal input to the digital signal processing device. A sound field processing device wherein an output level of an analog signal output from a digital signal processing device via a digital-analog converter is controlled.

[0008]

In the normal mode, the lines 43A and 43A
A signal is output through the filter 3B and the filters 47A and 47A.
B is not mediated. For this reason, in normal mode,
The signal is output without being attenuated, the number of bits is not reduced, and the dynamic range is prevented from being reduced and the quantization distortion is prevented from being increased. In this case, the output gain changes between the normal mode and the DBB mode or the DSS mode. Therefore, in the case of the DDB mode or the DDS mode, the analog amplifier 1
The gains of 3A and 13B are set large.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following order. a. Overall configuration of compact disc player b. Basic operation of system controller c. Realization of signal processing in audio DSP d. Realization of filter configuration

A. Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows the overall configuration of a compact disc player to which the present invention can be applied. In FIG. 1, a digital audio signal is recorded on a compact disk 1 along a spiral track in a predetermined recording format. The rotation of the compact disk 1 is controlled by the spindle motor 2 at CLV (constant linear velocity). The rotation of the spindle motor 2 is controlled by detecting the bit clock of the reproduction signal and controlling the servo signal processing circuit 5 under the control of the CPU 6 for system control.
It is performed by

An optical pickup 3 is provided facing the compact disc 1. A thread feed motor 4 is provided to move the optical pickup 3 in the radial direction of the compact disc 1. Thread feed motor 4
Under the control of the CPU 6 for system control,
It is moved along the radial direction of the compact disc 1.
The optical pickup 3 is provided with a biaxial device for controlling the optical axis direction to be biaxial. The two-axis device is controlled by a CPU for system control by a servo signal processing circuit 5.
6, and the tracking servo and the focus servo control are performed.

A reproduction signal from the optical pickup 3 is supplied to a CD digital signal processing circuit 8 via an RF amplifier 7. Memory 9 for CD digital signal processing circuit 8
Is provided. The CD digital signal processing circuit 8 forms the EFM signal by shaping the waveform of the reproduction signal from the compact disk, demodulates the EFM signal, performs error correction processing and the like, and decodes the left and right digital audio signals. . This CD digital signal processing circuit 8
Is controlled by the CPU 6 for system control. Further, subcode information and the like are obtained from the CD digital signal processing circuit 8, and the subcode information is supplied to the CPU 6 for system control.

An output of the CD digital signal processing circuit 8 is supplied to an audio DSP 10. Audio DSP1
0 performs signal processing on the reproduced sound as needed. The audio DSP 10 can set, for example, a normal mode, a DBB (dynamic bus boost) mode, and a DDS (digital dynamic surround) mode. The DBB mode is a mode for performing processing for raising a low frequency range and obtaining a powerful reproduction sound. The DDS mode is a mode in which a process is performed in which a small buried reproduction sound is raised and heard.

A dedicated CP for the audio DSP 10
U is not prepared, and the audio DSP 10 is also controlled by the CPU 6 for system control. The reason why the audio DSP 10 can be controlled by the system control CPU 6 is that each mode can be dealt with only by changing the coefficient, and the audio DSP 10 can be easily managed as compared with the related art. Since a dedicated CPU is not provided for the audio DSP 10, the size of the device can be reduced and the cost can be reduced. The fact that each mode can be dealt with only by changing the coefficient will be described later.

The output of the audio DSP 10 is supplied to a digital filter 11. The output of the digital filter 11 is supplied to the D / A converter 12. The output of the D / A converter 12 is a left and right analog audio amplifier 1
3A and 13B. The gains of the analog audio amplifiers 13A and 13B are switched between a normal mode and a DBB mode or a DDS mode. When in DBB mode or DDS mode,
The gain is increased as compared with the normal mode. This is because, as described later, a sufficient reproduction sound is obtained in the normal mode, and an input exceeding the dynamic range is not made to the audio DSP in the DBB mode or the DDS mode. Outputs of the left and right analog audio amplifiers 13A and 13B are output from output terminals 14A and 14B.

The CPU 6 for system control includes:
An input is provided from an input key 15. The control state of each system is set according to this input. A display 16 is provided in the CPU 6 for system control. Necessary information is displayed on the display 16.

B. Basic Operation of System Coat Roller In one embodiment of the present invention, C for system control is used.
The PU 6 performs the processing of the entire system and the audio DSP 1
0 control. At this time, the processing of the entire system is prioritized over the control of the audio DSP 10.

FIG. 2 is a flowchart showing an outline of the processing performed by the CPU 6 for system control. When the start of performance is input from the input key 15, the CPU 6 for system control powers on each circuit (step 21). Then, a wait is performed while the power supply is stabilized (step 22). When the power supply is stable,
The servo system is initialized and the servo system data is transferred (step 23). And audio DSP10
, Necessary data is transferred (step 24). When the necessary data is transferred, the performance is started (step 25).

During the performance, it is determined whether sub-code information has been sent (step 26). The subcode information is obtained, for example, about every 13 msec. When the subcode information arrives, the subcode information is read (step 27), and it is determined whether or not the audio DSP flag is set (step 28). Audio DS
If the P flag has not been set, the process returns to step 26, and the reading process of the subcode information is continued.

When it is determined in step 26 that the subcode information has not come, that is, while the subcode information is obtained, a display process, a surfer process, and an input reading process are performed (step 29). Then, it is determined whether the mode or the effect amount of the audio DSP 10 has been changed (step 30). Audio DSP1
If the mode of 0 and the effect amount have not been changed, the process returns to step 26, and the reading process of the subcode information is continued.

If it is determined in step 30 that the mode or effect amount of the audio DSP 10 has been changed, it is determined whether subcode information has been sent (step 31). If the subcode information has not been sent, a process for changing the mode and the effect amount of the audio DSP 10 is performed (step 32). Then, the audio DSP flag is cleared (step 3).
3). Then, the process returns to step 26, and the reading process of the subcode information is continued.

In step 30, even if the mode or the effect amount of the audio DSP 10 has been changed, if sub-code information has been sent, this processing must be given priority. For this reason, if it is determined in step 31 that the subcode information has been transmitted, the audio D
The SP flag is set (step 34), and step 2
Returned to 6.

If the audio DSP flag is set, after the sub-code information is read in step 27, it is detected in step 28 that the audio DSP flag is set. And a process for changing the effect amount. Then, in step 33, the audio DSP flag is cleared. Then, the process returns to step 26, and the reading process of the subcode information is continued.

As described above, in one embodiment of the present invention, the system control CPU 6 performs the processing of the entire system and the control of the audio DSP 10. It can be said that the control at this time generally performs a process for changing the mode and the effect amount of the audio DSP 10 during the time for reading the subcode information. Therefore, the processing for changing the mode and the effect amount of the audio DSP 10 must be completed while reading the subcode information (about 13 msec).

Conventionally, the DSP sets a program so that signal processing corresponding to each mode is performed. Therefore, it is difficult to change the mode in such a short time. Therefore, in one embodiment of the present invention, mode change processing and effect amount setting can be handled by changing several sets of coefficients. Thus, during the time for reading the subcode information, it is possible to sufficiently perform the processing such as the mode change and the setting of the effect amount.

C. Realization of Signal Processing in Audio DSP The audio DSP 10 will be described. FIG.
2 shows a flow of signal processing realized by the audio DSP 10. The audio DSP 10 includes only a signal processing circuit as shown in FIG. 3, and a mode can be changed by changing a coefficient of the signal processing circuit. That is, in the normal mode, the amplifiers 42A and 4A
The gain of 2B is set to 1, and the gains of the amplifiers 45A and 45B are set to 0. In the DBB mode, the amplifier 42A
And 42B are set to 1, the gain of amplifiers 45A and 45B is set to 1, and filters 47A and 47B are set.
B is set in the low-pass filter. In the DDS mode, the gains of the amplifiers 42A and 42B are set to 0, and the gains of the amplifiers 45A and 45B are set to 1. At the same time, the filters 47A and 47B are set as all-pass filters. The effect amount in each mode is set by the shift amounts of the shift registers 56A and 56B.

The gains of the amplifiers 42A and 42B and the gains of the amplifiers 45A and 45B can be set only by changing the coefficients. The shift amounts of the shift registers 56A and 56B can also be set only by changing the coefficients. Further, the filter 47
The setting of the characteristics of A and 47B can be changed only by setting the coefficient, as described later.

First, the signal flow in the normal mode will be described. In the normal mode, the gains of the amplifiers 42A and 42B are set to 1, and the gains of the amplifiers 45A and 45B are set to 0. In normal mode, input terminal 4
Left and right digital audio signals are supplied to 1A and 41B, respectively. The left and right input digital signals are supplied to amplifiers 42A and 42B, respectively. In the normal mode, since the gains of the amplifiers 42A and 42B are set to 1, the signals from the input terminals 41A and 41B are transmitted through the lines 43A and 43B and the amplifier 42 having the gain of 1 respectively.
A and 42B are respectively supplied to the adders 44A and 44B. On the other hand, in the normal mode, since the gains of the amplifiers 45A and 45B are set to 0, no signal is output via the lines 46A and 46B. Therefore, in the normal mode, the signals from the input terminals 41A and 41B are directly output from the output terminals 57A and 57B.
B outputs.

In the DBB mode, the gains of the amplifiers 42A and 42B are set to 1, the gains of the amplifiers 45A and 45B are set to 1, and the filters 47A and 47B are set as low-pass filters. In the DBB mode, the left and right digital audio signals from the input terminals 41A and 41B are supplied to filters 47A and 47B and to amplifiers 42A and 42B, respectively. Since the filters 47A and 47B are low-pass filters, low frequency components in the left and right input digital signals are extracted by the filters 47A and 47B.
The low frequency components in the left and right input digital signals are divided into lines 46A and 46B and delay circuits 48A and 48B.
Are supplied to the multiplication circuits 49A and 49B, respectively.

The outputs of the filters 47A and 47B are supplied to a level comparison circuit 50. Level comparison circuit 50
The left and right audio signal levels are compared. The level comparison circuit 50 outputs the larger signal of the left and right audio signal levels. Level comparison circuit 50
Is supplied to the absolute value detection circuit 51. The absolute value detection circuit 51 calculates the absolute value of the larger one of the left and right audio signal levels. Absolute value detection circuit 51
Is supplied to the envelope detection circuit 52. The envelope detection circuit 52 calculates the envelope level of the larger one of the left and right audio signal levels.

The output of the envelope detection circuit 52 is linear.
The signal is supplied to a gain generation circuit 54 via a non-linear circuit 53. The linear-nonlinear circuit 53 includes an envelope detection circuit 5
3 is logarithmically converted. The gain generation circuit 54 generates data for setting a gain according to the envelope level of the input signal. The output of the gain generation circuit 54 is supplied to the multiplication circuits 49A and 49A via the non-linear circuit 55.
9B.

In the multiplication circuits 49A and 49B, the low frequency components of the left and right audio signals are multiplied by the gain given from the gain generation circuit 54 via the nonlinear-linear circuit 55. The output of the multiplication circuits 49A and 49B is
5A and 45B respectively. In the DBB mode, the gains of the amplifiers 45A and 45B are set to 1, so that the outputs of the multiplication circuits 45A and 45B are
And 45B via bit shift circuits 56A and 56A.
6B respectively. Bit shift circuits 56A and 56
The shift amount of 6B is set according to the effect amount.
The outputs of the amplifiers 45A and 45B are bit-shifted by the bit shift circuits 56A and 56B, respectively. By bit shifting the data in this way, the enhancement level of the low frequency components of the left and right audio signals is set.

The outputs of the bit shift circuits 45A and 45B are supplied to adders 44A and 44B, respectively. The adder circuits 44A and 44B add the left and right digital audio signal signals via the lines 43A and 43B and the low frequency components enhanced via the filters 47A and 47B and the lines 46A and 46B. Thereby, the low frequency components of the audio signal are enhanced. The left and right audio signals with the enhanced low frequency components are output from output terminals 57A and 57B, respectively.

In the DDS mode, the gains of the amplifiers 42A and 42B are set to 0, and the amplifiers 45A and 45B
The gain of B is set to 1. At the same time, filter 4
7A and 47B are set as all-pass filters. D
In the DS mode, the left and right digital audio signals from the input terminals 41A and 41B are supplied to the filters 47A and 47B and to the amplifiers 42A and 42B. At this time, the filters 47A and 47B are set as all-pass filters. Filters 47A and 4
The output of 7B is supplied to multiplier circuits 49A and 49B via delay circuits 48A and 48B, respectively.

The outputs of the filters 47A and 47B are supplied to a level comparison circuit 50. Level comparison circuit 50
The left and right audio signal levels are compared. The level comparison circuit 50 outputs the larger signal of the left and right audio signal levels. Level comparison circuit 50
Is supplied to the absolute value detection circuit 51. The absolute value detection circuit 51 calculates the absolute value of the larger one of the left and right audio signal levels. Absolute value detection circuit 51
Is supplied to the envelope detection circuit 52. The absolute value detection circuit 51 determines the envelope level of the larger of the left and right audio signal levels.

The output of the envelope detection circuit 52 is linear
The signal is supplied to a gain generation circuit 54 via a non-linear circuit 53. The linear-nonlinear circuit 53 includes an envelope detection circuit 5
2 is logarithmically converted. The gain generation circuit 54 generates a gain value according to the envelope level of the input signal. The output of the gain generation circuit 54 is a non-linear / linear circuit 55
Is supplied to the multiplication circuits 49A and 49B via the.

In the multiplication circuits 49A and 49B, the left and right digital audio signals are multiplied by the gain given from the gain generation circuit 54 via the non-linear circuit 55. When the envelope level of the input signal is large, the gain given to the multiplication circuits 49A and 49B is set small, and when the envelope level of the input signal is small, the gain given to the multiplication circuits 49A and 49B is set large. As described above, the gain is set nonlinearly with respect to the input signal level, the dynamic range of the input signal is compressed, and the small signal can be sufficiently reproduced.

The outputs of the multiplication circuits 49A and 49B are supplied to amplifiers 45A and 45B. In the DDS mode, the gains of the amplifiers 45A and 45B are set to 1, so that the outputs of the multiplication circuits 49A and 49B are supplied to the addition circuits 44A and 44B via the bit shift circuits 56A and 56B, respectively. In the DDS mode, since the gains of the amplifiers 42A and 42B are set to 0, no signal is output via the line 42A. Therefore, the bit shift circuit 56 is output from the adder circuit 44A.
Outputs of A and 56B are output as they are, and output from output terminals 57A and 57B.

When signal processing is performed in the audio DSP 10, an input signal is usually attenuated so that overflow does not occur. This attenuation is realized by the filters 47A and 47B. Since the attenuation is substantially a reduction in the number of bits, when the input signal is attenuated, the dynamic range is reduced and the distortion is increased.

In one embodiment of the present invention, in the normal mode, a signal is output via lines 43A and 43B and not through filters 47A and 47B. Therefore, in the normal mode, the signal is output without being attenuated, and the dynamic range does not decrease.

In this case, the output gain changes between the normal mode and the DBB mode or the DDS mode. That is, in the normal mode, the same output is obtained, but in the DBB mode or the DDS mode, the input signal is attenuated. So, DB
In the case of B mode or DDS mode, audio D
The gain of the analog amplifiers 13A and 13B (FIG. 1) is set to be large by the amount that the signal is attenuated when input to the SP10.

D. Implementation of Filter Configuration As described above, the filters 47A and 47B can be set as a low-pass filter and an all-pass filter by changing coefficients. FIG. 4 is an example of such a filter. In FIG. 4, 61 to 64 are one-sample delay circuits, 65 to 69 are multiplication circuits, and 70 is an addition circuit. When configuring a low-pass filter, the multiplication circuits 65 to 6
9 is set to an appropriate coefficient. In this case, the delay circuits 61 to 64, the multiplication circuits 65 to 68, and the addition circuit 70 constitute an IIR digital filter. Therefore, when a digital signal is supplied to the input terminal 71, the low frequency component is output from the output terminal 72.
When configuring an all-pass filter, the multiplication circuit 65
Is set to 1 and the coefficients of the other multiplication circuits 66 to 69 are set to 0. Therefore, when a digital signal is supplied to the input terminal 71, the signal is output as it is to the output terminal 7 as it is.
2 output. Thus, in such a filter, the characteristics can be changed by changing the coefficients of the multiplication circuits 61 to 66.

When signal processing is performed in the audio DSP 10, an input signal is usually attenuated so that overflow does not occur. This attenuation is set by the coefficients of the multiplication circuits 61 to 66. Note that an amplifier (attenuator) may be provided before the filter.

[0044]

According to the present invention, in the normal mode, a signal is output via the lines 43A and 43B, and the signals are not passed through the filters 47A and 47B. For this reason, in the normal mode, the signal is output without being attenuated, and the number of bits is not reduced even if the DSP 10 is used, so that the dynamic range is not reduced and the quantization distortion is not increased. In this case, the output gain changes between the normal mode and the DBB mode or the DSS mode. Therefore, in the case of the DDB mode or the DDS mode, the gain of the analog amplifiers 13A and 13B is set to be large as much as the signal is attenuated when input to the DSP 6.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a compact disc player to which the present invention is applied.

FIG. 2 is a flowchart used to describe an example of a compact disc player to which the present invention is applied.

FIG. 3 is a block diagram used for explaining an audio DSP in an example of a compact disc player to which the present invention is applied.

FIG. 4 is a block diagram used for explaining a filter of a DSP in an example of a compact disc player to which the present invention is applied.

FIG. 5 is a block diagram of an example of a compact disc player equipped with a conventional audio DSP.

FIG. 6 is a block diagram used for explaining a conventional audio DSP.

[Explanation of symbols]

 10 Audio DSP 13A, 13B Analog amplifier 43A, 43B Line through filter 47A, 47B Filter

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-64-41511 (JP, A) JP-A-1-176114 (JP, A) JP-A-1-284117 (JP, A) JP-A-1- 261997 (JP, A) JP-A-3-188800 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03G 9/14 H04S 5/02

Claims (3)

(57) [Claims] A normal mode and a variable sound field mode are selected.
In a sound field processing device that can be selectively set, the input two-channel digital audio signal
A pair of sound field processing and attenuation processing for each
The output signals from the filter means and the pair of filter means are compared to determine the level.
Comparing means for outputting an output signal having a large level, and detecting an absolute value of the output signal output from the comparing means.
Detection means and the envelope of the absolute value detected by the detection means.
And a gain value based on the output of the envelope detecting means.
Means for generating a gain value to be generated, and the input two-channel digital audio signal
The above gain value is generated after subjecting each of the signals to a predetermined delay processing.
First multiplying means for multiplying a gain value generated by the means, and multiplying an output signal from the first multiplying means by a predetermined gain.
Second multiplying means, and a predetermined gain for the input digital audio signal.
A third multiplying means for multiplying the output of said second multiplier means and the third multiplier adder
Adding means for performing the above operation. When the normal mode is selected, the second multiplying means
Multiply the gain so as to cut off the output of the
When the mode is selected, the output from the second multiplying means is blocked.
A sound field processing device characterized by multiplying a gain so as not to cut it . 2. The method according to claim 1, wherein the selected sound field variable mode is a low band strong mode.
In the case of the key mode, the output from the third multiplying means is
Multiplying gain so as not to block
Item 2. The sound field processing device according to item 1. 3. The selected sound field variable mode is a small signal
In the case of the mode of lifting the
Multiplying the gain to block the output And features
The sound field processing device according to claim 1.