JPH04372775A - Disk reproducing device - Google Patents

Abstract

PURPOSE:To attain the miniaturization and cost reduction of the equipment of a compact disk player equipped with a DSP. CONSTITUTION:The regenerative signal of the compact disk is decoded by a digital signal processing circuit 8. This decoded signal is signal-processed by an audio DSP 10, converted into an analog signal by a D/A converter 12, and outputted. As for the audio DSP 10, a mode or an effect amount can be set only by the setting of a coefficient. The management of this audio DSP 10 is operated by a CPU 6 for a system control. The control of the entire equipment, and the management of the audio DSP 10 can be operated by one CPU 6, so that the miniaturization and cost reduction of the equipment can be attained.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to a DSP for signal processing.
The present invention relates to a disc playback device suitable for use in a compact disc player equipped with a digital signal processor (Digital Signal Processor), and particularly relates to miniaturization and cost reduction of a compact disc player equipped with a DSP.

0002

2. Description of the Related Art Portable compact disc players equipped with an audio DSP are known. DSP is
A processor for performing digital signal processing, and can perform various signal processing depending on the program. for example,
When this DSP is installed in a portable compact disc player, it can perform processing such as boosting the low range to obtain powerful reproduced sound, and making low-pitched reproduced sound stand out.

[0003] Conventionally, when a DSP is installed, this D
A controller is required to control the SP. Therefore, in addition to the CPU for system control, conventional compact disc players equipped with a DSP have a DS
A CPU for P control is provided. However, with a dedicated CPU for DSP like this,
As the circuit size increases, the cost also increases.

That is, as shown in FIG.
In the installed compact disc player, an audio DSP 102 is provided at the subsequent stage of a digital signal processing circuit 100 that decodes a digital audio signal from a reproduction signal from the disc. In addition to the system control CPU 101 that controls the servo system and the entire system, there is also a DSP that controls the audio DSP 102.
A CPU 103 for SP control is provided. The audio DSP 102 performs signal processing such as low frequency emphasis and surround sound. The audio signal processed in this way is passed through the digital filter 104 and then sent to the D/A
It is supplied to converter 105. D/A converter 10
At 5, the digital audio signal is converted to an analog audio signal. These left and right analog audio signals are output from output terminals 107A and 107B via analog amplifiers 106A and 106B.

Conventional CPU 10 for DSP control
3 stores programs and data for realizing signal processing performed by the audio DSP 102. When the mode of the audio DSP 102 is changed, programs and data corresponding to this mode are called, and the audio DSP 102 is changed.
The SP 102 is newly implemented so that it can perform processing according to the mode.

For example, assume that the audio DSP 102 can be set to three types of modes: a normal mode, a DBB mode that emphasizes low frequencies, and a DSS mode that enhances small signals. In this case, conventionally, in order to realize signal flows in these three modes, separate program data and parameters are prepared in the DSP control CPU 103 for each mode.

FIGS. 6 to 8 show the flow of signals set when the normal mode, DBB mode, and DDS mode are set.

In the normal mode, as shown in FIG. 6, left and right digital audio signals from input terminals 111A and 111B are outputted from output terminals 113A and 113B via amplifiers 112A and 112B, respectively.

In the DBB mode, as shown in FIG. 7, left and right digital audio signals from input terminals 111A and 111B are supplied to adder circuits 114A and 114B, respectively, and are also supplied to low-pass filters 115A and 115.
A low frequency component is extracted through each of the amplifiers 116A and 116B, and is given an appropriate gain by amplifiers 116A and 116B, and then supplied to adder circuits 114A and 114B. Addition circuit 1
14A and 114B, input terminals 111A and 111B
The left and right digital audio signals from the left and right digital audio signals are added together with the low-frequency components that have been amplified by applying an appropriate gain. As a result, an audio signal with enhanced low frequency components is obtained. A signal with enhanced low frequency components is output from output terminals 113A and 113B.

In the DDS mode, as shown in FIG. 8, left and right digital audio signals from input terminals 111A and 111B are supplied to multiplication circuits 121A and 121B, respectively, and also to a gain setting circuit 123. A gain setting circuit 123 sets a gain according to the envelope level of the larger of the left and right input digital audio signals. This gain is supplied to multiplication circuits 121A and 122B, respectively. This results in
The gain is set nonlinearly with respect to the input signal level. In this way, signals obtained by nonlinearly amplifying the input signal are output from the output terminals 113A and 113B, respectively.

[0011] In a compact disc player equipped with a conventional audio DSP 102, normal mode, D
If the BB mode and DDS mode can be set, the program data and parameters for realizing the three types of signal flows shown in Figures 6 to 8 will be transferred to the DSP.
It must be prepared in the control CPU 103.

0012

[Means for Solving the Problems] As described above, in a compact disc player equipped with a conventional audio DSP, in addition to the CPU 101 for system control, the CPU 103 for controlling the audio DSP 102 is used.
This is an obstacle to miniaturization and cost reduction of equipment. It is desirable to be able to control the audio DSP 102 using only the CPU 101 for system control, but in the past, the program data and parameters for realizing each mode were set in the CPU 103.
It is difficult to control the audio DSP 102 alone.

[0013] Accordingly, an object of the present invention is to provide a disc playback device that can control an audio DSP using only a system control CPU.

[0014]

[Means for Solving the Problems] The present invention provides a read signal output section that drives a disk to read and output an audio signal encoded and recorded on the disk, and an audio signal outputted by the read signal output section. a first signal processing section that decodes a signal; a playback signal output section that converts the decoded audio signal into an analog signal and outputs a playback signal; a second signal processing section that controls the decoded signal from the signal processing section; and a central section that controls the read signal output section using the decoded signal from the first signal processing section and sends parameters to the second signal processing section. This is a disc playback device comprising a control section.

[0015]

[Operation] Since the audio DSP 10 can be controlled by the system control CPU 6, the equipment can be downsized and costs can be reduced. The signal flow of Audio DSP10 is realized in the same way, and the settings for each mode are supported only by changing the coefficients, so Audio DS
P10 management becomes easier and C for system control
The PU6 can control the audio DSP10.

[0016]

EXAMPLES Examples of the present invention will be described in the following order. a. Overall configuration of compact disc player b. Basic operation of system controller c. Realization of signal processing in audio DSP d. Realizing the configuration of the filter

a. Overall Configuration of Compact Disc Player An embodiment of the present invention will be described below with reference to the drawings. Figure 1
1 shows the overall configuration of a compact disc player to which the present invention can be applied. In FIG. 1, a compact disc 1 includes, along a spiral track,
A digital audio signal is recorded in a predetermined recording format. The compact disc 1 is rotationally controlled by a spindle motor 2 at CLV (constant linear velocity). Rotation control of the spindle motor 2 is performed by detecting the bit clock of the reproduction signal and using the CP for system control.
This is performed by the servo signal processing circuit 5 under the control of U6.

An optical pickup 3 is provided opposite the compact disc 1. A thread feed motor 4 is provided to move the optical pickup 3 in the radial direction of the compact disc 1. The thread feed motor 4 is moved along the radial direction of the compact disc 1 under the control of a CPU 6 for system control. The optical pickup 3 is provided with a two-axis device that controls the direction of the optical axis into two axes. This two-axis device uses a servo signal processing circuit 5 to control the CPU for system control.
6, and tracking servo and focus servo control are performed.

A reproduced signal from the optical pickup 3 is supplied to a CD digital signal processing circuit 8 via an RF amplifier 7. For the CD digital signal processing circuit 8, the memory 9
is provided. The CD digital signal processing circuit 8 shapes the waveform of the reproduced signal from the compact disc to form an EFM signal, demodulates this EFM signal, performs error correction processing, etc., and decodes left and right digital audio signals. . This CD digital signal processing circuit 8 is controlled by a CPU 6 for system control. Further, subcode information is obtained from the CD digital signal processing circuit 8, and this subcode information is supplied to the CPU 6 for system control.

The output of the CD digital signal processing circuit 8 is supplied to an audio DSP 10. Audio DSP1
0 performs signal processing on the reproduced sound as necessary. The audio DSP 10 can be set to, for example, a normal mode, a DBB (dynamic bass boost) mode, and a DDS (digital dynamic surround) mode. The DBB mode is a mode for processing to boost the low range and obtain powerful reproduced sound. The DDS mode is a mode in which processing is performed so that hidden, low-pitched reproduced sounds can be heard more prominently.

A dedicated CP for the audio DSP 10
No U is provided, and the audio DSP 10 is also controlled by the CPU 6 for system control. The reason why the audio DSP 10 can be controlled by the system control CPU 6 in this way is that each mode can be handled by simply changing the coefficients, and the audio DSP 10 can be managed more easily than in the past. Since a dedicated CPU is not provided for the audio DSP 10, the device can be made smaller and costs can be reduced. The fact that each mode can be handled simply by changing the coefficients will be explained later.

The output of the audio DSP 10 is supplied to a digital filter 11. The output of digital filter 11 is supplied to D/A converter 12 . The output of the D/A converter 12 is connected to the left and right analog audio amplifiers 1.
3A and 13B. The gains of the analog audio amplifiers 13A and 13B can be switched between the normal mode and the DBB mode or DDS mode. In the DBB mode or DDS mode, the gain is increased compared to the normal mode. This is to ensure that sufficient reproduced sound is obtained in the normal mode, and that input exceeding the dynamic range of the audio DSP 10 is not made to the audio DSP 10 in the DBB mode or DDS mode, as will be explained later. The outputs of the left and right analog audio amplifiers 13A and 13B are output from output terminals 14A and 14B.

[0023] The CPU 6 for system control includes:
Input is given from the input key 15. The control state of each system is set according to this input. Further, a display 16 is provided in the CPU 6 for system control. Necessary information is displayed on this display 16.

b. Basic operation of the system coat roller In one embodiment of the present invention, a C for system control is provided.
PU6 handles the entire system processing and audio DSP1
0 control is performed. At this time, the processing of the entire system is prioritized over the control of the audio DSP 10.

That is, FIG. 2 is a flowchart showing an overview of the processing performed by the system control CPU 6. When the start of performance is input from the input key 15, the system control CPU 6 powers on each circuit (step 21). Then, it waits while the power supply is stabilized (step 22). When the power became stable,
Initialization of the servo system and transfer of servo system data are performed (step 23). Then, the necessary data is transferred to the audio DSP 10 (step 24). Once the necessary data has been transferred, the performance will begin (step 2).
5).

During the performance, it is determined whether subcode information has been sent (step 26). Subcode information is obtained, for example, approximately every 13 msec. When the subcode information is received, the subcode information is read (step 27), and it is determined whether the audio DSP flag is set (step 28). audio DS
If the P flag is not set, the process returns to step 26 and the subcode information reading process continues.

When it is determined in step 26 that subcode information has not arrived, that is, while subcode information is being obtained, display processing, search processing, and input reading processing are performed (step 29). Then, it is determined whether the mode or effect amount of the audio DSP 10 has been changed (step 30). Audio DSP1
If the mode and effect amount of 0 have not been changed, the process returns to step 26 and the subcode information reading process is continued.

If the mode and effect amount of the audio DSP 10 have been changed in step 30, it is determined whether subcode information is being sent (step 31). If subcode information has not been sent, processing is performed to change the mode and effect amount of the audio DSP 10 (step 32). The audio DSP flag is then cleared (step 33).
. Then, the process returns to step 26 to continue reading the subcode information.

In step 30, even if the mode or effect amount of the audio DSP 10 has been changed, if subcode information is being sent, this processing must be given priority. Therefore, if it is determined in step 31 that subcode information is being sent, the audio D
The SP flag is set (step 34) and step 2
It will be returned to 6.

If the audio DSP flag is set, the subcode information is read in step 27, and then it is detected in step 28 that the audio DSP flag is set, and the process goes to step 32, where the mode of the audio DSP 10 is Processing is performed to change the effect amount. Then, in step 33, the audio DSP flag is cleared, and then the process returns to step 26 to continue reading the subcode information.

As described above, in one embodiment of the present invention, the system control CPU 6 processes the entire system and controls the audio DSP 10. Generally speaking, the control at this time can be said to perform processing for changing the mode and effect amount of the audio DSP 10 during the time to read the subcode information. Therefore, the process for changing the mode and effect amount of the audio DSP 10 must be completed while the subcode information is being read (approximately 13 msec).

[0032] Conventionally, DSP programs are set to perform signal processing corresponding to each mode. Therefore, it is difficult to change the mode in such a short time. Therefore, in one embodiment of the present invention, mode change processing and effect amount setting can be handled by changing several sets of coefficients. Therefore, processes such as changing the mode and setting the amount of effect can be sufficiently performed during the time for reading the subcode information.

c. Realization of signal processing in audio DSP This audio DSP 10 will be explained. Figure 3 shows
It shows the flow of signal processing realized by the audio DSP 10. The audio DSP 10 includes only a signal processing circuit as shown in FIG. 3, and the mode can be changed by changing the coefficients of this signal processing circuit. That is, in the normal mode, the amplifiers 42A and 4
The gain of 2B is set to 1, and the gains of amplifiers 45A and 45B are set to 0. When in DBB mode, amplifier 42A
and 42B are set to 1, and the gains of amplifiers 45A and 45B are set to 1, and the filters 47A and 47
B is set as a low-pass filter. In the DDS mode, the gains of amplifiers 42A and 42B are set to 0, and the gains of amplifiers 45A and 45B are set to 1. Along with this, filters 47A and 47B are set as all-pass filters. The effect amount of each mode is set by the shift amount of shift registers 56A and 56B.

The gains of the amplifiers 42A and 42B and the gains of the amplifiers 45A and 45B can be set simply by changing the coefficients. The shift amounts of shift registers 56A and 56B can also be set simply by changing the coefficients. Furthermore, the filter 47
The settings of the characteristics of A and 47B can also be changed by simply setting the coefficients, as will be explained later.

First, the signal flow in the normal mode will be explained. In the normal mode, the gains of amplifiers 42A and 42B are set to 1, and the gains of amplifiers 45A and 45B are set to 0. In normal mode, input terminal 4
Left and right digital audio signals are supplied to 1A and 41B, respectively. These left and right input digital signals are supplied to amplifiers 42A and 42B, respectively. In normal mode, the gains of amplifiers 42A and 42B are set to 1, so signals from input terminals 41A and 41B are sent to lines 43A and 43B, amplifier 42 with a gain of 1.
The signals are supplied to adder circuits 44A and 44B via circuits A and 42B, respectively. On the other hand, in the normal mode, the gains of the amplifiers 45A and 45B are set to 0, so the signals transmitted through the lines 46A and 46B are not output. Therefore, in the normal mode, signals from the input terminals 41A and 41B are directly transmitted to the output terminals 57A and 57.
Output from B.

In the DBB mode, the gains of amplifiers 42A and 42B are set to 1, the gains of amplifiers 45A and 45B are set to 1, and filters 47A and 47B are set to be low-pass filters. In the DBB mode, left and right digital audio signals from input terminals 41A and 41B are supplied to filters 47A and 47B, and also to amplifiers 42A and 42B, respectively. Since the filters 47A and 47B are low-pass filters, the filters 47A and 47B extract low frequency components in the left and right input digital signals. The low frequency components in the left and right input digital signals are connected to lines 46A and 46B and delay circuits 48A and 48B.
are supplied to multiplication circuits 49A and 49B, respectively.

The outputs of the filters 47A and 47B are also supplied to a level comparison circuit 50. Level comparison circuit 50
The left and right audio signal levels are compared. The level comparison circuit 50 outputs the signal with the higher level of the left and right audio signals. Level comparison circuit 50
The output of is supplied to the absolute value detection circuit 51. The absolute value detection circuit 51 determines the absolute value of the higher of the left and right audio signal levels. Absolute value detection circuit 51
The output of is supplied to the envelope detection circuit 52. The envelope detection circuit 52 determines the envelope level of the larger of the left and right audio signal levels.

The output of the envelope detection circuit 52 is linear -
The signal is supplied to a gain generation circuit 54 via a nonlinear circuit 53. The linear-nonlinear circuit 53 is an envelope detection circuit 5
Logarithmically transform the output of step 3. The gain generation circuit 54 generates data for setting a gain according to the envelope level of the input signal. The output of the gain generation circuit 54 is sent to the multiplier circuits 49A and 4 through the nonlinear-linear circuit 55.
9B.

In the multiplier circuits 49A and 49B, the low frequency components of the left and right audio signals are multiplied by the gain provided from the gain generation circuit 54 via the nonlinear-linear circuit 55. The outputs of the multiplier circuits 49A and 49B are connected to the amplifier 4.
5A and 45B, respectively. In the DBB mode, the gains of the amplifiers 45A and 45B are set to 1, so the outputs of the multiplier circuits 45A and 45B are sent to the bit shift circuits 56A and 56 via the amplifiers 45A and 45B.
B is supplied respectively. Bit shift circuits 56A and 56
The shift amount of B is set according to the effect amount. Bit shift circuits 56A and 56B bit shift the outputs of amplifiers 45A and 45B, respectively. By bit-shifting the data in this manner, the enhancement level of the low frequency components of the left and right audio signals is set.

The outputs of bit shift circuits 45A and 45B are supplied to adder circuits 44A and 44B, respectively. Addition circuits 44A and 44B add the left and right digital audio signals passed through lines 43A and 43B, and the low frequency components enhanced via filters 47A and 47B and lines 46A and 46B. This enhances the low frequency components of the audio signal. Left and right audio signals with enhanced low frequency components are output from output terminals 57A and 57B, respectively.

In the DDS mode, the gains of amplifiers 42A and 42B are set to 0, and the gains of amplifiers 45A and 45
The gain of B is set to 1. Along with this, filter 4
7A and 47B are set as all-pass filters. D
In the DS mode, left and right digital audio signals from input terminals 41A and 41B are supplied to filters 47A and 47B, as well as amplifiers 42A and 42B. At this time, filters 47A and 47B are set as all-pass filters. Filters 47A and 4
The output of 7B is supplied to multiplication circuits 49A and 49B via delay circuits 48A and 48B, respectively.

The outputs of filters 47A and 47B are also supplied to level comparison circuit 50. Level comparison circuit 50
The left and right audio signal levels are compared. The level comparison circuit 50 outputs the signal with the higher level of the left and right audio signals. Level comparison circuit 50
The output of is supplied to the absolute value detection circuit 51. The absolute value detection circuit 51 determines the absolute value of the higher of the left and right audio signal levels. Absolute value detection circuit 51
The output of is supplied to the envelope detection circuit 52. The absolute value detection circuit 51 determines the envelope level of the larger of the left and right audio signal levels.

The output of the envelope detection circuit 52 is linear -
The signal is supplied to a gain generation circuit 54 via a nonlinear circuit 53. The linear-nonlinear circuit 53 is an envelope detection circuit 5
Logarithmically transform the output of 2. The gain generation circuit 54 generates a gain value according to the envelope level of the input signal. The output of the gain generation circuit 54 is a nonlinear-linear circuit 55
The signal is supplied to multiplication circuits 49A and 49B via.

[0044] In the multiplier circuits 49A and 49B, the left and right digital audio signals are multiplied by the gain provided from the gain generation circuit 54 via the nonlinear-linear circuit 55. When the envelope level of the input signal is high, the gain given to the multiplication circuits 49A and 49B is set small, and when the envelope level of the input signal is small, the gain given to the multiplication circuits 49A and 49B is set large. In this way, the gain is set nonlinearly with respect to the input signal level, the dynamic range of the input signal is compressed, and small signals can be sufficiently reproduced.

The outputs of multiplier circuits 49A and 49B are supplied to amplifiers 45A and 45B. In the DDS mode, the gains of amplifiers 45A and 45B are set to 1, so the outputs of multiplier circuits 49A and 49B are sent to adder circuits 44A and 4 through bit shift circuits 56A and 56B, respectively.
4B respectively. In DDS mode, the gains of amplifiers 42A and 42B are set to 0, so
The signal passed through line 42A is not output. Therefore, the adder circuit 44A outputs the outputs of the bit shift circuits 56A and 56B as they are, and this is the output terminal 5.
Output from 7A and 57B.

Note that when signal processing is performed within the audio DSP 10, the input signal is normally attenuated to prevent overflow. This attenuation is achieved by filters 47A and 47B. Attenuation is essentially a reduction in the number of bits, so attenuating an input signal reduces the dynamic range and increases the distortion rate.

In one embodiment of the invention, when in normal mode, signals are output via lines 43A and 43B and are not passed through filters 47A and 47B. Therefore, in the normal mode, the signal is output without being attenuated, and the dynamic range does not decrease.

[0048] If this is done, the output gain will differ between the normal mode and the DBB mode or DDS mode. That is, in the normal mode, the same output is obtained, but in the DBB mode or the DDS mode, the input signal is attenuated. Therefore, DBB
mode or DDS mode, audio DS
Since the signal is attenuated when input to P10,
The gains of analog amplifiers 13A and 13B are set large.

d. Realization of Filter Configuration As described above, the filters 47A and 47B can be set as a low-pass filter or an all-pass filter by changing the coefficients. FIG. 4 is an example of such a filter. In FIG. 4, 61 to 64 are 1 sample delay circuits, 65 to 69
is a multiplication circuit, and 70 is an addition circuit. When configuring a low-pass filter, appropriate coefficients are set in multiplication circuits 65-69. In this case, delay circuits 61 to 64, multiplication circuits 65 to 68, and addition circuit 70 constitute an IIR type digital filter. Therefore, input terminal 7
When a digital signal is supplied to the output terminal 72, its low frequency component is output from the output terminal 72. When configuring an all-pass filter, only the multiplication circuit 65 is set to 1, and the coefficients of the other multiplication circuits 66 to 69 are set to 0. Therefore, when a digital signal is supplied to the input terminal 71, that signal is output as is from the output terminal 72. In this way, in such a filter, the multiplication circuits 61 to
By changing the 66 coefficients, the characteristics can be changed.

[0050] When signal processing is performed within the DSP 10,
Typically, the input signal is attenuated to prevent overflow. This attenuation is performed by the multiplication circuit 61
It is set by a coefficient of ~66. Note that an amplifier (attenuator) may be provided before this filter.

[0051]

According to the present invention, the system control CPU 6 can control not only the entire system but also the audio DSP 10, so that the equipment can be downsized and costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a flowchart used to explain one embodiment of the present invention.

FIG. 3 is a block diagram used to explain a DSP in an embodiment of the present invention.

FIG. 4 is a block diagram used to explain a DSP filter in an embodiment of the present invention.

FIG. 5 is a block diagram of an example of a compact disc player equipped with a conventional DSP.

FIG. 6 is a block diagram used to explain a conventional DSP.

FIG. 7 is a block diagram used to explain a conventional DSP.

FIG. 8 is a block diagram used to explain a conventional DSP.

[Explanation of symbols]

1 Compact disk 6 CPU 10 for system control Audio DSP

Claims (1)

[Claims] 1. A read signal output section that drives a disk to read and output an audio signal coded and recorded on the disk, and a first signal that decodes the audio signal output by the read signal output section. a processing section, a reproduction signal output section that converts the decoded audio signal into an analog signal and outputs a reproduction signal, and a parameter that determines the signal waveform of the reproduction signal,
a second signal processing section that controls the decoded signal from the first signal processing section; and a second signal processing section that controls the read signal output section using the decoded signal from the first signal processing section;
a central control section that sends the parameters to the second signal processing section.