JP2943112B2 - Digital signal processor - Google Patents

Description

The present invention relates to a digital signal processing device that processes data input in time series based on a predetermined algorithm and outputs the data as time series data. (B) Conventional technology Generally, primitive information sources existing around us, such as voices and images, are often analog signals. A system that processes this analog signal by a digital method is a digital signal processing device (digital signal processing system: DSP system). In recent years, digital circuits have rapidly become LSIs, and DSP systems can be easily realized on one chip. Furthermore, high-precision processing is possible compared to analog signal processing, and arbitrary characteristics can be stabilized by setting parameters. Features such as uniform acquisition and no adjustment
The system has been rapidly commercialized. Also, DS
The application range of the P system is widely used for audio signal processing, communication signal processing, measurement signal processing, image signal processing, seismic wave signal processing, underwater acoustic signal processing, and the like. Also, in the audio field, as digital processing of audio signals progresses, such as CD (compact disk) players and DAT (digital audio tape) players, DS that digitally processes audio signals is used.
The P system has been put into practical use. The conventional DSP system has an architecture shown in FIG. 6 so that a digital filter can be easily formed. In FIG. 6, an input / output circuit (I
/ O) (1), data RAM (2), multiplier (3), arithmetic circuit (ALU) (4), accumulator (ACC) (5), etc. are connected, and output of data RAM (2) and data ROM The output of (6) is connected to the multiplier (3), and the multiplication result output of the multiplier (3) is applied to one input of the ALU (4). Each of these circuits is controlled by a microcode signal output according to the instruction from a decoder (8) that decodes an instruction sequentially read from the program ROM (7). In the realization of digital filters _{Y = A · x i + B} · x i-1 + C · x i-2 sum of products form of ...... cracking repeated table. When this digital filter is implemented by a DSP system, the calculation order of the nodes in the filter is determined, a program is created, and the program is stored in the program ROM (7) and calculated in the data ROM (6). Stores the constant of the expression. Then, by executing the program, a product-sum operation is performed, and the operation results are sequentially stored in the data RAM (2). (C) Problems to be solved by the invention When the DSP system shown in FIG. 6 is used in the audio field, it is necessary for audio such as a graphic equalizer function, bass treble, loudness, low boost function, and surround effect function. Although various functions can be realized, since the audio signal has two channels of left and right, processing for realizing the above function must be performed on the signals of the left and right channels, respectively. In order to change the characteristics of the left and right channels independently, different constants must be written in the data ROM. Therefore, in a CD player or a DAT player, since the signal sampling cycle is a high frequency such as 44.1 KHz or 48 KHz, all processing for realizing the above-described functions is performed between the left and right channels during the sampling cycle. Each must be done. Therefore, depending on the processing speed of the DSP system, it may not be possible to realize any of the above functions. That is, there is a disadvantage that the throughput of the DSP system is deteriorated. (D) Means for Solving the Problems The present invention has been made in view of the above points, and has a pair of digital processing circuits having a multiplier and an ALU for performing arithmetic processing on input digital data. A pair of data buses for performing data transfer in each of the digital processing circuits,
A program memory in which a program is stored, and a sole control circuit that decodes the instructions constituting the program and outputs only a control signal and controls the pair of digital processing circuits by the control signal The same control signal output based on the same instruction in the program is output to the pair of digital processing circuits, and the pair of digital processing circuits input digital data according to the same control signal. It is an object of the present invention to provide a digital signal processing device that simultaneously processes left and right channel signals by performing arithmetic processing at the same time and improves throughput. (E) Operation According to the above-described means, for example, when a program for realizing a digital filter is executed, each of a pair of digital processing circuits is simultaneously controlled by a control signal output from the control circuit. Two input data:
The product-sum operation is performed on the data of the left channel and the right channel at the same time, and the filtering operation is performed. Thus, a throughput twice as high as that of the related art can be obtained. Also, when different filter characteristics are obtained for the left and right channels, it can be realized by storing different constants in each digital processing circuit and then performing the same product-sum operation. (F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.
A pair of digital processing circuits (9) and (10) and data buses (BUS1) (BUS2) (1) of the digital processing circuits (9) and (10)
The data input / output circuit (12) connected to the data bus (11) and the interface circuit (1) also connected to the data bus (11)
3) and these digital processing circuits (9) (10), data input / output circuit (12), and interface circuit (1
This is an audio DSP system composed of a control circuit (14) for controlling the operation of 3). The data bus (11) has a 24-bit configuration of 8 bits × 3. The data input / output circuit (12) serially inputs 16-bit left channel and right channel sampling data (for example, data of a sampling frequency of 44.1KHz in the case of a CD player) externally applied to the input terminal IN. , Left channel data is BU of data bus (11)
The data of the right channel is BUS2 of the data bus (11) on S1.
And further receives the processed left channel data transmitted to the data bus BUS1 and the processed right channel data transmitted to the data bus BUS2, and outputs the output terminal OUT
And serially output the data alternately. The interface circuit (13) transmits and receives data between the DSP system and the microcomputer (not shown), and sends a digital filter constant or the like applied from the microcomputer to the data bus (11). , Receives the system status data and the like sent to the data bus (11) and sends it to the microcomputer. The data processing circuit (9) is for data processing of the left channel, and the data processing circuit (10) is for data processing of the right channel, each having exactly the same configuration. That is, the data processing circuits (9) and (10) are connected to the data bus (11) and the data RAM.
(15), constant RAM (16), constant ROM (17), address pointer (18) (19) (20), multiplier (MUL) (21), (AL
U) (22), an accumulator (ACC) (23), and temporary registers (TMP1, TMP2,...) (24). The data RAM (15) stores data before processing and data after arithmetic processing sent from the data input / output circuit (12).
This is a first RAM having a capacity of 24 bits × 128, and is connected to a data bus (11) and an input of a multiplier (21). Constant RA
M (16) is a second RAM having a capacity of 16 bits × 256 for storing constants such as coefficients of a digital filter sent from the interface circuit (13), and a data bus (11).
And the other input of the multiplier (21). The address pointer (18) is composed of 8 bits and has a data RAM (1
The address is specified in 5), and the control circuit (14)
Is controlled by the microcodes INC1 and DEC1 output from the controller, and the stored address data is incremented (+
In addition to the functions of 1) and decrementing (-1), a register capable of setting an arbitrary value by a program and a circuit for comparing the set value with address data are incorporated. It has a function of becoming a set value when the result of the decrement becomes less than "0" when it exceeds "0", that is, a function of circulating between "0" and the set value. This cyclic addressing function is used to simplify the product-sum operation of the digital filter. The address pointer (19) is a 10-bit pointer that specifies the address of the constant RAM (16), and is controlled by the microcode INC2 output from the control circuit (14). It has a function of incrementing data and a function of being cleared to "0" by a microcode CLEAR2 output from the control circuit (14). In addition, the address pointer (20)
Is an 8-bit pointer that specifies the address of the constant ROM (17), and has a function of decrementing address data by the microcode DEC3 output from the control circuit (14). The multiplier (21) performs multiplication of 24 bits × 16 bits. The A input is 24 bits and the B input is 16 bits, and the multiplication result is determined after one cycle. Further, an input selection circuit is connected to the A input and the B input of the multiplier (21).
MPXA and MPXB are provided, and the input selection circuit MPXA selects the data bus (11) by the microcode A-BUS from the control circuit (14), and the data is transmitted by the microcode A-DRAM.
Select RAM (15), apply to A input, input select circuit MPX
B selects the data bus (11) by the microcode B-BUS, and the constant RAM (16) by the microcode B-CRAM.
Is selected, and the constant ROM (1
7) is selected and applied to the B input. The multiplication result is output in 32 bits. ALU (22) is a 32-bit arithmetic circuit. The 32-bit multiplication result input to one side and the 32-bit ACC (23) data input to the other side are added by microcode ADD, and the result is added. To the ACC (23). ACC (23)
Of the 32 bits, the upper 24 bits are connected to the data bus (11), and the lower 8 bits are connected to the lower 8 bits of the temporary register (24) by the auxiliary bus (25). The temporary register (24) is composed of 32-bit registers TMP1, TMP2,..., TMP8, and holds up to eight 32-bit data. The upper 24 bits of each are connected to the data bus (11). With the data bus (11) and the auxiliary bus (25), temporary registers (24)
Transfer of 32-bit data is performed between ACC (23). The control circuit (14) is a program for storing a program.
ROM (26), program counter (PC) (27) for specifying the address of program ROM (26), and instruction decoder (I-DEC) for decoding the read instruction
(28). The program ROM (26) has a capacity of 32 bits × 512, and stores a program for realizing a digital filter and other necessary programs. The instruction decoder (28) decodes the instruction and outputs microcode, and controls the address pointers (18), (19) and (20) INC1, INC2, and DEC.
1, CLEAR2, DEC3 and input selection circuits MPXA, MPXB.
A-BUS, A-DRAM, B-BUS, B-CRAM, B-CROM, or AL
Outputs ADD, THR, etc. that control U (22). Since the microcode is applied to a common circuit of each part of the data processing circuits (9) and (10), the same control is simultaneously performed on the data processing circuits (9) and (10) by executing one instruction. . FIG. 2 shows an example of instructions necessary to construct a digital filter in the DSP system shown in FIG. In FIG. 2, a MUL instruction is a multiplication instruction, which selects an object to be input to the input A and the input B of the multiplier (21) and performs multiplication. The AP instruction increments, decrements, or clears the address pointers (18), (19), and (20). ALU instruction is ALU
ALUADD is a control instruction of (22). ALUADD adds two input data by ALU (22), and stores the addition result in ACC (23). ALUTHR is a multiplication result from multiplier (21). In the ACC (23). RAM1D, TMP1D, T
MP2D is a store instruction, and stores data on the data bus (11) in the data RAM (15) and the temporary register (24). ACCS, TMP1S and TMP2S are transfer instructions, and ACC (2
3) This is an instruction to send the data of the temporary register (24) to the data bus (11) and the auxiliary bus (25). By the way, when realizing a graphic equalizer in audio signal processing, y _i = x _i A + x _i-1 B + x _i-2 C + y _i-1 D + y _i-2 E (A, B, C, D, E are The constant is obtained by cascading a plurality of band digital filters realized by the product-sum operation represented by the following expression. FIG. 3 realizes a two-band graphic equalizer by cascading two stages of band-pass digital filters of a secondary direct IIR filter. In FIG. 3, (29) Z ^-1 is a delay element for a unit time (here, a sampling period), (30) is a multiplication element of constants A to J, and (31) is an addition element. x _i is the input data input to the filter, and z _i is the filter output. In the case of an audio system, such filtering must be performed on the left channel signal and the right channel signal. In the DSP system shown in FIG. 1, a program for realizing the digital filter shown in FIG. Since the digital processing circuits (9) and (10) perform the same operation by one execution of (1), filter processing is performed on the left channel signal and the right channel signal simultaneously. Therefore, in the DSP system shown in FIG. 1, the operation for realizing the digital filter shown in FIG. 3 will be described with reference to FIGS. FIG. 4 is a diagram showing a program for realizing the digital filter of FIG. 3, and FIG. 5 is an allocation diagram of data stored in a data RAM (15) and a constant RAM (16). According to the program shown in FIG. 4, constant multiplication is performed by C, B, A,
In order to perform the processing in the order of E, D, H, G, F, J, and I, constants are stored in the same order at addresses “0” to “9” of the constant RAM (16). On the other hand, data of x _i , y _i , and z _i are written in the data RAM (15) every three addresses. However, in the sampling period, that is, in each filtering process period for one input data x _{i + 1} , By writing x _{i + 1} , y _{i + 1} , and z _{i + 1} shifted by one address, the delay data by the delay element (29) is created. Therefore, in the case of the digital filter shown in FIG. 3, the address pointer (18) is "0" to
The cyclic address designation of "7" and the address pointer (19) are set by a program so as to designate the cyclic address of "0" to "9". Here, in the time of performing step "0" in the fourth diagram of the program for the input data x _i, the data RAM (1
When the contents of 5) are as shown in FIG. 5A and the address pointers (18) and (19) are both at the address "0",
When step “0” is executed, the input A of the multiplier (21)
And B, the data x _i−2 (input data two samples before) stored at the address “0” of the data RAM (15) and the coefficient stored at the address “0” of the constant RAM (16) C is applied, and the result of the multiplication is determined and output in the next step. At the end of step “0”, the instruction
Address pointer (18) (19) by AP1INC and AP2INC
Are both incremented, and the content becomes “1”. When step "1" is executed, the data RAM (15) and the constant RAM (16) are selected as inputs to the multiplier (21), as in step "0", and are respectively stored at the address "1". The data x _i-1 and the constant B are applied to the multiplier (21). The result multiplied in the previous step "0" is the instruction AL
By UTHR, the first multiplication result C · x _i−2 is stored in ACC (23) through ALU (22). At the end of step "1", the instructions AP1INC and AP2INC cause the address pointer (1
8) (19) is incremented, and the content becomes address “2”. Next, when step "2" is executed, the instruction MULA-BU
The S, H-CRAM selects the data bus (11) as the input A of the multiplier (21) and the constant RAM (16) as the input B. On the other hand, the instruction TMP1S sends out the contents of the temporary register TMP1 to the data bus (11), and the instruction RAM1D
The data sent to the data bus (11) is stored at the address "2" of the data RAM (15) specified by the address pointer (18). At this time, the temporary register TMP1 stores the data input circuit (1
Input data x _i that is applied from the outside it is pre-stored in 2). Accordingly, the input data x _i is a multiplier (21) while being multiplied by a constant A which is read from the constant RAM (16) by and stored in the address of the data RAM (15) "2". On the other hand, according to the instruction ALUADD, the multiplication result B · x of C · x _i−2 stored in ACC (23) and step “1” is obtained.
_i−1 is added, and as a result, B · x _i−1 + C · x _i−2 becomes ACC
Stored in (23). At the end of step "2", the address pointers (18) and (19) are incremented, and the content becomes address "3". When the step "3" is executed, the inputs A and B of the multiplier (21) contain the data _yi-2 stored at the address "3" of the data RAM (15) and the constant RAM (16). constant E is applied, the instruction ALUADD, step contents _{B · x i-1 + C} · x i-2 "2" of the multiplied result a · x _i and ACC (23) are ALU (2
Is added at the 2), the addition result _{A · x i + B · x} i-1 + C
X _i-2 is stored in ACC (23). At the end of step "3", the address pointers (18) and (19) are incremented to become address "4". When the step "4" is executed, the inputs A and B of the multiplier (21) include the data y _i-1 stored at the address "4" of the data RAM (15) and the constant RAM (16). The constant D is applied, and the multiplication result E · y _{i−2 of} step “3” and the contents A · x _i + B · x _i−1 + C · x of the ACC (23) are applied by the instruction ALUADD.
_i-2 is added in the ALU (22), and the addition result A · x _i + B
X _i-1 + C x _i-2 + E y _i-2 is stored in ACC (23). At the end of step "4", the instructions AP1DEC and AP2INC decrement the address pointer (18) to address "3" and increment the address pointer (19) to address "5". When the step "5" is executed, the inputs A and B of the multiplier (21) include the data y _i-2 stored at the address "3" of the data RAM (15) and the address of the constant RAM (16). The constant H stored in “5” is applied. That is, the multiplier (21) performs the second-stage multiplication of the digital filter shown in FIG. 3 from step "5". On the other hand, the instruction AL
By UADD, the multiplication result D · y _{i−1 of} step “4” and ACC
Contents of (23) A x _i + B x _i-1 + C x _i-2 + E y _i-2
Addition is performed in ALU (22), and the addition result A · x _i + B · x
_i-1 + C.x _i-2 + D.y _{i + 1} + E.y _i-2 is stored in ACC (23). The content of ACC (23) at this time becomes the output y _i of the first-stage digital filter. At the end of step "5", the address pointer (18) is incremented to address "4", and the address pointer (19) is incremented to address "6". When the step "6" is executed, the inputs y and b of the multiplier (21) include the data y _i-1 stored at the address "4" of the data RAM (15) and the address of the constant RAM (16). The constant G stored in “6” is applied. Also the instruction
ACCS, the data y _i which is stored in the ACC (23) is sent to the data bus (11), the instruction TMP2D, data bus (11) to the delivery data y _i is temporary register
Stored in TMP2. On the other hand, according to the instruction ALUTHR, the multiplication result H · y _i−2 of step “5” passes through the ALU (22) and is stored in the ACC (23). At the end of step "6", the address pointers (18) and (19) are incremented to become address "5" and address "7". When step "7" is executed, the instruction MULA-BUS, B-C
The RAM sends the data sent to the data bus (11) and the constant F stored at address "7" of the constant RAM (16) to the inputs A and B of the multiplier (21). Also,
The instruction TMP2S and RAM1D cause the temporary register TMP2
The stored data y _i in is sent to the data bus (11) multipliers while being applied to the input A (21), the address of the data RAM designated by the address pointer (18) (15) "5 Is stored. On the other hand, the multiplication result G · y _i−1 of step “6” and H · y of ACC (23) are obtained by the instruction ALUADD.
_i-2 is added at ALU (22), and as a result, G · y _i-1 +
H.y _i-2 is stored in ACC (23). Step "7"
Finally, the address pointers (18) and (19) are incremented to become address "6" and address "8". When the step "8" is executed, the inputs A and B of the multiplier (21) contain the data z _i-2 stored at the address "6" of the data RAM (15) and the address of the constant RAM (16). The constant J stored at “8” is applied while the ALU (2
In step 2), the multiplication result F · y _i and ACC (2
The data G · y _i−1 + H · y _i−2 stored in 3) is added, and as a result, F · y _i + G · y _i−1 + H · y _i−2 becomes ACC (23).
Stored in At the end of step "8", the address pointers (18) and (19) are incremented to become address "7" and address "9". When the step "9" is executed, the inputs z and _i of the constant (16) and the data z _i-1 stored at the address "7" of the data RAM (15) are inputted to the inputs A and B of the multiplier (21). The constant I stored at "9" is applied while the ALU (2
In step 2), the multiplication result J · z _{i−2 of} step “8” and ACC
Data F · y _i + G · y _i−1 + H · y stored in (23)
_i−2 is added, and the addition result F · y _i + G · y _i−1 + H · y _i−2
+ J · z _i−2 is stored in ACC (22). When the address pointers (18) and (19) are incremented at the end of step "9", the address pointers (18) and (19) both become the address "0". When step “10” is executed, no multiplication is performed, and the multiplication result I · z _{i−1 of} step “9” and data F · y _i + G · y _i−1 + H · H stored in ACC (23) are obtained. y _i-2 + J ・ z _i-2
Addition is performed in ALU (22), and the addition result F · y _i + G
Y _i-1 + H y _i-2 + I z _i-1 + J z _i-2 is stored in ACC (23). The data of ACC (23) at this time becomes the output z _i of the second stage digital filter. Finally, when step “11” is executed, the data z _i stored in ACC (23) by the instruction ACCS is transferred to the data bus (1).
The data z _i transmitted to the data bus (11) and sent to the data bus (11) is stored at the address “0” of the data RAM (15) specified by the address pointer (18) by the instruction RAM 1D. At the end of step "11", the address pointer (18)
Is incremented to the address “1”. Therefore, the next time the program is executed again from step "0", the data RAM (15) addressed by the address pointer (18) will be accessed from address "1", and the previous start address One address ahead. By executing the above program steps "0" to "11", the filter processing is performed for the input data x _i, the contents of the data RAM (15) is changed as FIG. 5 (b), the filter output z _i is obtained. Further, by advancing the start address by one address for the filtering process of the next sampling data x _{i + 1} , delayed data for the data x _{i + 1} can be obtained. Therefore, step "0"
By repeatedly executing the program of "11" to the sampling data, the data RAM (15) changes as shown in FIGS. 5 (c) and (d), and the filter outputs z _{i + 1} , z _{i +2} …
... is obtained. The above operations are performed simultaneously in the digital processing circuits (9) and (10), so that filter output data of the left channel and the right channel can be obtained at the same time. Further, before executing the program of FIG. 4, the constants stored in the constant RAM (16) of the digital processing circuits (9) and (10) are changed in advance, so that the filter characteristics of the left channel and the right channel are changed. That is, the level of the graphic equalizer can be left and right independent. In this case, constant writing to the constant RAM (16) is performed by transferring a constant applied from the microcomputer to the interface circuit (13) to the constant RAM (16). (G) Effects of the Invention As described above, according to the present invention, by executing a program for realizing a digital filter, one set of digital processing circuits operate simultaneously and one set of digital filters can be realized. The digital signal processing of the audio signal of the right channel and the right channel can be performed in about half of the conventional program length, and there is an advantage that the functions that can be realized during the sampling period are increased. Therefore, an easy-to-use DSP device with improved throughput can be obtained. Further, in the present invention, only one instruction decoder is required to control a pair of digital processing circuits, so that the hardware configuration can be simplified.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 2 is a block diagram shown in FIG. 1 showing instructions necessary for realizing a digital filter; FIG. 3 is a diagram showing a second-order direct type IIR digital filter connected in two stages, FIG. 4 is a diagram showing a program for realizing the digital filter of FIG. 3 in the embodiment of FIG. 1, and FIG. FIG. 2 is an address assignment diagram of a data RAM and a constant RAM, and FIG. 6 is a block diagram showing a conventional example. (9) (10) ... digital processing circuit, (12) ... data input / output circuit, (13) ... interface circuit, (14)
Control circuit, (11) Data bus, (15) Data RAM, (16) Constant RAM, (17) Constant ROM, (1
8) (19) (20) ... address pointer, (21) ... multiplier, (22) ... ALU, (23) ... accumulator (A
CC), (24) Temporary register, (25) Auxiliary bus, (26) Program ROM, (27) Program counter, (28) Instruction decoder, (29) Delay element , (30) ... Multiplier, (31)
... Addition element.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideki Ohashi 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Masaki Kawaguchi 2-18-18 Keihanhondori, Moriguchi-shi, Osaka (56) References JP-A-61-16369 (JP, A) JP-A-59-172065 (JP, A) JP-A-61-110256 (JP, A) JP-A-60-241130 (JP JP, A) Shinji Tomita, Parallel Computer Architecture, Shokodo (S61-11) 100-P130 (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 15/16 G06F 15/80

Claims (1)

(57) [Claims] A digital signal processing device for performing signal processing on a stereo audio signal having two left and right channels, comprising a multiplier, an ALU, and a memory storing coefficients for signal calculation, and a left and right two channel audio signal. A pair of digital processing circuits for respectively processing the first and second digital data input corresponding to the first and second digital data;
A unique program memory that does not include an ALU and stores a unique program for controlling the pair of digital processing circuits, and a unique instruction decoder that decodes an instruction constituting the program and outputs a control signal A single control circuit that controls the pair of digital processing circuits by the control signal, and outputs the same control signal output based on the same instruction in the program to the pair of digital processing circuits. A digital signal processing device, wherein the pair of digital processing circuits simultaneously operate the input first and second digital data in accordance with the same control signal. 2. A data input / output circuit that is commonly connected to the pair of data buses and performs data input / output between each data bus and an external terminal;
2. The digital signal processing device according to claim 1, further comprising an interface circuit that inputs and outputs data between each data bus and an external device. 3. The said pair of digital processing circuits, the pair of data buses, the control circuit, the data input / output circuit, and the interface circuit are formed on a single semiconductor chip. 3. The digital processing device according to claim 2, wherein