JPS62123820A - Digital graphic equalizer - Google Patents

Abstract

PURPOSE:To reduce ripples at a flat band, to improve the S/N and to keep the sound volume constant at the time of adjustment by using an FIR digital band pass filter being virtual at each plural bands and a multiplier provided to the output. CONSTITUTION:A controller 9 and a digital signal processor (DSP) 4 change a filter coefficient corresponding to the designation from a characteristic input section 15 among plural coefficients of the FIR digital bandpass filter assumed at plural bands according to the designation. Then the plural coefficients are added to obtain the total sum at each plural coefficients, the gain coefficient is obtained from the total sum and a digital word length and the gain of the multiplier 25 provided to the output of the FIR digital filter is changed based on the gain coefficient obtained in such a way.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital graphic equalizer;
The present invention relates to a graphic equalizer that outputs a digital audio signal such as a PCM audio signal by varying the level for each frequency band.

Conventional technology Digital filters used in conventional digital graphic equalizers are generally designed with a focus on the cutoff frequency (center frequency), and are not designed with a focus on plateau characteristics in frequency characteristics. There wasn't.

Problems to be Solved by the Invention For the above reasons, in the conventional FIR digital filter, the band emphasis characteristic Kb (boost ILH
, ') and band attenuation characteristics, if (cut amount and In other words, there was a problem in that the tone changed unnaturally.

On the other hand, in order to reduce the ripple in the flat region of frequency 111 or more of the low-frequency emphasis characteristic and the ripple in the flat region of frequency f or less of the low-frequency attenuation characteristic, for example,
A technique using an IIR digital filter described in Publication No. 315 is known, but since it is an IIR digital filter, the phase is non-linear, and the high-frequency SN ratio deteriorates due to rounding errors. There was a problem that it was easy to oscillate.

Furthermore, conventional digital filters have the problem that it is difficult to obtain desired band emphasis and attenuation characteristics.

Furthermore, when conventional equalizers have variable equalizer characteristics, overflows and underflows occur during the filter multiplication process, especially in digital ones, and as a result, the input and output volume cannot be maintained constant, resulting in a loss of natural hearing. There was a problem that it was not possible to obtain the This was also the case with analog equalizers.

The present invention has less ripple in a flat area, and therefore can obtain a natural tone.Furthermore, the S/N ratio is good, and H
Provides a digital graphic equalizer that is suitable for iFi, can obtain desired band emphasis and attenuation characteristics with a small amount of coefficient data, and can maintain input and output volume constant when the equalizer characteristics are varied. The purpose is to

Means for Solving the Problems In FIG.
Signal processor) 4 includes means for changing filter coefficients according to specifications from the characteristic input section 15 and adding coefficients for each band to obtain a gain coefficient, means for changing frequency characteristics with new coefficients, and a multiplier. 25 is each embodiment of a means for varying the gain with a gain coefficient.

Function A plurality of coefficients for each of the virtual FIR digital bandpass filters 191 to 19o (FIG. 4) for each of a plurality of bands (out of 1 to l, the coefficients of the filter in the corresponding band corresponding to the specification from the characteristic input section 15 are specified. Accordingly, change it by multiple coefficients (1
~Il), a plurality of bands = 1~2)) is calculated, a gain coefficient is obtained from M and the digital word length, and a gain coefficient is set at the output of the FIR digital filter 50 based on the obtained gain coefficient. The gain of the multiplier 25 is changed.

Embodiment FIG. 1 shows a block diagram of an embodiment of the equalizer of the present invention. In the figure, 15 is a characteristic input section, 16 is a display section,
As shown in FIG. 2, characteristic variable switches sw, sw2.
...5Wo1 display element group 16, 162. ...16o
A 1λ display element and a 16λ display element are provided. Reference numeral 4 denotes a DSP which performs digital filter calculations in order to realize 1 to Ko on the n-band equalizer characteristics shown in FIG. has.

FIG. 13 shows a concrete block system diagram of the DSP4. In the figure, a multiplexer (MUX), a program counter (PC), a stack, a data memory page pointer (DP), and an auxiliary register.

Since the auxiliary register pointer (ARP), shift circuit, etc. are not directly related to the present invention, their explanation will be omitted. The DSP includes a multiplier 51 as hardware, and its calculation speed reaches about 10 to 100 times that of the CPU. In general, calculations using an FIR digital filter have about 20 to 100 steps, and must be performed at a sampling period (1/44.1 kHz 1 = 23E), which enables high-speed calculations and SP, for example, as shown in Figure 5. It can be effectively used as a fixed tap FIR digital filter having the configuration shown in FIG.

In FIG. 13, a program ROM 41 stores programs to be executed by the DSP and multiplication coefficient data in advance, and transmits these data via a program bus 52 to a controller 53 or the like, and via a program bus 52 and an internal data bus 54. The signal is supplied to the multiplier 51 and the like. Further, a clock signal (CLKIN) is supplied to the controller 53 from an external oscillator (not shown).

The data on the input/output data bus 55 is 16 bits (-L) (digital word length) as shown in FIG. 14 (A>).
As shown in the same figure (B), after combining the MSB, this is shifted to the LSB side by 4 bits, and the internal data bus 5 is shifted as a whole.
It is calculated using 24 bits, which is the number of bits of 4. As described later, if no overflow or underflow occurs, the 4 bits on the MSB side are assumed to be 0000 or 1111, depending on the sign of the data, and in order to match the MSBs, the data is shifted by 4 bits to the MSB side, and is converted to 16 bits. Output. The operation result of the multiplier 51 is the logic operation circuit (AL
U) 56 and an accumulator (ACC) 57, and is supplied to the internal data bus 54.

A digital audio signal supplied to an input terminal 1 via an optical fiber (not shown) is converted into an electrical signal by an optical interface 2, converted into a serial/parallel signal, and supplied to a latch circuit 3 where it is latched. . The output of the latch circuit 3 has its equalizer characteristics varied by the DSP 4, which will be described later, according to the specifications of the characteristic input section 15, is supplied to the latch circuit 5, is parallel-to-serial converted by the optical interface 6, is converted into an optical signal, and is sent to a terminal. 17 and supplied to the optical fiber.

As shown in FIG. 4, the DSP 4 is substantially configured to obtain desired equalizer characteristics from 1 to 1 by varying the coefficients of the n-band digital bandpass filters 191 to 19o by rewriting the coefficient memory 42. As a digital bandpass filter, for example, those shown in FIGS. 6(A) and 6(B) can be considered.

FIGS. 6(A) and 6(B) respectively show the hardware configuration (circuit diagram) of the digital bandpass filter and its schematic block system diagram. In FIG. 6(A), the 1-sample delay section 3
01 to 30□, multiplication sections 311 to 31fl, addition section 322
Low-pass filter (low-pass filter) 22.1 sample delay unit 35 to obtain the characteristics of the solid line in FIG. 7(A) at ~32□
1-35 fl.

The multipliers 361 to 36□ and the adders 372 to 37□ each constitute a high-pass filter (high-pass filter) 24 that obtains the characteristics shown by the solid line in FIG. ~341, Multiplication section (level adjustment section) 33.3
8 constitutes a whole range filter (substantially a delay circuit and an attenuator) 23.

Coefficients a1~ of the multipliers 311~31° of the low-pass filter 22
a2 is a function window shown in FIG.
is a functional window similar to that shown in FIG. 3B, and the output of the whole range filter 23 is added to the adders 32, 37, . is supplied to

In this case, as shown in FIG. 7(A), the low-pass filter (actual number 8) and the whole range filter (dotted chain line) are combined to obtain the characteristic shown by the broken line, and as shown in FIG. A band filter (solid line) and a band filter (dotted chain line) are combined to obtain the characteristic shown by the broken line, and these are combined to obtain the band attenuation characteristic K shown in FIG.

get.

On the other hand, when obtaining band emphasis characteristics, the coefficients a1 to a of the multipliers 311 to 31fl of the low-pass filter 22 are variably set to obtain the characteristics shown in FIG. 7(E), while the high-pass filter 24 multipliers 361 to 36fl coefficients b1 to
The configuration is such that b2 is set variably to obtain the characteristics shown in FIG. As in the case of obtaining the above-mentioned band attenuation characteristic, in this case, as shown in FIG. 7(D), a high-pass filter (solid line)
and the whole range filter (dotted chain line) to obtain the characteristic shown by the broken line, and as shown in the same figure (E), the low pass filter (solid line) and the whole range filter (dotted chain line) are combined to obtain the characteristic shown by the broken line. These are synthesized to obtain the band emphasis characteristic Kb shown in FIG.

As described above, in the present invention, since the flat characteristic above the frequency f□ and the flat characteristic below the frequency f are each involved in a whole range filter, there are fewer ripples in the flat region than in the conventional one.

Fig. 8 is a simplified version of the bandpass filter shown in Fig. 6 (A>).
The coefficient aH (81 to a Il) of the high-pass filter 24 and the coefficient S, (b1 to bIl) of the high-pass filter 24 are added to the adder 40 (401 to
The coefficient hIi (h11~h1□) (
11) is set as the coefficient of the multiplier 31 (31-31°), and is substantially equivalent to the circuit diagram shown in FIG. 6(A).

The bandpass filters shown in FIG. 6(A) and FIG. 8 are respectively applied to the bandpass filters 191 to 19o shown in FIG. 4, but the bandpass filter shown in FIG. 5 is the bandpass filter 191 shown in FIG. .about.19 DEG and equivalent to the entire adder 21 (indicated at 50), the present invention can use the bandpass filter shown in FIG. 5 as a more preferred embodiment. In the case shown in Fig. 5, h −h shown in Fig. 8 is the coefficient of the first band, h21 to h2□ is the coefficient of the second band, and h31 to
h32 is the coefficient of the third band, . . . , ho1 to ho2 are the calculators 31, 312, . . . 31°, a result equivalent to calculating the individual bandpass filters 191 to 19o shown in FIG. 4 can be obtained with one bandpass filter.

Next, switching of equalizer characteristics will be explained. When switching the equalizer characteristics, the coefficient data corresponding to the coefficients of the digital filter that substantially constitutes the DSP 4 is switched, and this switching operation is controlled by the CPU 10 in the control device 9.
1. It is configured to operate according to the flowchart shown in FIG. 9 based on control signals from the RAM 12.

Switch position control data is input by operating the switch of a predetermined band in the characteristic input section 15 (see FIG. 9).
A) In step 101), a predetermined segment of the display element/group corresponding to this band is displayed (step 102).
, filter coefficients corresponding to the specified equalizer characteristics (
For example, for the third band, h , h , ・h3e)
is retrieved from the ROM 11 (step 103). R.O.
When the filter coefficients are retrieved from M11, the gain coefficient adjustment section 101 (Fig. 1) calculates the sum of the filter coefficients M
(step 104), and then, assuming that the digital word length is L, a coefficient (gain coefficient) of (2L-1)/M=λ is determined, and the filter coefficient memory 422 constituting the coefficient memory 42 ,422L...

42n and the filter coefficient memories 421, 422.42n and the gain coefficient memories 4g. ..., the filter coefficient is stored in 42o, the gain coefficient is stored in the memory 4, and the gain of the multiplier 25 shown in FIG. 4 is adjusted by the control signal from the memory 4g (step 105). At the stage before adjustment, for example, a 2-bit overflow as shown in FIG. 14(C) or a 2-bit overflow as shown in FIG.
For example, a 2-bit underdub O- is generated as shown in FIG. Same 1il from 50! As shown in I(E), 16-bit output data without overflow and underdub O- is extracted.

Since the gain coefficient is changed in this way, the multiplication units 311 to 31□ (Fig. 5), which play a central role in the system, are set to have a length that is, for example, 4 bits better than the word length, and the coefficient word length is also set to a value that is better than the word length by 4 bits. For example, the calculation output is 24 bits longer than the word length by 8 bits (the 14th bit).
It is preferable to use the one shown in Figure (B)).

Since the gain is adjusted in this manner, the input and output volumes can be held constant, and deterioration of the SN ratio due to overflow or level drop can be prevented.

Next, the coefficient λ is displayed on the λ display element group 16λ (step 106), and the filter coefficients are sequentially sent from the RAM 12 to the latch circuit 8 at interrupt timing (FIG. 9(B)).
middle step 111). At the same time, address data is supplied to the address memory 7, and an address corresponding to each latch data is specified (step 112). At this time,
CPLJlo counts up sequentially from 1 to 2 (steps 113 to 115), and outputs the coefficient λ (step 1).
16). The coefficient λ is the latch circuit 13, the optical interface 1
4 from the terminal 18 and supplied to a tone control volume or the like to return the volume to the value before gain adjustment.

The DSP4 executes the flowchart shown in FIGS. 12(A) and 12(B).
After being initialized (step 121 in FIG. 12(A)), the previously performed calculation result is output at the interrupt timing (step 131), and the latch circuit 8 The next sampling data is input (step 132) and written into the coefficient memory 42 at the address specified in the address memory 7 (step 133). When the filter coefficients are written to all addresses (step 134), the memory sections 421, 422 . ..., 42o is switched to the memory section of the inactive page of the two memory sections (step 135 in FIG. 12), and thereby new coefficients h, h, . . . , h2 are set. A filter operation is performed every sampling (step 136), and a new equalizer characteristic is obtained.

In addition, when the bandpass filters 191 to 19o are configured to be controlled by one thread path, by switching the switch S by the operation of the CPU 10, the inactive one of the two memory sections (for example, 42 and 422) is It is also possible to switch to the page memory section.

In this case, the equalizer characteristic is varied in the characteristic adjusting section 15.

In the above embodiment, the multiplier 25 was described as being provided separately, but the multiplier 51 within the DSP 4 may also be used.

Effects of the Invention According to the digital graphic equalizer of the present invention, in particular, since the flat characteristic substantially involves a whole range filter, it is possible to reduce ripples in the flat region compared to conventional ones. It is possible to obtain a more natural tone than that using the FIR digital filter, and furthermore,
Because it uses an FIR digital filter, the SN in the high frequency range is particularly low compared to that using an IIR digital filter.
There is no deterioration of the ratio, and there are no problems such as oscillation. Also, since the gain coefficient λ is obtained from the sum of filter coefficients and the digital word length and the gain of the multiplier is varied, overflow and underflow are avoided. Since this does not occur, the input/output volume can be kept constant, and deterioration of the SN ratio due to overflow or level drop can be prevented.Also, by outputting the gain coefficient λ, the volume can be adjusted in conjunction with the volume control volume. It is also possible to return to the value before gain adjustment, and by displaying the gain coefficient λ, it is easy to set the desired characteristic by operating the characteristic variable switch in the characteristic input section. Since it can be converted into a set of systems, various characteristics can be combined with a small amount of coefficient data, and this allows a large degree of freedom in characteristics. It has the advantage of being simple in configuration and can be constructed compactly and at low cost using, for example, a high-speed processor such as a DSP.

[Brief explanation of drawings]

11 and 2 are block diagrams and partial schematic diagrams of embodiments of the equalizer of the present invention, and FIGS. 3 and 4, respectively.
The figures are an equalizer characteristic diagram and a block system diagram of a bandpass filter that obtains equalization characteristics, Figure 5 is a circuit diagram of an FIR digital filter used in the equalizer of the present invention, Figure 6 is a circuit diagram of an FIR digital bandpass filter, and Figure 7 is a block diagram of a bandpass filter that obtains equalization characteristics.・The figure is a frequency characteristic diagram of the filter, Figure 8 is a circuit diagram of the FIR digital bandpass filter, Figure 9 is a flowchart for explaining the operation of the CPU, Figures 10 and 11 are diagrams showing the coefficient values of the filter, and Figure 8 is a circuit diagram of the FIR digital bandpass filter. 12 and 13 are a flowchart and block system diagram for explaining the operation of the DSP, respectively, and FIG. 14 is a diagram for explaining the bit length of data. 1...Digital audio signal input terminal, 4...
DSP, 42... Coefficient memory, 421, 422...
Filter coefficient memo 1c4. ...Gain coefficient memo 1
Huff: Address memory, 8: Latch circuit, 9.
...Control device, 10...CPU, 101...Gain adjustment section, 11...Program ROM, 12...CP
RAM for U work. 15... Characteristic input section, 16... Display section, 17...
Audio signal output terminal, 18...Coefficient output terminal, 1
9... Bandpass filter, 21... Adder, 25...
Multiplier, 301-30□...1 sampling delay unit,
311-31...multiplication section, 322-32□, 411
~41... Addition unit, 50... FIR digital filter. Patent Applicant: Victor Japan Co., Ltd. Figure 6 Figure 8 Figure 9 (A) (B) Figure 10 Figure 1 Figure 12 (A) (B) Figure 13 Figure 14

Claims (3)

[Claims] (1) A characteristic input section that specifies desired equalizer characteristics for each of a plurality of bands, and a virtual FIR for each of the plurality of bands.
Among the plurality of coefficients of each digital band filter, the coefficients of the filter of the corresponding band corresponding to the specification from the characteristic input section are changed according to the specification, and the coefficients of the plurality of bands are added for each of the plurality of coefficients. a coefficient changing means for calculating the sum and obtaining a gain coefficient from the sum and the digital word length; and an F whose frequency characteristics are changed based on the coefficient obtained by the coefficient changing means.
A digital graphic equalizer comprising an IR digital filter and a multiplier provided at the output of the FIR digital filter and whose gain is varied by the gain coefficient. (2) The coefficient changing means is characterized by being provided with means for outputting a gain coefficient such that (2^L-1)/M=λ, where the sum is M and the digital word length is L. A digital graphic equalizer according to claim 1. (3) The coefficient changing means is characterized by being provided with means for displaying a gain coefficient of (2^L-1)/M=λ, where M is the summation and L is the digital word length. A digital graphic equalizer according to claim 1.