JPH01259610A - Sound volume adjusting device - Google Patents

Abstract

PURPOSE:To easily change the sound volume of the audio signals of plural channels by processing in a time-sharing way a series of sequence processing steps determined beforehand and accumulating gain quantity data to the audio signals of the plural channels in a gain data memory part. CONSTITUTION:By processing in the time-sharing way the series of sequence processing steps determined beforehand, the gain quantity data to audio signals SANIN1-SANIN4, SDIGIN1-SDIGIN4, SANOUT1-SANOUT4 and SDIGOUT1-SDIGOUT4 of the plural channels are prepared and accumulated in a gain data memory part 41, when a gain quantity reading request (D5, SMPY) is generated from a multiplying means, the processing of the sequence processing steps (SP1N)N1-12-(SP5 N)N1-12 are discontinued and gain quantity data (DATA)M of the channel corresponding to the gain quantity reading request (D5, SMPY) are sent to the multiplying means. Thus, the sound volume of the audio signals of the plural channels can be surely adjusting with a simple structure.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A: Industrial field of application B: Outline of the invention C: Prior art (Figs. 9 to 11) D: Problems to be solved by the invention (Figs. 9 to 11) E: Means for solving the problems (Fig. 1 to Fig. 3) F action (Fig. 1 to Fig. 3) G embodiment (G1) First embodiment (Fig. 1 to Fig. 7) (G2) Other embodiments (Fig. 8 Figure) Effects of the Invention A Field of Industrial Application The present invention relates to a volume adjustment device, and is particularly applicable to a digital volume adjustment circuit.

B. Summary of the Invention The present invention is such that, in a volume adjustment device, when an interrupt command is generated from a multiplication circuit while sequentially processing gain book calculation processing, a process for reading gain amount data to the multiplication circuit is executed. As a result, the volumes of audio signals of multiple channels can be reliably adjusted with a simple configuration.

C. Conventional Technology Digital volume adjustment circuit l generally multiplies audio input data DIN by gain amount data D G A I N in a multiplier circuit 2 to obtain audio output data D, as shown in FIG. U, and the sound 1tHjl signal signal S, which is output when the sound ffi 11 adjuster 3 is manually adjusted, for example. Gain amount data DGAIN having a value corresponding to 8a is generated in the gain controller 4.

Conventionally, as the gain controller 4, as shown in FIG. 10, one having an up/down counter configuration is used.

That is, the gain controller 4 has an up/down counter 11, and final value setting data DFlH or initial value setting data DINA is supplied as preset data DATA to its preset input terminal PR, and the load terminal LD
When the load signal LOAD is applied to the load signal LOAD, the preset data DATA is read, and the volume adjustment signal S is then applied to the up/down command input terminal U/D. 8. Depending on the contents of , an up-count operation or a down-count operation is performed in synchronization with a clock signal CLOCK applied to a clock input terminal CK.

The count contents of the up/down counter 11 are sent from the gain controller 4 to the multiplication circuit 2 (FIG. 9) as gain amount data DGAIN.

In the configuration of FIG. 10, when the sound ff1fill adjustment signal S CQII whose content is to increase (or decrease) the volume is given from the volume adjuster 3 (FIG. 9), the up/down counter 11 changes the count content. Closing price setting data DFIN (or initial value setting data DIN?
) is counted up (or down counted) from the value of the preset data DATA.

Here, the sound fim adjustment signal 5 cos a is given to the switching circuit 12 as a switching control signal, and the volume adjustment signal y4 cos a is given to the switching circuit 12 as a switching control signal.
When aNt specifies up counting (or down counting), the final value setting data DFIN (or initial value setting data DIN?) given to the input terminal al (or G2) is transferred from the output terminal cl to the up/down counter 11.
It is sent as preset data DATA. At the same time, the switching circuit 12 supplies the initial value setting data Du, 4t (or final value setting data DFIN) given to the switching input terminal a2 (or G3) to the reference value data input terminal B of the comparator 13.

The comparator 13 converts the data supplied to the reference value data input terminal B into gain amount data D supplied to the comparison value data input terminal A. Up-count operation (or down-count operation) of up-down counter 11 compared to AIM
determine the end point.

That is, the comparator 13 receives the volume adjustment signal S. 1 is received and up-counting (or down-counting) is specified, and when comparison value data A becomes larger (or smaller) than closing price setting data D FIN supplied to reference value data input terminal B. Comparison value detection signal 5cou
+ (or S, .,) to all switching input terminals of the switching circuit 14
(or G12), is applied as a load signal LOAD to the load input terminal LO of the up/down counter 11 through the switching output terminal cll and further through the inverter 15.

In this way, the comparator 13 determines that when up-down count 1~ (or down count) is specified, the count contents of the up-down counter 11 are changed to the final value setting data DF+, 4 (
Or, when it exceeds the first 'M (lffff setting dark 01N?), load the up/down counter 11 to preset the initial value setting data DINA (or final value setting data DF1-) and continue the subsequent counting operation. It is made possible to do so.

In this way, according to the configuration shown in FIG. 10, when the operator is trying to increase (or decrease) the volume using the volume adjuster 3, the up/down counter 11 counts one step at a time with the cycle of the clock signal CLOCK. Since the stepwise operation is performed to increase (or decrease) the content, the gain amount data DGAIN eventually becomes as shown in FIG.
Volume adjustment signal S. During the interval Tt+P in which NY commands an increase in volume, the initial stage (l!!D1NT to inclined part G1
Contrary to this, during the section T9゜□ in which the volume is commanded to decrease, the final value D□8 passes through the slope G2 and changes to the initial value DIN□. It is possible.

D Problems to be Solved by the Invention However, according to the gain controller 4 shown in FIG. 10, firstly, the number of channels that can be controlled is limited to one channel, so the audio input data D is not correct (see FIG. 9).
Since it is necessary to separately prepare gain controllers 4 having the configuration shown in FIG. 10 corresponding to the number of channels, the greater the number of channels, the more
There is an unavoidable problem that the overall configuration of the system becomes large.

Second, the slopes of the slope portions G1 and G2 of the gain amount data DGAIN (FIG. 11) that can be obtained by the gain controller 4 of FIG.
The audio output data D is uniquely determined by the repetition period of CK. There is a problem in that it is not possible to change LIT at an arbitrary rate of change as needed.

Incidentally, (in order to change the slopes of the oblique portions G1 and G2 as necessary, it would be possible to change the repetition period of the clock signal CLOCK as necessary; however, in practice, the repetition period of the clock signal CLOCK The repetition period is equal to the sampling frequency FS of the audio signal (for example, 48 (
kllz) ), and its repetition period cannot be changed arbitrarily.

The present invention has been made in consideration of the above points, and when changing and controlling the volume of audio signals of multiple channels,
It is possible to avoid complicating the overall configuration, and
The present invention attempts to propose a volume adjustment circuit that allows the rate of change of gain amount data to be easily changed as necessary.

EMeans for solving the problem In order to solve the problem, in the first invention, a plurality of channels of audio signals 5ANINI~sAN
+sa, 5DIGINI ~ 5OIGIN4,
S ANOUT, ~S ANOUT4% So+c
out+~S A series of predetermined sequence processing steps (S P I N) for gain amount data DGA, 4 for DIGOUT4 N-1~, 2~ (SP5
N) Created by time-divisionally processing N-1 to +2, stored in the gain data memory section 41, and multiplied by the multiplication means 25.
When a gain amount read request (Ds, 514PY) is generated from the sequence processing step (SPIN) Ha
l-12~(S P5 N) Interrupt the processing of N-1~ and 2 and send the gain amount data (DATA) M of the channel corresponding to the gain amount read request (Ds, 5spv) to the multiplication means 25. A gain control means 26 is provided.

Further, in the second invention, in addition to the invention of it, a gain amount readout request (Ds, 5
read processing (SPM) M-1 to M-3 corresponding to spv)
．． Sequence processing steps (S P
I N) N-1~1! ~(S P 5 N) +1+
Make it interrupt l to l□.

Further, in the third invention, in addition to the first invention, a series of sequence processing steps (SPIN) N, 1 to I□
~(S P 5 N) Volume change processing step (SP4N) N1. to N-1-1□. ~1: including a volume change request (D,, SCP) from the volume data input means (29, 30)
When υ) occurs, the relevant volume change data (DATA)
r in a series of sequence processing steps (S P I N)
N-1-+t~(S P 5 N) It is written into the gain data memory section 41 as data used for the processing of N-1~ and 2.

F action In the first invention, a plurality of channels of audio signals S ANINI "" S A NIN4, S I
IIGINI~S DIGIN4% S ANo
ut+~S ANOut4s S DIGOLI
Gain amount data for TI~5DIGOLIT4 (D
ATA) □ is created by a series of predetermined sequence processing steps (S P I N) N-1 to 1□ to (S
P 5 N) H-r~,! By processing in a time-sharing manner, even if the number of channels to be processed increases, the change rate can be specified arbitrarily for each channel without making the overall volume adjustment device configuration complicated and large-scale. It is possible to realize a volume adjustment device that can adjust the volume.

Therefore, the gain amount data (DA
A series of sequence processing steps (SPIN) 881 to 1□ to (S P
5N) By interrupting N-1 to 1□, the volume of all channels can be reliably adjusted as necessary.

Further, in the second invention, a gain 1lfl output request (D
3. By interrupting the read processing corresponding to S□V) in the order of highest priority, the gain amount data (D
ATA), 1 creation process and gain amount data (DAT
A) It is possible to perform the readout process of H to the multiplication means 25 at asynchronous timing, and thus, in order to time manage the creation process and readout process of gain amount data (DATA) 4, a large-scale means is required. You can make it unnecessary.

Further, in the third invention, volume change data (DATA
) P write processing is performed as a series of sequence processing steps (S P I N) N-1 ~, ~ (S P 5 N)
By including it in N, ...1□, it is possible to reliably change the data as needed without having to manage the time between the input means (29, 30) of the volume change data (DATA) P and the gain control means 26. Volume change data (DATA) r can be written into the gain data memory section 41.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) First embodiment In FIG. 1, 21 represents the digital sound MUf as a whole.
A 4-channel adjustment circuit is shown, which takes in 4 channels of analog audio input signals S□IN1 to 8□184 to the bus 23 via the analog-to-digital conversion circuit 22.
Digital audio input signal SDI for channels
GIN+"" 31110184 is taken into the bus 23, and four channels worth of digital audio output signals S DIO8LIT+S DIG. u
rn to the outside from the bus 23, and 4 channels of analog audio output signals S ANOU□ to S
ANOLIT4 is sent out from the bus 23 via the digital-to-analog conversion circuit 28.

In this embodiment, the bus 23 is connected to the main controller 24.
In addition, the data sampling frequency FS (=48
(kHz)), the audio signals of the 1st to 16th channels are sequentially processed in a time-division manner in synchronization with the system clock CL srH of 129
At the timing Lsts, the main control signal SMAIN is applied to the multiplication circuit 25, gain controller 26, and auxiliary memory 27 for sequentially processing the data of 12 channels according to a predetermined sequence.

In this embodiment, the gain controller 26 is connected to the bus 23.
8 channels of input audio signals are sequentially input in a time-sharing manner to the
Gain amount data (DATA) M representing the multiplicand to be multiplied with respect to the audio signal for each channel is processed in the first to fifth sequence processing steps (S) for each channel.
PIN) N, ~1□~(S P 5 N) N-1-
It is created by periodically calculating according to 1□ (Figure 6).

Incidentally, the digital volume adjustment circuit 21 inputs the input audio signals, that is, the analog audio input signal S ANINI "' S ANI84 for 4 channels and the digital audio input signal S 111 for 4 channels.
For each of GINI to 5llICIN4, the input audio signal of each channel can be adjusted to the reference level as necessary, since the input signal level changes due to the influence of the cable length of the input transmission system. Perform adjustments to fit within the dynamic range of

In contrast, the analog audio output signal S ANOU
T, ~S ANOtlT4 and digital audio output signal SIIIGOLITI”SolGoUt
Regarding a, gain control for four channels is performed based on the fact that there is no difference in the effect of the length of the output transmission system between sending out an analog audio signal and sending out a digital audio signal.

The 12 channels of audio signals to be subjected to sound adjustment are referred to as audio signals of the first to twelfth channels.

On the other hand, when the audio data of the first to eighth channels are time-divisionally input to the bus 23 from the outside, the multiplier circuit 25 takes in the audio data in response to this, and also inputs the audio data to the gain controller 26. generates an interrupt command and outputs the gain amount data (DATA) of the corresponding channel.
) After reading M from the gain controller 26 and performing multiplication processing, it is stored in the corresponding channel of the auxiliary memory 27 via the bus 23.

Also, the gain controller 26 controls when the audio data stored in the auxiliary memory 27 is read out to the bus 23.
This is taken in as the audio data of the 9th to 12th channels, and an interrupt command is generated to the gain controller 26 to obtain the gain amount data (
DATA).

is read from the gain controller 26, subjected to multiplication processing, and then sent to the outside via the bus 23.

In this way, the digital sound N adjustment circuit 21 adjusts the audio input signals for 8 channels and the audio output signals for 4 channels to the first level as shown in FIG.
, second, . . . , the gain processing of the corresponding channels is executed during the gain processing periods TI, T2, . . . , T12 of the twelfth channel.

As shown in FIG. 4, the gain controller 26 stores channel data C representing the processing channel for each control channel N (=1 to 12) that controls the gain.
HN O and the initial value data (I
NIT)N and the direction of gain change (increasing direction when positive;
When the step data (STEP) s representing the rate of change and the closing price data (FINAL) N are input through the setting panel 30, the CPU 29
By supplying the control signal S CPLI to the gain controller 26, data can be written to the memory area assigned to the corresponding channel in the gain data memory section 41 (FIG. 2) of the gain controller 26.

Here, when a positive value is selected as the step data 5TEP, as shown in FIG. 5(A), the initial value data INIT, which is a low value, changes to the final price data FINAL, which is a high value, at a rate of change of l 5TEP l. This means that the gain amount data DGA1N is specified, and if a negative value is set as the step data 5TEP, a high value initial value data INIT is set as shown in FIG. 5(B). to the closing price data FINAL of the lower value from l 5T
Gain amount data D that changes at a rate of change of EP1.

This means that AID has been specified.

The data stored in the gain data memory section 41 is controlled by state control signals SAI and I generated in the state control section 43.
are processed in the first processing mode according to the sequence shown in FIG. Ru.

That is, when in the first processing mode, the state control unit 43 controls the first system clock CLSTM in the gain processing period T1 of the first channel (that is, N=1), as shown in FIG. (FIG. 3(B)), the first Siegen processing step 7" (S P I N)
N1. , the initial value data (INIT) I of the first channel is read out from the gain data memory section 41 to the calculation section 42, and then the second sequence processing step (S P 2 N) By executing N, 1, the step data (STEP) is stored in the gain data memory section 4.
The sequence processing step (
By executing SP3N)N and I, the final value data (FINAL) is read out from the gain data memory section 41 into the calculation section 42.

In this way, the calculation unit 42 has all the data necessary to calculate the gain amount.

Subsequently, the state control unit 43 outputs the fourth system clock CL.
The address data D3 sent from the CPU interface 46 at the timing of STH is selected by the address selector 44 and inputted to the gain data memory section 41 as address data Di, and thus the data of the P channel latched by the CPU interface 46 is input. Initial value data (INIT), step data (ST
EP) 2, the final price data (FINAL) P is written as the write data (DATA) P in the gain data memory section 41.
Write to the channel's memory area.

Subsequently, the state control unit 43 controls the fifth system clock CL.
The fifth sequence processing step (S P
5N) H-+, the gain amount data (DGAIN) + is transferred from the calculation unit 42 to the initial value data (DGAIN) of the first channel of the gain data memory unit 41.
INIT), to write to the corresponding memory area.

Here, the state control unit 43 controls the CPU interface 46
While writing the write data (DATA) F to the gain data memory unit 41, the calculation unit 42 uses the gain amount data (DGAIN) 1 as shown in the following formula (%) (1) (timing of the first channel). Then N-1),
The sum value of the first M 4iM data (INrT) + and step data (STEP) is initial value data (INIT),
is obtained and written into the initial value data memory area of the first channel of the gain data memory section 41.

By doing this, step data (STEP
) , is (STEP)N > 0...
・When the value is positive as in (2), the initial value data (I
The initial value data (INIT) representing N is the step data until it becomes larger than the final value data (F I N A L) N. (S
TEP) increases at the rate of change of H. Eventually, when (3) 2 is satisfied, assuming that the closing price data (FINAL)s has been reached, from then on (INIT) N = (FINA
L) s......as in (4), convert the initial value data (INIT) N to the final price data (FINAL)
Performs an operation that makes it equal to ++.

On the contrary, when step data (STEP)N is negative (direct) as in the following formula % formula % (5), (INIT)N < (FINAL)N ・
....Until the condition (6) is met, the initial value data (INIT) N representing the gain amount data (DGAIM) H is
decreases at the rate of change of step data (STEP) H.

Eventually, when a state is reached that satisfies equation (6), from then on (INI
T)N = (FINAL)N...
- Execute an operation to maintain the final price data (FINAL) as in (7).

In this way, when the state control unit 43 completes the gain amount calculation processing for the first channel (that is, N=1 channel), the state control unit 43 similarly performs the gain calculation processing for the second, third, and so on.
12th channel (i.e. N = 2.3...
・12 channels), the sequence processing step (S P I N) s-t~, 2, (SP2
N) N-2~l□・・・・・・(S P 5 N) N
The processes from −z to 1□ are executed as the first processing mode.

In this embodiment, the CPU interface 46 receives address data D4 and a write/continue control signal S. 2. is given from the CPU 29, the system clock CL
1 (MHz
) data from CPU29 (DATA)
p x and thus the latched data to the system clock CL st
, the gain data memory section 4 writes the write data (DATA) P of P channels (P-1 to P-12) at
I'll write it in 1).

In addition to the first processing mode described above, the state control unit 43 also allows the multiplication circuit interface 51 to output the interrupt command signal S CO
When M is generated, the first processing mode switches to the second processing mode and the data (DATA) is preferentially processed.
s is sent to the multiplication circuit interface 51.

That is, the multiplication circuit interface 51 is connected to the multiplication circuit 2.
5 to address data D and write/continue control signal S at a timing asynchronous with the system clock CLstq.
When receiving the HPV, an interrupt command signal S is sent to the state control unit 43. . and address data D based on address data D5.

is sent to the address selector 45.

At this time, the internal address generator 44 responds to the state control signal SADD of the state controller 43 and outputs the system clock CI.
, sTs, the address selector 45 selects the address data D, and sends it out as the address data D2 to the gain data memory section 41.

At this time, the gain data memory section 41 reads out the gain amount data (MPY) M of the first channel and uses it as read data (DATA) s to the multiplication circuit interface 51.
The data is sent to the multiplication circuit 25 via the bus 23 as gain amount data (1) ATA)□.

State side in this way? The if1 section 43 receives an interrupt command signal S from the multiplication circuit interface 51 while executing the processing operation in the first processing mode described above with reference to FIG. , occurs, in response to this, as shown in FIG. 7, the execution of the sequence processing step following the currently processed sequence processing step is made to wait, and the interrupt processing steps (SPM) M-1 to M-1 are executed. By executing 1□, the gain amount data (MPY) M is read out and the data (
DATA), 4 is read out from the gain data memory section 41 to the multiplication circuit interface 51.

This interrupt processing step (SPM), 4-+-1
When the process ends, the state control unit 43 starts execution of the next sequence processing step that has been kept waiting.

In the above configuration, the gain controller 26 receives the interrupt command signal S from the multiplication circuit 25. Unless ON (Fig. 2) arrives, the gain processing period T'l in Fig. 3(C)
, T2..., the first (N=1)
Channel, 2nd (N=2) channel...
The sequence processing steps (S P I N) N-1 to (S P5 N) described above with respect to FIG.
N-1, (S P I N), 4-z~(s p 5
N) N+! A first processing mode in which . . . is repeated is executed in synchronization with the system clock CL3-H.

Here, the fourth sequence processing step (SP 4
N) N-1 to I□ as input data from the CPU 29 (C
By assigning it as the writing period of PtJ)F,
For example, as shown in FIG. 3(A), when a write command signal s cpu arrives from the CPU 9, data (cpu
) F to the fourth sequence processing step (S P 4
N), l-I to 1□ can be used to write to the gain data memory section 41.

Therefore, even if the data latch for the CPU interface 45 is not synchronized with the system clock CL 5T14, the CPU
Data (DAT) representing data (CPU) p from U29
A) When PX is latched, this data (CPU) P is sent to the sequence processing step (S P 4 N
) At H-+-1t, it can be written to the gain data memory section 41 as write data (DATA) p from the CPU interface 46 in synchronization with the system clock CLs.

For example, as shown in FIG. 3A, the write/continuous output control signal sctu is generated in the CPU interface 46 at time points t and t2 during the gain processing period TI of the first (N=1) channel. Data (DATA) □ is C
When latched by the PU interface 46, the write data (DATA) P based on this data is used in the sequence processing step (DATA) included in the next gain processing period, that is, the gain processing period T2 of the second (N=2) channel.
SP4N) N-2 (FIG. 3(E)) is written by writing the gain data memory section 41 (SP4N) N-2 (FIG. 3(E)).
(Fig. (F)) can be written into the gain data memory section 41.

In this way, the gain controller 26 operates in synchronization with the system clock CLSfH in the first processing mode.
2nd...12th (N=1.2...P12
)CPU2 due to the operation of changing the gain amount of the channel.
Execute the data rewrite operation from 9.

While executing the processing in the first processing mode, the write/continuation control signal S HP" is output from the multiplication circuit 25.
1 (FIG. 2), the gain controller 26 enters the second processing mode described above with respect to FIG. Interrupt processing step (S P
M), 4-1-12 (Fig. 3(D)) is executed.

At that time, the multiplier circuit 25 operates for each channel M=1 to
12, the gain amount data (MPY) M of the channel in which the write/continuous output control signal 5HPV is generated can be read from the gain data memory section 41.

As a result, the gain data memory section 41 performs the sequence processing step (S P 5 N) N-1 of the gain processing period T1 of the first channel, as shown in FIG.
Sequence processing step (SP4N) M, □, (SP 5 N) H-t of channel gain processing period T2
, the sequence processing step (S P 5 N) of the gain processing period T3 of the third channel N-3..., the gain amount data (DGAIN) 3, CP
LI data (CPU) P, gain amount data (DGA
, , ) , , (DGAIN) * are stored sequentially.

According to the above-described configuration, the gain controller 26 executes gain calculations for all channels in synchronization with the system clock CLst14 while maintaining an asynchronous relationship with the multiplication operation of the multiplication circuit 25, and
By preferentially executing the data reading process of the multiplication circuit 25 when an interrupt command arrives from the multiplication circuit 5, the volume adjustment process for a large number of channels can be realized with an extremely simple configuration.

Incidentally, the calculation of the gain amount of all channels is performed in the sequence processing step (S P I N) s-+~rt, (
SP2N)s-+~17, (S P 3 N) N-1
~, A, (S P 5 N)) I. , . . . , 2 can be executed in a time-division manner during one sample period, so there is no need to provide the arithmetic processing means in parallel for all channels.

Furthermore, when gain amount change data is input from the CPU 29, the period for processing it is executed as one of the sequence processing steps (S P 4 N) N-1 to 12, so that the CPU 29 The timing of data write processing from and gain controller 2
The time management between the timing of gain amount calculation processing in step 6 can be realized with a simple configuration.

In addition, by interrupting the sequence processing step to read out the gain amount data for the multiplication circuit 25, the timing of the arithmetic processing in the multiplication circuit 25 and the gain amount in the gain controller 26 can be adjusted. Time management between calculation processing timing can be realized with a very simple configuration.

(G2) Other Embodiments (1) In the above embodiment, the writing process of data (CPU) P from the CPU 29 is performed in the fourth sequence processing step (S P 4 ) of the sequence processing steps.
N) Although the order of the sequence processing steps is set to N-1 to 1□, the order of the sequence processing steps is not limited to this and may be changed in various ways.

(2) In the above embodiment, a case was described in which five processes are performed as sequence processing steps, but even if the number of steps is five or more including other processes, the same result as in the above case will occur. effect can be obtained.

(3) In the above embodiment, as described above for equations (1) to (7), the calculation result of the initial value data (INIT) N and the step data (STEP) s is used as the initial value data (INIT). N is written in the gain data memory section 41, but instead of this, the gain amount data obtained by calculation is written as initial value data (INI
T), other data (DGAIH) are stored in the gain data memory unit 41 separately from the initial value data (INIT) as s, and the gain amount data (DGAIH) is stored separately from the initial value data (INIT).
Even if N) is read out by the multiplication circuit 25, the same effect as in the above case can be obtained.

(4) In the above embodiment, as shown in FIG.
In the above description, a configuration having only the function of reading the gain amount data from the gain data memory section 41 of No. 6 is used. Even if data can be written in accordance with the above, the same effect as in the above case can be obtained.

In this case, as shown in FIG. 8 with the same reference numerals assigned to parts corresponding to those in FIG. When a write command is issued to the gain controller 26, the gain controller 26
As shown in FIG. 8(F), data (DWII
I? ! ) It is sufficient to perform a write operation on M.

(5) In the above embodiment, outputs 5ANOIITI to S ANOUT are used as channels for volume adjustment.
4 and S (IIGOUT+ ”” S DIGOL1
Although 4 channels (i.e., 9th to 12th channels) are allocated to the audio output signals, it is also possible to allocate 8 channels (i.e., 9th to 16th channels) to all audio output signals. The same effect can be obtained as in the case of .

(6) In the above embodiment, one sampling period (
=1/FS), but the total number of sequence processing steps is not limited to this and may be increased or decreased as necessary.

H Effects of the Invention As described above, according to the present invention, by time-sharingly processing the gain amounts of multiple channels in accordance with a series of sequence processing steps, an arbitrary rate of change can be achieved as necessary. In addition to adjusting the volume, the multiplication circuit that performs asynchronous arithmetic operations interrupts the sequence processing step and reads the gain data, making the overall configuration simple even when the number of channels increases. It is possible to realize a volume adjustment device that does not have to be complicated and large-scale.

In this way, when the sound-IUN adjustment data is taken into the gain controller, the processing of the volume change data is processed as one step included in the sequence processing step, so that the writing operation of the change data is performed as a gain controller. Even if it is configured to occur asynchronously with the quantity calculation operation, it can be reliably captured, thereby further simplifying the component of this minute time management.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the volume adjustment device according to the present invention, FIG. 2 is a block diagram showing the detailed configuration of the gain controller, and FIG. 3 is a signal waveform diagram for explaining the operation of FIG. 2. , Fig. 4 is a chart for explaining the setting data input from the CPU in Fig. 1, Fig. 5 is a signal waveform diagram showing changes in gain amount data, and Figs. 6 and 7 are sequence processing of the gain controller. 8 is a signal waveform diagram illustrating another embodiment of the present invention; FIG. 9 is a block diagram illustrating a conventional volume adjustment circuit;
FIG. 10 is a block diagram showing the configuration of the gain controller, and FIG. 11 is a signal waveform diagram for explaining changes in the gain amount data in FIG. 10. 21...Digital volume adjustment circuit, 24...
... Main controller, 25 ... Multiplier circuit, 26 ... Gain controller, 29 ...
...CPU, 30...Settings panel, 41...
...Gain data memory section, 42...Calculation section, 43...State control section, 44...Internal address generation section, 45...Address selector ,
46... CPU interface, 51...
...Multiplication circuit interface.

Claims (3)

[Claims] (1) Gain amount data for audio signals of multiple channels is created by time-divisionally processing a series of predetermined sequence processing steps, is stored in the gain data memory section, and is requested to be read out from the multiplier. 2. A volume adjustment device comprising: gain control means for interrupting the processing of the sequence processing step when the above-mentioned sequence processing step occurs, and transmitting the gain amount data of the channel corresponding to the gain amount read request to the multiplication means. (2) The gain control means interrupts the readout process corresponding to the gain amount readout request generated from the multiplication means into the sequence processing step in the order of highest priority. Volume adjustment device as described. (3) The gain control means includes a volume adjustment processing step in the series of sequence processing steps, and when a volume change request is generated from the volume data input means, the gain control means applies the volume change data to the processing of the series of sequence processing steps. 2. The volume adjustment device according to claim 1, wherein the data to be used is written into the gain data memory section.