JPS6258548B2 - - Google Patents

Info

Publication number
JPS6258548B2
JPS6258548B2 JP56054089A JP5408981A JPS6258548B2 JP S6258548 B2 JPS6258548 B2 JP S6258548B2 JP 56054089 A JP56054089 A JP 56054089A JP 5408981 A JP5408981 A JP 5408981A JP S6258548 B2 JPS6258548 B2 JP S6258548B2
Authority
JP
Japan
Prior art keywords
lead frame
alloy
semiconductor
lead
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56054089A
Other languages
Japanese (ja)
Other versions
JPS57169265A (en
Inventor
Ryozo Yamagishi
Osamu Yoshioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP56054089A priority Critical patent/JPS57169265A/en
Publication of JPS57169265A publication Critical patent/JPS57169265A/en
Publication of JPS6258548B2 publication Critical patent/JPS6258548B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
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    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
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    • H01L2924/01028—Nickel [Ni]
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To reduce cost, and to improve reliability by forming an Ni or Co alloy plated layer containing phosphorus to at least a semiconductor element arranging section and lead terminal section of the base body of the lead frame for the semiconductor while using a glossy copper plated layer as a foundation. CONSTITUTION:The base body 1 made of phosphor bronze is punched and molded, and the semiconductor element arranging section 2 and lead terminal section 3 of the lead frame are formed, and the glossy copper plated layer 4 in 4mum and the Ni or Co alloy plated layer 5 containing phosphrous in 2mum are shaped onto the base body 1. Accordingly, cost is reduced because the precious metals are not used, an Al alloy bonding wire can be employed while the leg breaking property of the lead frame is improved, and reliability is ameliorated.

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明はIC等半導体装置を組立てるときにそ
の構成材料として用いられる半導体用リードフレ
ームに関する。 一般に、半導体用リードフレームの基体材料
（ベース材料）としては、鉄−ニツケル合金、銅
合金又はそれらの単体金属からなる材料が主に用
いられている。 そして、これらの材料には、プレスによる打抜
き後半導体装置を組立てるときに所望のボンデイ
ング機能を持たせるために、金メツキ或いは銀メ
ツキを表面に施すことが行われている。 金や銀は普通の金属よりも耐食性に優れ、それ
だけボンデイング性にも優れているが、高価であ
ることから、ダイボンド部（素子配置部）、ワイ
ヤボンド部（リード端子部）のみ部分的にメツキ
を行い、リードフレームのコストを低くすること
が一般に行われている。さらに、コストを下げる
ためにメツキ厚を薄くする等の検討も行われてい
るが、基体材料の表地から影響を受けずに所定の
ボンデイング性を確保するためには、金及び銀メ
ツキの厚を３μ以下にすることは難しい。 このため、コストを下げるには、金や銀を使用
しているのでは限界がある。 そういうことから、その対策として、金や銀の
代わりにリンを含有するニツケル合金メツキを用
いる例がある。しかし、Ｐ−Ni合金メツキのみ
では本来のボンデイング性は良いが、表地の影響
を受けることによつてＡ合金ワイヤとのボンデ
イング性に欠けるという難点があり、このため下
地として光沢Niメツキを施している。 ところが、光沢Niメツキは金属として非常に
硬いという性質を有し、このため、半導体装置を
組み立てたあと外部リード（脚部）の曲げ加工が
一般に行われるが、このとき外部リードが折れる
等損傷することがあり、光沢Niメツキは下地メ
ツキとしての機能的安定性に欠けるという欠点が
ある。 本発明の目的は、前記した従来技術の欠点を解
消し、金、銀を排した安価な構造のリードフレー
ムにあつて所定のボンデイング性を得ることがで
きると共に外部リードの曲げ加工性等の作業性を
向上させることができるきわめて実用的な構造の
半導体用リードフレームを提供することにある。 即ち、本発明の要旨とするところは、基体の少
なくとも半導体素子配置部及びワイヤボンデイン
グを行うリード端子部の夫々最表面に、光沢銅メ
ツキ層を下地としてリンを含有するニツケル又は
コバルト合金メツキ層を設けて構成されたことを
特徴とする半導体用リードフレームにある。 本発明においては、光沢銅メツキ層は飽くまで
もボンデイングのために最表面に設けられるリン
を含有するニツケル又はコバルト合金メツキ層の
下地として設けられるものである。これはワイヤ
ボンデイングを例えばＡ合金線で行う場合につ
いてみると、Ｐ含有合金メツキ面におけるワイヤ
ボンデイング性は下地である光沢銅メツキ面の平
滑性に関係するからである。 又、光沢銅メツキ面の平滑性は、基体材料の表
地の平滑性に関係してくる。 即ち、光沢銅メツキ面に所望の平滑性をもたせ
るには、光沢銅メツキ層の厚さは、基体材料が平
滑性に優れた材料の場合は薄く、平滑性の低い材
料の場合は厚くする必要がある。 半導体素子のろう接の作業性を考えて、本発明
においては、Ｐ−Ni合金メツキ層の上にさらに
半田メツキ層を設けることが考えられる。 この場合、半田メツキ層は二層として、表面に
錫又は錫に富んだ合金層を設け、その下に鉛又は
鉛に富んだ合金層を設けることにより、全体とし
て鉛80〜98重量％の組成の半田層とすることが望
ましい。 鉛80〜98重量％の組成の半田は、半導体素子と
の熱膨張の整合性の点で有利であるが、変色し易
いという問題点がある。しかし、表面に錫がある
とそのような変色を防止することができる。 又、鉛80〜98重量％の組成の半田は、熱膨張係
数が半導体素子のそれと近く、ヒートサイクル等
によつて、半導体素子の割れが発生しにくいとい
える。鉛80〜98重量％という半田の組成範囲につ
いては、鉛が98重量％を越えると半導体素子との
ぬれ性が低下し、一方鉛80重量％未満では熱膨張
係数が大きくなつて、ヒートサイクル等で半導体
素子の割れが発生するということから、定められ
たものである。 次に添付図面により本発明半導体用リードフレ
ームの実施例について説明する。 実施例 １ 第１図はリン青銅からなる基体１を打抜いて図
示の如きパターン形状に成形したリードフレーム
の正面図を示す。この図において、２は半導体素
子配置部（ダイボンド部）、３はリード端子部
（ワイヤボンド部）である。 第２図は本発明の実施例に係るリードフレーム
の断面を示し、上記リードフレームの一面に光沢
銅メツキ層４を４μ、さらにＰ−Ni合金メツキ
層５を２μ設けてなる。 即ち、このものは上記リードフレームを脱脂処
理、酸洗処理後、硫酸銅浴で光沢銅メツキを４μ
を行い、さらにその上に電気Ｐ−Niメツキ浴で
Ｐ−Ni合金メツキを２μ行つて構成したもので
ある。 尚、このリードフレームにおいて、第３図のよ
うに、Ｐ−Ni合金メツキ層５上にさらに半田メ
ツキ層６を設けることができる。 このようにすれば、半導体素子の接着を有利に
行うことができる。 第４図は、半田箔７を用いて上記リードフレー
ムの所定位置に半導体素子８を加熱圧接後、半導
体素子８とリード端子部３とをＡ合金ワイヤ９
にてワイヤボンデイングして作成した半導体装置
の断面を示す。 比較のため、従来例として、リン青銅を基体と
するリードフレーム上に、直接Ｐ−Ni合金メツ
キを２μ設けたもの、光沢Niメツキを４μ設け
た後、Ｐ−Ni合金メツキを２μ設けたもの、又
Auメツキを４μ部分メツキしたものを、夫々上
記実施例と同様の方法で半導体装置に作成した。
これら実施例及び従来例について、次の試験を行
い評価した。この結果は、表１に示す通りであ
る。 (1) ワイヤボンデイング性 Ａ合金ワイヤをボンデイング後、引張試験に
より、Ａ合金ワイヤが破断するものを良好〇、
Ａ合金ワイヤがメツキ面で剥離するものを不良
×とした。 (2) ワイヤ腐食性 高温高湿環境下で放置し、メツキ面でＡ合金
ワイヤに接触腐食が発生するか否かで判定した。 〇：腐食なし、×：腐食有り。 (3) 脚折れ性 半導体装置の脚部（外部リード）において90゜
曲げを繰り返し、脚部の破断するまでの回数で判
定した。 〇：70回以上、×：６回以下。 実施例 ２ リン青銅を基体とするリードフレーム上に、実
施例１と同様光沢銅メツキを４μ、Ｐ−Niメツ
キを２μメツキした。さらに、第３図のように半
導体素子配置部に半田メツキを10μ部分メツキし
て、ろう材である半田箔の代わりとした。 半田メツキは組成と構造を変えて検討した。実
施例１と同様に、半導体装置として作成後、次の
試験を行い評価した。この結果は表２に示す通り
である。 (1) ぬれ性 半導体素子を剥離して、ろう材とのぬれ面積に
より評価した。〇：70％以上、△：70〜50％、
×：50％未満。 (2) ヒートサイクル −50℃←→150℃を１サイクルとして、これを200
回行つた後、半導体素子の割れ発生有無により評
価した。〇：割れなし、×：割れ発生。 The present invention relates to a semiconductor lead frame used as a constituent material when assembling a semiconductor device such as an IC. In general, materials made of iron-nickel alloys, copper alloys, or single metals thereof are mainly used as base materials for semiconductor lead frames. After punching with a press, these materials are plated with gold or silver on their surfaces in order to have a desired bonding function when assembling a semiconductor device. Gold and silver have better corrosion resistance than ordinary metals and have better bonding properties, but because they are expensive, only the die bond area (element placement area) and wire bond area (lead terminal area) are partially plated. It is common practice to reduce the cost of lead frames by doing this. Furthermore, studies are being conducted to reduce the thickness of the plating in order to reduce costs, but in order to ensure the desired bonding properties without being affected by the outer surface of the base material, the thickness of the gold and silver plating must be reduced. It is difficult to reduce the thickness to 3μ or less. For this reason, there is a limit to reducing costs by using gold or silver. For this reason, as a countermeasure, there are examples of using nickel alloy plating containing phosphorus instead of gold or silver. However, although P-Ni alloy plating alone has good bonding properties, it has the disadvantage that it lacks bonding properties with A alloy wire due to the influence of the surface material. There is. However, bright Ni plating has the property of being extremely hard as a metal, and for this reason, the external leads (legs) are generally bent after the semiconductor device is assembled, but this can cause damage such as breakage of the external leads. However, glossy Ni plating has the disadvantage of lacking functional stability as a base plating. An object of the present invention is to solve the above-mentioned drawbacks of the prior art, to provide a lead frame with an inexpensive structure that eliminates gold and silver, and to provide a predetermined bonding property, as well as ease of work such as bending workability of external leads. An object of the present invention is to provide a semiconductor lead frame having an extremely practical structure that can improve performance. That is, the gist of the present invention is to provide a phosphorous-containing nickel or cobalt alloy plating layer on the outermost surface of at least the semiconductor element placement area and the lead terminal area for wire bonding, respectively, of the base body, with a bright copper plating layer as a base. There is provided a lead frame for a semiconductor, characterized in that the lead frame is provided with the following structure. In the present invention, the bright copper plating layer is provided as a base for the phosphorus-containing nickel or cobalt alloy plating layer provided on the outermost surface for bonding. This is because when wire bonding is performed using, for example, an A alloy wire, the wire bonding properties on the P-containing alloy plating surface are related to the smoothness of the underlying bright copper plating surface. Furthermore, the smoothness of the bright copper plating surface is related to the smoothness of the surface of the base material. In other words, in order to give the bright copper plating surface the desired smoothness, the thickness of the bright copper plating layer needs to be thin when the base material is a material with excellent smoothness, and thick when the base material is a material with low smoothness. There is. Considering the workability of soldering semiconductor elements, it is conceivable in the present invention to further provide a solder plating layer on the P-Ni alloy plating layer. In this case, the solder plating layer is two-layered, with a tin or tin-rich alloy layer on the surface and a lead or lead-rich alloy layer below, resulting in an overall lead composition of 80 to 98% by weight. It is desirable to have a solder layer of Solder having a composition of 80 to 98% by weight lead is advantageous in terms of thermal expansion matching with the semiconductor element, but has the problem of being susceptible to discoloration. However, the presence of tin on the surface can prevent such discoloration. Further, solder having a composition of 80 to 98% by weight of lead has a coefficient of thermal expansion close to that of the semiconductor element, and it can be said that the semiconductor element is less likely to crack due to heat cycles or the like. Regarding the solder composition range of 80 to 98% lead by weight, if the lead content exceeds 98% by weight, the wettability with the semiconductor element will decrease, while if the lead content is less than 80% by weight, the coefficient of thermal expansion will increase and heat cycles etc. This was established because cracking of semiconductor elements occurs in Next, embodiments of the semiconductor lead frame of the present invention will be described with reference to the accompanying drawings. Embodiment 1 FIG. 1 shows a front view of a lead frame formed by punching out a base 1 made of phosphor bronze and molding it into the pattern shown. In this figure, 2 is a semiconductor element arrangement part (die bond part), and 3 is a lead terminal part (wire bond part). FIG. 2 shows a cross section of a lead frame according to an embodiment of the present invention, in which a bright copper plating layer 4 of 4 μm and a P-Ni alloy plating layer 5 of 2 μm are provided on one surface of the lead frame. In other words, this lead frame is degreased and pickled, and then plated with 4 μm of bright copper in a copper sulfate bath.
This was followed by 2μ of P-Ni alloy plating using an electric P-Ni plating bath. In this lead frame, a solder plating layer 6 can be further provided on the P--Ni alloy plating layer 5, as shown in FIG. In this way, the semiconductor elements can be bonded advantageously. FIG. 4 shows that after heat-pressing the semiconductor element 8 to a predetermined position of the lead frame using the solder foil 7, the semiconductor element 8 and the lead terminal portion 3 are connected to the A alloy wire 9.
This figure shows a cross section of a semiconductor device fabricated by wire bonding. For comparison, conventional examples include one in which 2μ of P-Ni alloy plating is directly applied to a lead frame based on phosphor bronze, and one in which 4μ of bright Ni plating is applied and then 2μ of P-Ni alloy plating is applied. ,or
Semiconductor devices were fabricated using a method similar to that of the above-mentioned embodiments, each having a 4μ portion plated with Au.
The following tests were conducted and evaluated for these examples and conventional examples. The results are shown in Table 1. (1) Wire bonding properties After bonding the A alloy wire, a tensile test is conducted and the one where the A alloy wire breaks is rated as good.
Those in which the A alloy wire peeled off on the plating surface were rated as defective. (2) Wire Corrosion It was judged by whether contact corrosion occurred on the A alloy wire on the plating surface after leaving it in a high temperature and high humidity environment. 〇: No corrosion, ×: Corrosion. (3) Leg breakability The legs (external leads) of the semiconductor device were repeatedly bent by 90° and judged by the number of times until the legs broke. ○: 70 times or more, ×: 6 times or less. Example 2 As in Example 1, 4 μm of bright copper plating and 2 μm of P-Ni plating were plated on a lead frame having a phosphor bronze base. Furthermore, as shown in FIG. 3, a 10 μm portion of the semiconductor element placement area was plated with solder plating to replace the solder foil, which is a brazing material. Solder plating was examined by changing its composition and structure. As in Example 1, after fabricating a semiconductor device, the following tests were conducted and evaluated. The results are shown in Table 2. (1) Wettability The semiconductor element was peeled off and evaluated based on the wetted area with the brazing material. 〇: 70% or more, △: 70-50%,
×: Less than 50%. (2) Heat cycle -50℃←→150℃ is one cycle, and this is 200℃
After the test was carried out, evaluation was made based on the presence or absence of cracks in the semiconductor element. 〇: No cracking, ×: Cracking occurred.

【表】【table】

【表】 尚、本発明においては、Ｐ−Ni合金メツキの
下地として光沢銅メツキを行うのは、本来Ｐ−
Ni合金メツキ面の平滑性を調整し、それにより
Ａ合金ワイヤをワイヤボンデイングする際にお
けるワイヤボンデイング性を確保したいがためで
ある。このワイヤボンデイング性を確保した上
で、外部リードに対する曲げ加工性に悪影響を与
えないものということで光沢銅メツキが選ばれた
のである。従つて、そういう意味から、光沢銅メ
ツキ及びＰ−Ni合金はいずれもボンデイング性
を必要とする機能性にのみ部分メツキすることも
可能である。 以上説明から明らかなように、本発明の半導体
用リードフレームによれば、リンを含有するニツ
ケル又はコバルト合金メツキ層の下地として光沢
銅メツキ層を設けることにより、金、銀を排した
安価な構造のリードフレームにあつて所望のボン
デイング性を得ることができると共に、Niメツ
キがないために外部リード（脚部）の曲げ加工性
等の作業性を向上させることができるという効果
を有する。従つて、本リードフレームの使用によ
り、組立て時における信頼性を著しく向上させる
ことができ、又、半導体装置そのものの価格を低
下させることも可能である。[Table] In addition, in the present invention, bright copper plating is performed as a base for P-Ni alloy plating, which is originally P-Ni alloy plating.
This is because it is desired to adjust the smoothness of the Ni alloy plating surface and thereby ensure wire bonding properties when wire bonding the A alloy wire. Bright copper plating was selected because it ensured wire bonding properties and did not adversely affect the bending workability of external leads. Therefore, in this sense, both bright copper plating and P-Ni alloy can be partially plated only for functionality that requires bonding properties. As is clear from the above description, the semiconductor lead frame of the present invention has an inexpensive structure that eliminates gold and silver by providing a bright copper plating layer as the base of the phosphorous-containing nickel or cobalt alloy plating layer. In addition to being able to obtain the desired bonding properties in the lead frame, since there is no Ni plating, workability such as bending workability of the external leads (legs) can be improved. Therefore, by using this lead frame, reliability during assembly can be significantly improved, and the cost of the semiconductor device itself can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は一般に用いられているプレスによる打
抜き後の半導体用リードフレームの平面図、第２
図は本発明の一実施例に係る半導体用リードフレ
ームの断面図、第３図は本発明の他の実施例に係
る半導体用リードフレームの断面図、第４図は半
導体の断面図である。 １……基体、２……半導体素子配置部、３……
リード端子部、４……光沢銅メツキ層、５……Ｐ
−Ni合金メツキ層、６……半田メツキ層、７…
…半田箔、８……半導体素子、９……Ａ合金ワ
イヤ。 Figure 1 is a plan view of a semiconductor lead frame after punching with a commonly used press;
FIG. 3 is a cross-sectional view of a semiconductor lead frame according to an embodiment of the present invention, FIG. 3 is a cross-sectional view of a semiconductor lead frame according to another embodiment of the present invention, and FIG. 4 is a cross-sectional view of the semiconductor. 1...Base body, 2...Semiconductor element arrangement portion, 3...
Lead terminal part, 4...bright copper plating layer, 5...P
−Ni alloy plating layer, 6...Solder plating layer, 7...
...Solder foil, 8...Semiconductor element, 9...A alloy wire.

Claims (1)

【特許請求の範囲】[Claims] １ 基体の少なくとも半導体素子配置部及びワイ
ヤボンデイングを行うリード端子部の夫々最表面
に、光沢銅メツキ層を下地としてリンを含有する
ニツケル又はコバルト合金メツキ層を設けて構成
されたことを特徴とする半導体用リードフレー
ム。1. A phosphorous-containing nickel or cobalt alloy plating layer is provided on the outermost surface of at least the semiconductor element placement area and the lead terminal area for wire bonding, respectively, of the base body, with a bright copper plating layer as a base. Lead frame for semiconductors.
JP56054089A 1981-04-10 1981-04-10 Lead frame for semiconductor Granted JPS57169265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56054089A JPS57169265A (en) 1981-04-10 1981-04-10 Lead frame for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56054089A JPS57169265A (en) 1981-04-10 1981-04-10 Lead frame for semiconductor

Publications (2)

Publication Number Publication Date
JPS57169265A JPS57169265A (en) 1982-10-18
JPS6258548B2 true JPS6258548B2 (en) 1987-12-07

Family

ID=12960887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56054089A Granted JPS57169265A (en) 1981-04-10 1981-04-10 Lead frame for semiconductor

Country Status (1)

Country Link
JP (1) JPS57169265A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835984A (en) * 1981-08-28 1983-03-02 Hitachi Ltd Zener diode
US6140703A (en) * 1996-08-05 2000-10-31 Motorola, Inc. Semiconductor metallization structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5792854A (en) * 1980-11-29 1982-06-09 Toshiba Corp Plastic molded type semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5792854A (en) * 1980-11-29 1982-06-09 Toshiba Corp Plastic molded type semiconductor device

Also Published As

Publication number Publication date
JPS57169265A (en) 1982-10-18

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