KR100673951B1 - Lead frame for semiconductor package - Google Patents

Abstract

The present invention is to provide a lead frame for a semiconductor package having a structure excellent in delamination quality and EMC adhesion even in a harsh heating humidification environment, and the present invention, in order to achieve this object, the base metal layer made of a metal material And a Ni plating layer made of nickel or a nickel alloy, stacked on at least one surface of the base metal layer, a Pd plating layer made of a palladium or palladium alloy, and a Pd plating layer made of palladium or a palladium alloy, Provided is a lead frame for a semiconductor package having an Ag plated layer formed on the Ag plated layer and a protective plated layer made of gold or a gold alloy.

Description

Lead frame for semiconductor package

1 is a plan view schematically showing the structure of a conventional lead frame for a semiconductor package,

2 is a cross-sectional view showing a single layer structure of a conventional lead frame for a semiconductor package,

3A and 3B are cross-sectional views showing a single layer structure of another conventional lead frame for a semiconductor package,

4 is a cross-sectional view illustrating a single layer structure of a lead frame for a semiconductor package according to an embodiment of the present invention.

FIG. 5 is a table comparing delamination qualities of a lead frame having a plating layer of Ni / Pd / Au-Pd and a lead frame having a plating layer of Ni / Pd / Au-Ag.

6 is a graph comparing the EMC adhesion between the lead frame and the other comparative material according to the present invention,

7 is a table comparing the delamination quality of the lead frame and the other comparative material according to the present invention.

Explanation of symbols on the main parts of the drawings

1: Lead frame for semiconductor package 2: Die pad

3: pad support 4: inner lead

5: external lead 6: dambar

110: base metal layer 120: Ni plating layer

130: Pd plating layer 140: Ag plating layer

150: protective plating layer

The present invention relates to a lead frame for a semiconductor package, and more specifically, to a semiconductor package by connecting a semiconductor chip and an external circuit, and having a structure having excellent EMC (Epoxy Molding Compound) adhesion even in a harsh external environment. A lead frame for semiconductor packages.

The lead frame for a semiconductor package is one of the core components of a semiconductor package together with a semiconductor chip, and serves as a lead for connecting the semiconductor package to the outside and a support frame for supporting the semiconductor chip. Plays a role.

1 is a plan view of a lead frame for a conventional semiconductor package. As shown in FIG. 1, the lead frame 1 has a die pad 2 and leads 4, 5.

The die pad 2 is connected to the rail 7 by the pad support 3 and has a function of supporting the semiconductor chip.

Leads 4 and 5 have an inner lead 4 and an outer lead 5 and maintain and support the spacing of each lead between the inner lead 4 and the outer lead 5. A dam bar 6 is formed. When the assembly of the semiconductor package is completed, the rail 7 and the dam bar 6 are removed.

The lead frame having such a structure forms a semiconductor package through an assembly process with a semiconductor chip as a memory device. The semiconductor assembly process includes a die attach process, a wire bonding process, and a molding process. The die attach process is a process of attaching a semiconductor chip (die) to a pad of a lead frame. The wire bonding process is a process of joining and connecting the terminal portion of the semiconductor chip and the internal lead of the lead frame with gold, and the molding process is an EMC resin. It is a process of sealing a chip | tip, a wire, and an internal lead part with insulators, such as these.

In order to improve adhesion to the semiconductor chip in the die attaching step of the assembling process of the semiconductor and to improve the wire bonding property of the inner lead in the wire bonding process, the die pad 2 and the inner lead 4 have predetermined characteristics. Metallic materials are often applied. In addition, after the molding process, in order to improve solder wettability in the process in which the external lead 5 is mounted on the substrate, soldering base plating of an alloy of tin and lead (Sn-Pb) is performed on a predetermined portion of the external lead. .

However, the soldering base plating process is cumbersome and causes environmental problems due to exposed lead and lead plating solutions. In addition, there is a problem in that an additional process is required to remove the non-uniformity of the plating layer during the soldering base plating process, and the plating solution penetrates between the lead frame surface and the EMC frequently to cause a defect of the semiconductor chip.

In order to solve the above problems, a pre-plated frame has been proposed. In this method, the lead plating step in the post-semiconductor step can be omitted by applying the material having excellent solder wettability to the metal material before the semiconductor package step. The lead frame using the leading gold method has been in the spotlight recently because it not only simplifies the post-process but also reduces the environmental pollution process such as lead plating in the semiconductor package process.

2 is a schematic cross-sectional view showing an example of a lead frame manufactured using a conventional lead gold method. Referring to FIG. 2, it can be seen that the Ni plating layer 12 is entirely formed on the upper layer of the base metal layer 11 containing copper as a main component, and the Pd plating layer 13 is formed directly on the Ni plating layer 12. have. In other words, nickel and palladium are sequentially plated on the upper layer of the base metal layer 11.

Using a lead frame plated with palladium as the uppermost layer as described above can be environmentally friendly and simplify the manufacturing process of the semiconductor package. However, the Pd plating layer 13 formed of palladium is oxidized by the heat generated during the semiconductor assembly process to form a palladium compound, and therefore the physical properties thereof are easily lowered. The oxidation of the Pd plating layer 13 and the deterioration of physical properties thereof lower the wire bonding property and the solderability. In addition, when hydrogen is adsorbed at the time of plating, the plating surface is hardened, and thus there is a problem of weakening the impact.

To solve this problem, the lead frame disclosed in US Pat. No. 6469386 is shown in FIGS. 3A and 3B. 3A and 3B, the Ni plating layer 22, the Pd plating layer 23, the gold plating layer 24a, or the gold-palladium alloy plating layer 24b are sequentially plated on the base metal layer 21 of the metal material. . This structure is essentially the same as the structure shown in FIG. 2 except for the uppermost gold or gold-palladium alloy plating layers 24a and 24b.

Gold is more oxidation resistant than palladium. Therefore, as shown in FIG. 3A, when the pure gold plating layer 24a is formed on the top of the lead frame, the Pd plating layer 23 is oxidized while the gold plating layer 24a undergoes a thermal process in manufacturing a semiconductor package. The conventional solderability problem could be solved by preventing that.

However, in general, EMC resins are inferior in affinity with the surface of pure metals or alloys, and conversely, when the oxide layer is formed on the surface, the adhesion is excellent. For this reason, when pure gold plating layer is formed as a palladium antioxidant layer on the contact surface of EMC, the problem of the adhesiveness of EMC arises.

In this case, as shown in FIG. 3B, when the gold-palladium alloy plating layer 24b made of gold and palladium is formed on the Pd plating layer, the palladium constituting the gold-palladium alloy plating layer 24b is oxidized by EMC. The adhesion is excellent.

However, in recent years, manufacturing of environmentally friendly semiconductor packages has become a major concern, and in such environmentally friendly semiconductor packages, excellent adhesion between EMC and lead frames is required even in harsh environments with high humidity and temperature. There is a problem that the palladium alloy plating layer 24b has a poor EMC adhesiveness.

That is, as described later, according to the results of the evaluation of the Moisture Sensitivity Level (MSL) through a coupon test after 168 hours at a temperature of 85 ° C. and a relative humidity of 85%, the quality of delamination is poor. Appearance and the low EMC adhesion, there is a problem that the EMC adhesion in a poor moisture absorption environment is degraded.

Disclosure of Invention The present invention has been made to solve various problems including the above problems, and an object thereof is to provide a lead package for a semiconductor package having a structure having excellent delamination quality and EMC adhesiveness even in a poorly heated humidified environment.

In order to achieve the above object, the present invention is:

A base metal layer made of a metal material;

A Ni plating layer laminated on at least one surface of the base metal layer and made of nickel or a nickel alloy;

A Pd plating layer laminated on the Ni plating layer and made of palladium or a palladium alloy;

An Ag plating layer laminated on the Pd plating layer and made of silver or a silver alloy; And

Provided is a lead package for a semiconductor package comprising a protective plating layer laminated on the Ag plating layer and made of gold or gold alloy.

The Ag plating layer preferably has a thickness of 5 μ ″ to 30 μ ″.

Here, the protective plating layer is preferably made of a gold-silver alloy, in this case, it is more preferable that the weight fractions of silver and gold constituting the protective plating layer are substantially the same.

In addition, the protective plating layer preferably has a thickness of 0.2μ "to 2.0μ", in this case, the thickness of the Ni plating layer is 10μ "to 120μ", the thickness of the Pd plating layer is 0.1μ "to 3μ" More preferred.

On the other hand, the base metal layer is preferably made of a copper or alloy 42 (alloy42) material.

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view schematically showing a single layer structure of a lead frame for a semiconductor package according to a preferred embodiment of the present invention.

Referring to FIG. 4, a lead frame for a semiconductor package according to an embodiment of the present invention includes a base metal layer 110, a Ni plating layer 120 formed of nickel or a nickel alloy on an upper surface of the base material 110, and Pd plating layer 130 made of palladium or palladium alloy on the upper surface of the Ni plating layer 120, Ag plating layer 140 made of silver on the upper surface of the Pd plating layer 130, and gold or gold alloy on the Ag plating layer upper surface The protective plating layer 150 is formed.

The base metal layer 110 is usually made of copper or alloy 42 material.

The Ni plating layer 120 prevents the material of the base metal layer 110, for example, copper or iron-based nickel, from diffusing to the lead frame surface to generate copper oxide or copper sulfide.

Palladium or palladium alloys are usually metals with very good solder wettability. Therefore, the Pd plating layer 120 formed on the Ni plating layer 120 functions to protect the surface of the Ni plating layer 120 and to facilitate soldering.

The protective plating layer 150 is made of gold or a gold alloy, and serves as an anti-oxidation layer of the Pd plating layer 130, thereby preventing the Pd plating layer 130 from being oxidized during the thermal process during the manufacture of the semiconductor package. 5: The solderability of FIG. 1) is not reduced.

In this case, silver (Ag) is relatively excellent in adhesiveness with respect to the EMC resin for semiconductor packages compared with gold (Au). Therefore, it is preferable that the protective plating layer 150 is formed of an alloy of gold and silver, thereby improving the EMC adhesion, which is the adhesion between the lead frame and the EMC.

For lead frames having a base metal layer, a Ni plating layer, and a Pd plating layer of the same thickness and composition, and the protective plating layer is a gold-palladium alloy plating layer or a gold-silver alloy plating layer, respectively, the process of level 3 and level 2 is performed. After rough, the MSL evaluation using the SAM as shown in Figure 5 can be clearly seen. Here, the level 3 process means a moisture absorption process of 192 hours at a temperature of 30 ° C. and a relative humidity of 60%, and the level 2 process is a moisture absorption process of 168 hours at a temperature of 85 ° C. and a relative humidity of 60%, which is more severe than the level 3 process. it means.

That is, as shown in FIG. 5, especially when the level 2 process is performed, the degree of delamination occurs in the lead frame in which the protective plating layer is the gold-silver alloy plating layer, compared to the lead frame in which the protective plating layer is the gold-palladium alloy plating layer. It can be seen that it appears very small.

However, after the level 1 process, which is more severe than the level 2 process, that is, 168 hours with a temperature of 85 ° C. and a relative humidity of 85%, delamination occurs even in a lead frame in which the protective plating layer is a gold-silver alloy plating layer. It can be seen that the degree is large, and because of this, the lead frame in which the Ni plating layer 120, the Pd plating layer 130, and the protective plating layer 150 made of a gold-silver alloy is sequentially formed on the base metal layer 110 has a relative humidity. EMC adhesion is not good in very large external environments.

Therefore, in the present invention, the Ag plating layer 140 is formed between the Pd plating layer 130 and the protective plating layer 150 to maintain the EMC adhesiveness not only in the normal external environment but also in the thermal external environment.

That is, the Ag plating layer 140 is formed by plating silver on the upper side of the Pd plating layer 130 by using the high oxidation resistance of the silver (Ag) material, so that the Ag plating layer 140 may have the harsh moisture absorption environment. (130) effectively prevents the oxidation of the surface, and serves to prevent the diffusion of nickel and palladium, which is a material of the Pd plating layer 130 and Ni plating layer 120 to the protective plating layer. This maintains excellent solderability by maintaining the physical properties of the protective plating layer even under severe thermal external environments.

In this case, the thickness D4 of the Ag plating layer 140 is preferably 5 μ ″ (micro inch) to 30 μ ″, which is when nickel and palladium are the protective plating layer when the thickness D4 of the Ag plating layer is smaller than 5 μ ″. This is because it is difficult to prevent diffusion to 150, and when the thickness D4 is larger than 30 mu ", the plating material cost increases and productivity falls.

In this case, the thickness D5 of the protective plating layer 150 made of a gold-silver alloy is preferably 0.2 μ ″ to 2.0 μ ″. This is because when the thickness (D5) of the protective plating layer is formed to be smaller than 0.2 µ ", the coating thickness is thin, so that the management is difficult, and the management cost is excessively increased, and the thickness (D5) of the protective plating layer is higher than 2.0 µ". If the formation is large, it will have an excessive EMC adhesion beyond the required target EMC adhesion force is not significant to improve the reliability of the semiconductor package, in particular, because the consumption of expensive gold increases the manufacturing cost excessively.

In addition, the thickness of the Ni plating layer (D2) is 10μ "to 120μ", the thickness of the Pd plating layer (D3) is more preferably 0.1μ "to 3μ".

Here, it is more preferable that the weight fractions of silver and gold constituting the protective plating layer 150 are substantially the same. In this case, the protective plating layer 150 simultaneously has excellent oxidation resistance of gold and excellent EMC adhesion of silver. Because it can.

Hereinafter, the features of the present invention will be described in more detail with reference to comparative examples. However, it goes without saying that the scope of the present invention is not limited by the following comparative example.

6 and 7 show a graph showing the EMC shear force after using the coupon test and a table showing the degree of delamination of the EMC after comparing the lead frame according to the present invention with other comparative materials, respectively. have. Here, the degree of delamination represents the degree of contact between the EMC and the lead frame out of the total contactable area between the EMC and the lead frame after application of the following test conditions, that is, after the hygroscopic process and reflow.

On the other hand, the specimen and test conditions are as follows.

Psalms

(1) Lead Frame:

  1) The present invention: After forming a Ni / Pd plating layer on the base metal layer mainly composed of copper with a thickness of 30 / 0.8 micro inches, respectively, and forming an Ag plating layer thereon, protection of the gold-silver alloy of 0.3 micro inches. A plating layer was formed.

   2) First Comparative Material: A Ni / Pd plating layer was formed on the base metal layer mainly composed of copper, each having a thickness of 30 / 0.8 microinches, and a protective plating layer of 0.3 microinches of gold-palladium alloy was formed thereon.

    3) Second Comparative Material: A Ni / Pd plating layer was formed on the base metal layer mainly composed of copper with a thickness of 30 / 0.8 micro inches, respectively, and a protective plating layer of 0.3 micro inch gold-silver alloy was formed thereon.

(2) EMC resin: Model name SL 7300MES (MQFP type, Cheil Industries) was used.

2. Test condition

As below

(1) Curing before mold: 4 hours at 175 ℃

(2) Hygroscopic process: 168 hours at 85 ℃ and 85% relative humidity

(3) Reflow: After sequentially performing the process of up to 260 ℃ (three times), the adhesion of the specimen was measured.

3. testing equipment

(1) SAM: Model name HS-100 (SONIX company)

(2) Strength tester: Model name AGS-100A (Shimadzu) was used.

As shown in FIG. 6, in the case of the lead frame specimen according to the embodiment of the present invention, that is, the Ag plating layer is formed between the Pd plating layer and the protective plating layer, it is much higher than the level required for maintaining the reliability of the semiconductor package in the art. High levels of EMC adhesion above 90 kgf.

On the other hand, the first comparative material has an EMC adhesive strength of 10 Kgf, and the second comparative material has an EMC adhesive strength of 60 Kgf to 70 Kgf. Therefore, it can be seen that the EMC adhesive force of the lead frame having the Ag plating layer formed between the Pd plating layer and the protective plating layer is significantly higher than that of the first and second comparative materials.

On the other hand, as shown in Figure 7, in the case of the present invention it can be seen that almost no delamination occurs. On the other hand, in the case of the first comparative material, the delamination phenomenon occurs in all parts, and in the case of the second comparative material, it can be seen that the delamination phenomenon occurs relatively in comparison with the lead frame material of the present invention.

Therefore, as shown in FIG. 7, it can be seen that the degree of delamination of the lead frame having the Ag plating layer formed between the Pd plating layer and the protective plating layer is significantly smaller than that of the first and second comparative materials.

As described above, according to the lead frame for a semiconductor package according to the present invention, not only the wire bonding property and the solderability, which are the quality targets of the lead frame, but also the EMC adhesive property is greatly improved, so that the reliability of the semiconductor package can be improved.

In particular, the lead frame according to the present invention has excellent EMC adhesiveness and delamination quality even under poor hygroscopic environmental conditions, and is suitable for manufacturing environmentally friendly semiconductor packages such as lead free (Pb free).

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and any person skilled in the art to which the present invention pertains may have various modifications and equivalent other embodiments. Will understand. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (7)

A base metal layer made of a metal material; A Ni plating layer laminated on at least one surface of the base metal layer and made of nickel or a nickel alloy; A Pd plating layer laminated on the Ni plating layer and made of palladium or a palladium alloy; An Ag plating layer laminated on the Pd plating layer and made of silver; And A lead frame for a semiconductor package stacked on the Ag plating layer and having a protective plating layer made of a gold-silver alloy. The method of claim 1, The Ag plating layer is a semiconductor package lead frame, characterized in that having a thickness of 5μ "to 30μ". delete The method of claim 1, A lead frame for a semiconductor package, wherein a weight fraction of silver and gold constituting the protective plating layer is substantially the same. The method of claim 1, The protective plating layer has a thickness of 0.2μ "to 2.0μ" lead frame for a semiconductor package. The method of claim 5, The thickness of the Ni plating layer is 10μ "to 120μ", the thickness of the Pd plating layer is 0.1μ "to 3μ" lead frame for a semiconductor package. The method of claim 1, The base metal layer is a lead frame for a semiconductor package, characterized in that made of copper or alloy 42 (alloy42) material.

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