JPS6256665B2 - - Google Patents
Info
- Publication number
- JPS6256665B2 JPS6256665B2 JP1451583A JP1451583A JPS6256665B2 JP S6256665 B2 JPS6256665 B2 JP S6256665B2 JP 1451583 A JP1451583 A JP 1451583A JP 1451583 A JP1451583 A JP 1451583A JP S6256665 B2 JPS6256665 B2 JP S6256665B2
- Authority
- JP
- Japan
- Prior art keywords
- brazing
- lead frame
- brazing material
- lead
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005219 brazing Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 description 13
- 239000000919 ceramic Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はセラミツク基板等にリードフレームを
ろう付接続するための方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for brazing a lead frame to a ceramic substrate or the like.
従来技術によるリードフレームの一例を第１図
に示す。リードフレーム１はつなぎ部材２によつ
て連結され、その相互間隔（ピツチ）を一定に保
たれている。セラミツク基板３には、リードフレ
ームと同一ピツチでろう付用端子４がその端辺に
設けられている。今、この両者をろう付により接
続するには、リボン状、あるいはワイヤ状のろう
材５をリードフレーム１とセラミツク基板３の端
子４との間にはさみ込み、これら相互間が動かな
いように、側面図第２図の矢印６で示すように加
圧力を加えながら、ろう付温度まで温度をあげ
て、ろう材５を融かすことによつて、リードフレ
ーム１とセラミツク基板の端子４の間にぬれ拡が
らせ、この両者の間をろう接する。ろう接用のろ
う材としては、例えば、銀ろう、あるいは鉛−錫
はんだ、金−錫はんだなどが使用され、それぞ
れ、ろう接温度としては、700〜800℃，200〜300
℃，300〜400℃の範囲の温度が使用される。リー
ドフレーム１と、セラミツク基板３、ろう材５を
相互に位置あわせし保持するために、適正に設計
された保持治具を使用する必要があり銀ろう付け
の場合、カーボン（黒鉛）固体により製作される
ことが多い。
An example of a lead frame according to the prior art is shown in FIG. The lead frames 1 are connected by connecting members 2, and their mutual spacing (pitch) is kept constant. Brazing terminals 4 are provided on the edge of the ceramic substrate 3 at the same pitch as the lead frame. Now, in order to connect these two by brazing, a ribbon-shaped or wire-shaped brazing material 5 is inserted between the lead frame 1 and the terminal 4 of the ceramic substrate 3, so that they do not move. By increasing the temperature to the brazing temperature while applying pressure as shown by the arrow 6 in the side view of FIG. Wet and spread and solder the two. As the brazing material for soldering, for example, silver solder, lead-tin solder, gold-tin solder, etc. are used, and the soldering temperatures are 700-800℃ and 200-300℃, respectively.
℃, temperatures in the range 300-400℃ are used. In order to align and hold the lead frame 1, ceramic substrate 3, and brazing material 5 with each other, it is necessary to use an appropriately designed holding jig.In the case of silver brazing, it is necessary to use a holding jig made of solid carbon (graphite). It is often done.
このようにしてろう接された後の外観及びその
側面図を第３図、第４図に示す。中央部の端子７
では良好な接続が得られるが、両端部でか端子８
と端子９の間、あるいは端子１０と端子１１の間
で図のようにロウ材のブリツジによるシヨートが
発生してしまうことが多い。これは、第１図に示
すように、ろう材のリボンあるいはワイヤ５の両
端部１２，１３がとけて、第３図に示す端子８，
１１に過剰にたまるためである。ろう材５の長さ
を短かくすることによつてこのような不良はある
程度防ぐことができるが、そうすると、ろう材５
が左右に動いた時リードフレーム１からはずれ易
くなり、結果としてろう接不良が発生してしまう
問題がある。 The external appearance and side view after soldering in this manner are shown in FIGS. 3 and 4. Terminal 7 in the center
A good connection can be obtained with the terminal 8 at both ends.
As shown in the figure, shoots often occur between the terminals 9 and 9 or between the terminals 10 and 11 due to bridging of the brazing material. As shown in FIG. 1, both ends 12 and 13 of the brazing material ribbon or wire 5 are melted, and the terminals 8 and 13 shown in FIG.
This is because an excessive amount accumulates in 11. Such defects can be prevented to some extent by shortening the length of the brazing filler metal 5, but in this case, the length of the brazing filler metal 5
When the lead frame moves from side to side, it tends to come off from the lead frame 1, resulting in a problem of poor soldering.
本発明の目的は以上説明した従来技術の問題点
を解決するため、ろう材の左右方向への位置きめ
が容易な程度の長さのろう材を使用してもセラミ
ツク基板の端部において、余剰ろう材によるブリ
ツジ（シヨート）の発生を防止できるようなリー
ドフレームのろう接方法を提供することにある。
An object of the present invention is to solve the problems of the prior art as explained above, and to solve the problems of the prior art described above. It is an object of the present invention to provide a lead frame brazing method that can prevent the occurrence of bridges (shoots) caused by the brazing material.
本発明は、リード列の両外側に余剰ろう材を吸
収するダミーリードを設け、ここに余剰ろう材を
吸収することを特徴とする。
The present invention is characterized in that dummy leads are provided on both outer sides of the lead row to absorb excess brazing material.
第５図に本発明によるリードフレームの実施例
を示す。リードフレーム１は、その外側に余剰ろ
う材吸収用の幅の広いリード１４，１５を備えて
いる。ろう材５の余剰部１２，１３はそれぞれ幅
の広いリード１４，１５に接するように保持さ
れ、ろう付温度にまで加熱される。第７図にろう
付の完了した状況を示す。余剰ろう吸収用リード
１４，１５の先端１８，１９には余剰のろう材１
２，１３が溶融付着しており、余剰ろう量がここ
に吸収されたために、従来技術ではブリツジの生
じた端子１６，１７にも正常にろう付される端子
７と同一量のろうが付着するためブリツジが発生
せず、正常なろう付が行なわれる。しかる後に切
断線２０，２１に添つてリードつなぎ部材２を切
断し、余剰ろう吸収用リード１４，１５を切り離
すことによつて、第９図に示すように全ての端子
４がブリツジすることなく正常にろう付されたリ
ード付きセラミツク基板が得られる。なお、余剰
ろう吸収用リード１４，１５は、リードフレーム
ろう付工程中での取り扱いミスによるリード１の
曲がり等の損傷防止のための保護としても働く。
FIG. 5 shows an embodiment of a lead frame according to the present invention. The lead frame 1 is provided with wide leads 14 and 15 on the outside thereof for absorbing excess brazing material. Excess portions 12 and 13 of the brazing material 5 are held in contact with wide leads 14 and 15, respectively, and heated to a brazing temperature. Figure 7 shows the state of completion of brazing. Excess brazing material 1 is placed on the tips 18 and 19 of the excess brazing absorbing leads 14 and 15.
2 and 13 are melted and adhered thereto, and the excess amount of solder is absorbed there. Therefore, in the prior art, the same amount of solder adheres to the terminals 16 and 17 where bridging occurred as to the normally soldered terminal 7. Therefore, no bridging occurs and normal brazing is performed. After that, by cutting the lead connecting member 2 along the cutting lines 20 and 21 and separating the excess solder absorbing leads 14 and 15, all the terminals 4 are normal without bridging as shown in FIG. A ceramic substrate with leads soldered to the ceramic substrate is obtained. Note that the excess solder absorbing leads 14 and 15 also serve as protection to prevent damage such as bending of the lead 1 due to handling errors during the lead frame brazing process.
本発明によれば、従来技術で発生していた余剰
ろう材によるブリツジの発生をなくすることが可
能であり、従来技術で余剰ろう量をできるだけ減
らすためにろう材５の長さを短くした場合に発生
する、ろう材とセラミツク基板とリードフレーム
相互間の位置あわせの難かしさを解消することが
可能となる。
According to the present invention, it is possible to eliminate the occurrence of bridging due to surplus solder metal that occurs in the conventional technology, and when the length of the solder metal 5 is shortened in order to reduce the amount of surplus solder material as much as possible in the conventional technology. This makes it possible to eliminate the difficulty in aligning the brazing material, ceramic substrate, and lead frame with each other, which occurs during the process.
第１図は従来技術によるリードフレーム及びそ
れをろう付する前のセラミツク基板及びろう材と
の保持関係を示す平面図、第２図は第１図の側面
図、第３図は従来技術によるリードフレームを使
用してろう付し終つた状態を示す平面図、第４図
は第３図の側面図、第５図は本発明の一実施例に
よるリードフレーム及びそれをろう付する前のセ
ラミツク基板及びろう材との保持関係を示す平面
図、第６図は第５図の側面図、第７図はリードフ
レームを使用してろう付し終つた状態を示す平面
図、第８図は第７図の側面図、第９図は余剰ろう
吸収用リードを除去した状態を示す平面図、第１
０図は第９図の側面図である。
符号の説明、１……リードフレーム、２……リ
ードのつなぎ部材、３……セラミツク基板、４…
…セラミツク基板の端子、５……ロウ材（リボン
又はワイヤ）、１４，１５……余剰ろう吸収用リ
ード。
Fig. 1 is a plan view showing a lead frame according to the prior art and its holding relationship with a ceramic substrate and brazing material before being brazed, Fig. 2 is a side view of Fig. 1, and Fig. 3 is a lead frame according to the prior art. 4 is a side view of FIG. 3, and FIG. 5 is a lead frame according to an embodiment of the present invention and a ceramic substrate before brazing it. 6 is a side view of FIG. 5, FIG. 7 is a plan view showing the state after brazing using a lead frame, and FIG. 8 is a side view of FIG. Fig. 9 is a side view, Fig. 9 is a plan view showing the state in which the excess solder absorption lead has been removed, and Fig.
Figure 0 is a side view of Figure 9. Explanation of symbols: 1... Lead frame, 2... Lead connecting member, 3... Ceramic substrate, 4...
... Ceramic board terminal, 5 ... Brazing material (ribbon or wire), 14, 15 ... Lead for absorbing excess solder.
Claims (1)
ームを接続する方法において、リード列の両外側
に、余剰ろう材を吸収するために本来接続に要す
るリード以外のリードを設け、ここに余剰ろう材
を吸収することを特徴とするリードフレームのろ
う付け方法。1 In a method of connecting a terminal row to be connected and a lead frame by brazing, leads other than the leads originally required for connection are provided on both outsides of the lead row in order to absorb excess brazing material, and the excess brazing material is placed here. A lead frame brazing method characterized by absorbing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1451583A JPS59141256A (en) | 1983-02-02 | 1983-02-02 | Brazing method of lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1451583A JPS59141256A (en) | 1983-02-02 | 1983-02-02 | Brazing method of lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59141256A JPS59141256A (en) | 1984-08-13 |
| JPS6256665B2 true JPS6256665B2 (en) | 1987-11-26 |
Family
ID=11863220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1451583A Granted JPS59141256A (en) | 1983-02-02 | 1983-02-02 | Brazing method of lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59141256A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0789577B2 (en) * | 1986-07-14 | 1995-09-27 | 京セラ株式会社 | Manufacturing method of package for storing semiconductor devices |
| JPH01121945U (en) * | 1988-02-12 | 1989-08-18 | ||
| JPH0241452U (en) * | 1988-09-09 | 1990-03-22 | ||
| US5358169A (en) * | 1994-01-14 | 1994-10-25 | Caddock Electronics, Inc. | Method of soldering leads to electrical components |
-
1983
- 1983-02-02 JP JP1451583A patent/JPS59141256A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59141256A (en) | 1984-08-13 |
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