JPS6255745B2 - - Google Patents

Info

Publication number
JPS6255745B2
JPS6255745B2 JP55109041A JP10904180A JPS6255745B2 JP S6255745 B2 JPS6255745 B2 JP S6255745B2 JP 55109041 A JP55109041 A JP 55109041A JP 10904180 A JP10904180 A JP 10904180A JP S6255745 B2 JPS6255745 B2 JP S6255745B2
Authority
JP
Japan
Prior art keywords
output
signal
pulse
input
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55109041A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5733850A (en
Inventor
Kenzo Oono
Tsutomu Asabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP10904180A priority Critical patent/JPS5733850A/ja
Publication of JPS5733850A publication Critical patent/JPS5733850A/ja
Publication of JPS6255745B2 publication Critical patent/JPS6255745B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP10904180A 1980-08-07 1980-08-07 Non-return-to-zero code receiving device Granted JPS5733850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10904180A JPS5733850A (en) 1980-08-07 1980-08-07 Non-return-to-zero code receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10904180A JPS5733850A (en) 1980-08-07 1980-08-07 Non-return-to-zero code receiving device

Publications (2)

Publication Number Publication Date
JPS5733850A JPS5733850A (en) 1982-02-24
JPS6255745B2 true JPS6255745B2 (enrdf_load_stackoverflow) 1987-11-20

Family

ID=14500100

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10904180A Granted JPS5733850A (en) 1980-08-07 1980-08-07 Non-return-to-zero code receiving device

Country Status (1)

Country Link
JP (1) JPS5733850A (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4509121A (en) * 1982-09-30 1985-04-02 Honeywell Information Systems Inc. Apparatus for synchronizing a stream of data bits received over a single coaxial conductor
JPS6170829A (ja) * 1984-09-14 1986-04-11 Riyuudenshiya:Kk 同期用補正回路を有する受信装置
JPH0630488B2 (ja) * 1985-05-31 1994-04-20 日産自動車株式会社 デ−タ伝送装置
JP4481329B2 (ja) * 2007-12-19 2010-06-16 ローランド株式会社 音声データ送受信装置

Also Published As

Publication number Publication date
JPS5733850A (en) 1982-02-24

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