JPS6254476A - Lateral field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a good high-frequency gain characteristic by providing a gate electrode extending in the extension direction of the trench, and providing a source electrode and a drain electrode on the semiconductor layer at both positions sandwiching the trench therebetween. CONSTITUTION:On the inner surfaces 13a and 13b of a trench 3 of the source electrode 6 and drain electrode 7 sides, insulating films 21 and 22 of SiO2 extending to the bottom surface 13c of the trench 3 are formed respectively, the sides 14a, 14b of the gate electrode 4 on the source electrode 6 and drain electrode 7 sides are continuously joined with the insulating films 21, 22. Since the gate electrode 4 is provided so as to form a Schottky junction 5 between the semiconductor layer 2, the current to be supplied to the load can be turned off by a low threshold value of the control voltage to be applied across the source electrode 6 and the gate electrode 4 as in the case of a lateral field effect transistor. With this, a good high-frequency gain characteristic can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a lateral field effect transistor and its \J method.

BACKGROUND OF THE INVENTION Conventionally, a lateral field effect transistor has been proposed which has the following configuration with reference to FIG.

For example, on a semi-insulating substrate or a semi-insulating layer (hereinafter simply referred to as a semi-insulating substrate for simplicity) 1 made of, for example, GaAs, a semiconductor layer 2 made of, for example, GaAs and having n-type or ρ-type is formed. is formed.

A groove 13 is formed in the semiconductor layer 2 on its upper surface side, extending in the width direction across the width of the semiconductor layer 2.

Further, on the semiconductor layer 2, at the bottom surface 13cf of 1143, a gate electrode 4 extending in the extending direction of the ::iS 3 over the entire area of the semiconductor layer 2 forms a Schottky junction 5 between the semiconductor layer 2 and the semiconductor layer 2. It is fled to form a . In this case, opposite side surfaces 14a and 1/l of the gate electrode 4
b faces opposite side surfaces 13a and 13b of the groove 3 with gaps 8a and 8b interposed therebetween.

Further, a source electrode 6 and a drain electrode 7 are formed on the semiconductor layer 2 at both positions sandwiching ) δ3 from A to lumi (
=j has been done.

The above is an example of the configuration of a conventionally proposed lateral field effect transistor.

According to the lateral field effect transistor having such a configuration, Li charges (
By applying a control voltage between the source electrode 6 and the gate electrode 4 with a required power supply connected through
It is possible to control the spread of the depletion layer that spreads to the side.

Therefore, by controlling the control voltage applied between the source electrode 8i6 and the gate electrode 4, a function as a field effect transistor is obtained in which the current supplied to the load can be controlled on and off.

Further, in the case of the conventional lateral field effect transistor shown in FIG. 5, the semiconductor layer 2 is formed with a gate electrode 4, and the gate electrode 4 is formed on the semiconductor layer 2. Since the Schottky junction 5 is formed on the bottom surface 8 of the semiconductor layer 2 with the semiconductor layer 2, the thickness of the region under the Schottky junction 5 of the semiconductor layer 2 is smaller than that of other regions. Compared to R'J. Therefore, the current supplied to the load can be turned off at the low threshold value of the control voltage described above.

Furthermore, a lateral field effect transistor 6 having a 17i configuration has been proposed as described below with reference to FIG.

In Fig. 6, parts corresponding to those in Fig. 5 are designated with the same reference numerals.
A detailed explanation will be omitted.

The conventional lateral field effect transistor shown in FIG.
In the conventional lateral field effect transistor described above in the figure, its gate electrode 4 is connected to the semiconductor layer 2 with a full 3 bottom surface 13.
Instead of forming the Schottky junction 5 on the cliff conductor layer 2, a semiconductor region 8 having a conductivity type opposite to that of the semiconductor layer 2 is provided below the gate electrode 4 on the cliff conductor layer 2.
The structure is similar to that of the conventional lateral field effect transistor described above with reference to FIG. has.

The above is the structure of another example of the conventionally proposed lateral field effect transistor.

According to the lateral field effect transistor having such a configuration, it has a configuration similar to that described above in FIG. By applying a voltage, it is possible to control the expansion of the depletion layer extending from the pn junction 9 between the semiconductor layer 2 and the conductor region 8 toward the semi-insulating substrate 1, so a redundant explanation will be omitted. However, does it function as a field effect transistor in the same way as the conventional lateral field effect transistor described above in FIG. 9.

In addition, in the case of a conventional lateral field effect transistor not shown in FIG. 1'1
A body chain WJ, 8 is formed in the semiconductor layer 2 in the region below the groove 3 from the full bottom surface 13c so as to form a pn junction 9 with the semiconductor VJ2. Since the gate voltage VM4 is ohmically attached to the semiconductor region 8, the thickness of the region below the pn junction 9 of the semiconductor layer 2 is thinner than the other regions. Therefore, as in the case of the conventional lateral field effect transistor described above in FIG.
It has the feature that the voltage is low rJjJ (the current supplied to the load by iri can be A).

Invention solved J: It'll be intermittent in Figure 5 -
In the case of the conventional lateral field effect transistor described above, the gate electrode 4 is actually formed on the semiconductor layer 2 using a mask layer and then using another mask layer. , the length of the electrode 4 (the length in the direction connecting the source electrode 6 and the drain electrode 7) is set to a certain limit to make it sufficiently small.

For this reason, there was a certain limit to covering the material of the lateral field effect transistor at the junctions 1 to 5 by -1 minute.

Furthermore, in the case of the conventional lateral field effect transistor described above in FIG. Its long source from being formed considering? There was a certain limit to making [the length in the direction connecting the two poles 6 and the drain electrode 7] sufficiently small.

For this reason, there is a certain limit to making the distance from the source electrode 6 to the region under the Schottky junction 5 of the semiconductor layer 2 sufficiently small. There is a certain limit to making the transconductance of a lateral field effect transistor sufficiently small, and therefore there is a certain limit to making the transconductance of a lateral field effect transistor sufficiently large.

J, in the case of the conventional lateral field effect l-run lister described above in FIG.
It had the disadvantage of not being able to be evaluated well (as a B-type).

In addition, in the case of the conventional lateral field effect transistor described above in FIG. Furthermore, since the gate electrode 4 is formed using a mask layer after the semiconductor region 8 is formed, the length of the semiconductor layer II!!8 (in the direction connecting the source electrode 6 and the drain electrode 7) is There was a certain limit to making the length) sufficiently small.

For this reason, the gate capacitance of the lateral field effect transistor with J at the pn junction 9 must be set to a certain limit to make it sufficient, as in the case of the conventional lateral field effect transistor shown in Figure 5 (above). I had it.

Furthermore, in the case of the conventional lateral field effect transistor described above in FIG. Therefore, there is a certain limit to making the length (the length in the /j direction connecting the source electrode 6 and drain electrode 7) sufficient.

For this reason, there is a certain limit to making the distance from the source electrode 6 to the region under the pn junction 9 of the \-conductor layer 2 a sufficient factor, and therefore, as shown in FIG. As in the case of field effect transistors, there is a certain limit to making the source-gate resistance of a lateral field effect transistor a sufficient ratio. As in the case, there is a certain limit 1α for making the phase n conductance of a lateral field effect transistor sufficiently large.

Therefore, in the conventional case shown in FIG. 6, as well as in the case of the conventional lateral field effect transistor described above in FIG. I was right about the shortcomings.

By means of overcoming the problem, the present invention seeks to propose a novel lateral field effect transistor and its manufacturing method, which does not have the drawbacks of the conventional lateral field effect transistors mentioned above.

Lateral field effect transistor according to the first invention of the present application (
As in the case of the conventional lateral field effect transistor described above with reference to FIGS. 5 and 6, a p-type or p-type semiconductor layer is formed on a semi-insulating substrate or a semi-insulating layer, and the semiconductor A groove is formed in the layer extending in the width direction thereof,
On the semiconductor layer, on the bottom surface of the groove, a goo electrode extending in the extending direction of the groove is attached, and on the semiconductor layer, a source electrode and a drain electrode are attached at both positions across the groove. It has a structure in which electrodes are attached.

However, in the lateral field effect transistor according to the first invention of the present application, in the above-described configuration, first and second electrodes are provided on the inner surface of the groove on the side of the source electrode and the drain electrode, and extend to the bottom surface of the groove. The second insulating film is formed, and the side surfaces of the -V goat electrode on the source electrode and drain electrode sides are connected to the first and second insulating films, respectively.

In addition, the method for manufacturing a Herran Lister according to the second invention of the present application includes a step of forming a p-type or p-type semiconductor layer on a semi-insulating substrate or a semi-insulating layer; A step of forming a mask layer having a window extending 111 m in the width direction on the semiconductor layer, and an etching process on the semiconductor layer using the mask layer as a mask, forming a first and second insulating film extending up to the bottom surface of the groove on opposing inner surfaces of the groove; , a step of forming an electrode connected to the first and second insulating films, and forming a source electrode and a drain electrode on both sides of the groove on the semiconductor layer. The transverse field effect according to the first invention of the present application]
Lively.

Effects and Effects According to the lateral field effect transistor according to the first invention of the present application, it is formed in the semiconductor layer in the structure of the conventional lateral field effect transistor described above in FIGS. 5 and 6. First and second insulating films extending up to the bottom surface of the groove are formed on the inner surface of the source electrode and drain electrode side of the groove, and It has the same structure as the conventional lateral field effect transistor described above with reference to FIGS. 5 and 6, except that the side surface on the electrode side is connected to the first and second insulating films, respectively.

Therefore, as in the case of the conventional lateral field effect transistor shown in FIG. 5 and FIG. By applying a control voltage between the gate electrodes, a function as a field effect transistor is obtained in which the current supplied to the load can be controlled to be turned on or off.

Further, according to the lateral field effect transistor according to the first invention of the present application, a groove is formed in the semiconductor layer, and a gate electrode is attached to the semiconductor layer on the bottom surface of the groove. As with the conventional lateral field effect transistor described above in FIGS. 5 and 6, the low threshold of the control voltage described above allows the current supplied to the load to be turned off.

Furthermore, according to the lateral field effect transistor according to the first invention of the present application, the gate electrode is completely formed in the semiconductor layer, as is clear from the above-mentioned method for manufacturing the lateral field effect transistor according to the second invention of the present application. It is formed after
Since the gate electrode is formed to be connected to the seventh and second insulating films previously formed on the opposing inner surfaces of the groove, the length of the groove and the gate electrode (source electrode and drain ff The length in the direction in which the electrodes are connected can be made much shorter than in the case of the conventional lateral field effect transistor described above with reference to FIGS. 5 and 6. Also,
Since the length of the groove can be sufficiently shortened, the distance from the source electrode to the region under the gate electrode of the semiconductor layer can be reduced compared to the case of the conventional lateral field effect transistor described above in FIGS. 5 and 6. can be significantly shortened,
Therefore, the source-gate resistance of the lateral field effect transistor can be made sufficiently smaller than that of the conventional lateral field effect transistor described above with reference to FIGS. 5 and 6.

Therefore, the gate capacitance a of the lateral field effect transistor can be made much smaller than that of the conventional lateral field effect transistor described above in FIGS. 5 and 6. , the mutual conductance of the lateral field effect transistor can be made much lower than that of the conventional lateral field effect transistor described above in FIGS. 5 and 6.

Therefore, according to the lateral field effect transistor according to the first invention of the present application, compared to the conventional lateral field effect transistor described above in FIGS. 5 and 6, a much better high frequency gain can be achieved. Accelerate 1q characteristics.

Further, according to the method for manufacturing a lateral field effect transistor according to the second invention of the present application, a lateral field effect transistor having the above-mentioned excellent characteristics can be easily manufactured.

First, a first embodiment of a lateral field effect transistor according to the first invention of the present application will be described with reference to FIG.

In Figure 1, parts corresponding to Figure 5 are marked with the same -)
, and detailed explanation will be omitted.

The lateral field effect transistor according to the first invention of the present application, which is not shown in FIG. 1, has the structure of the conventional lateral field effect transistor described above in FIG.
and on the inner surfaces 13a and 13b on the drain electrode 7 side,
For example, 5102, which extends above the bottom surface 13C of full 3.
Insulating films 21 and 22 consisting of It has the same configuration as the conventional lateral field effect transistor described above with reference to FIG.

The above is the configuration of the first embodiment of the lateral field effect transistor according to the first invention of the present application.

A lateral field effect transistor having such a configuration has the same configuration as the conventional lateral field effect transistor described above in FIG. 5, except for the matters mentioned above.

Therefore, although a detailed explanation is omitted7, similar to the case of the conventional lateral field effect transistor described above in FIG.
The function as an h-field effect Song transistor can be obtained.

Also, the first part of the present application shown in FIG. According to the lateral field effect transistor according to the r1th invention, the semiconductor layer 2 is formed with the full 3 portions, and the bottom surface 13c of the full 3 portions is formed on the semiconductor layer 2.
Since the gate electrode 4 is attached so as to form a Schottky junction 5 with the semiconductor layer 2, the source electrode 6 is attached as in the case of the lateral field effect transistor described above in FIG. 5C. and the force applied between the gate electrodes 4
A low threshold of Ir allows the current supplied to the load to be turned off.

Further, according to the first invention of the present application shown in FIG. 1, the first embodiment of the method for manufacturing a lateral field effect transistor according to the second invention of the present application, which will be described later with reference to FIG. As is clear from 15II, the gate electrode 4 is formed after the semiconductor layer 2 is formed using the mask layer 32, but the gate electrode 4IA4 is formed without using the other mask 8). The length of the gate electrode KA/l (source electrode 6 and drain electrode 7 The length in the direction connecting the two can be made much shorter than that of the conventional lateral field effect transistor described above in FIG.

Therefore, the gate capacitance of the lateral field effect transistor connected to the Schottky junction 5 can be made much smaller than that of the conventional lateral field effect transistor described above in FIG.

In addition, in the case of the lateral field effect transistor according to the first invention of the present application shown in FIG. 1, for the reasons mentioned above, the length of the third aspect is shown in FIG. 5 compared to the case of the conventional lateral field effect transistor described above. , can be significantly shortened, so
The distance from the source electrode 6 to the region of the semiconductor layer 2 under the gate electrode 4, and thus under the Schottky junction 5, is compared to that of the conventional lateral field effect transistor described above in FIG.
Therefore, the source-gate 11 resistance of the lateral field effect transistor can be made sufficiently smaller than that of the conventional lateral field effect transistor described above in FIG. This means that the thickness of the insulating films 21 and 22 can be made sufficiently small as desired, and the length of the gate electrode 144 can be reduced accordingly compared to the conventional lateral field effect 1- This is even more so since it can be made much smaller than in the case of a transistor, and still be good.

Therefore, the phase U] inductance of the lateral field effect 1-transistor can be significantly increased η compared to the case of the conventional lateral field-effect 1-transistor described above in FIG.

Therefore, according to the lateral field effect 1-transistor according to the first invention of the present application shown in FIG. exhibits.

Example 2 of a 71-color lateral 1′ effect 1 transistor according to the invention No. 1 of the present application Next, with reference to FIG. Let's give an example.

In FIG. 2, parts corresponding to those in FIGS. 1 and 6 are designated by the same reference numerals, and detailed description thereof will be omitted.

The second embodiment of the lateral field effect transistor according to the first invention of the present application shown in FIG. The gate electrode 4 is located on the bottom surface 13 of full 3
Instead of forming a Schottky junction 5 on the semiconductor FM2, a J5 is attached below the gate electrode 4, as in the case of the conventional lateral field effect transistor described in FIG. A semiconductor region 8 having a conductivity type opposite to that of the semiconductor layer 2 forms a pn junction 9 with the semiconductor layer 2.
is formed so as to form a lateral electric field according to the first invention of the present application described above in FIG. It has the same configuration as the first embodiment of the effect transistor.

The above is the configuration of the second embodiment of the lateral field effect transistor according to the first invention of the present application.

According to the lateral field effect transistor having such a configuration, it has the same configuration as the lateral field effect transistor according to the first invention of the present application described above in FIG. 2, except for the above-mentioned matters. Although the explanation is omitted, the function as a lateral field effect transistor is blue, as in the case of the lateral field effect transistor according to the first invention of the present application described above in FIG. A low threshold of the stop voltage applied during t4i4 allows the current supplied to the load to be turned off.

Further, according to the first invention of the present application shown in FIG.
As is clear from the second embodiment of the method for manufacturing a lateral field effect transistor according to the second invention of the present application, which will be described later in the figure, the case of the lateral field effect transistor according to the first invention of the present application described above in FIG. Similarly, Goo 1-electrode 4 is
The insulating films 21 and 22 are formed in advance on the opposite inner surfaces 13a and 13b without using a mask layer. Since the r-conductor region 8 is formed using the insulating films 21 and 22 as a mask before forming the gate electrode 4, the length of the semiconductor layer 8 is set as that of the conventional lateral field effect transistor described above in FIG. It can be much shorter than that.

Therefore, the gate size of the lateral field effect transistor using the pn junction 9 can be made much smaller than that of the conventional lateral field effect transistor described above in FIG.

Furthermore, in the case of the lateral field effect transistor according to the first invention of the present application shown in FIG. 2, for the reasons mentioned above, the length of the groove 3 is made different from that of the conventional lateral field effect transistor shown in FIG. , can be significantly shortened, so
To make the distance from the source electrode 6 to the region of the semiconductor layer 2 under the gate electrode 4, and therefore under the pn junction 9, much shorter than in the case of the conventional lateral field effect transistor described above in FIG. Therefore, the resistance between the source and gate electrodes of the lateral field effect transistor can be made sufficiently larger than that of the conventional lateral field effect transistor described above in FIG. This means that the insulating films 21 and 22
The thickness can be adjusted to a sufficient amount as desired, and by this amount,
This is even more so since the length of the semiconductor region 8 can be increased while being significantly smaller than that of the conventional lateral field effect transistor described in FIG.

Therefore, the mutual conductance of the lateral field effect transistor can be made much smaller than that of the conventional lateral field effect transistor described above in FIG.

Therefore, the lateral field effect transistor according to the first invention of the present application shown in FIG. 2 exhibits significantly better high frequency gain characteristics than the conventional lateral field effect transistor described above in FIG.

Next, with reference to FIG. 3, an embodiment of the method for manufacturing a lateral field effect transistor according to the second invention of the present application will be explained. Let us describe the case of manufacturing a lateral field effect transistor according to the first invention.

First, a semi-insulating substrate 1 similar to that described above in FIG. 1 is prepared in advance (FIG. 3A).

Then, on the semi-insulating substrate 1, a semiconductor layer 2 similar to that described above in FIG. 1 is formed by various methods known per se (FIG. 3B). Then, a mask layer 32, made of silicon nitride, for example, having windows 31 corresponding to the grooves 3, similar to those described above in FIG. (Fig. 3C).

Next, using the mask w7J32 for the semiconductor layer 2 as a mask, the semiconductor layer 2 is etched by a known etching process, such as a reactive ion etching process, as shown in FIG.
A groove 3 similar to that made in L is formed (Fig. 3D).

Next, an insulating layer 33 extending continuously on the mask layer 32 and on the inner surface of the trench 3, which will later become the insulating films 21 and 22 described above in FIG. The insulating layer 33 is formed by a CVD method (FIG. 3E), and then the insulating layer 33 is etched by a known etching process, such as a highly anisotropic reactive ion etching process. , extends onto the inner surfaces 138 and 13b of the mask layer 3, extends above the bottom surface 13c of the mask layer 32, and extends to the opposing inner surfaces of the windows 31 of the mask layer 32.
2 are formed with insulating films 21 and 22 similar to those described above in FIG. 1, but not extending (FIG. 3F).

Next, the grooves 13 on the mask layer 32 and the insulating films 21 and 22 are
On the surface opposite to the a and 13b sides, a conductive layer 34, which is continuously extended so as to bury the groove 13 and will become the gate voltage l4i4 described above in FIG. In order to form a Schottky joint 5 similar to that described above in FIG.
The electrically conductive layer 3/I may be formed by, for example, a vapor deposition method or a sputtering method (FIG. 3G), and then be applied to the conductive layer 3/I by a method known per se, for example by applying ions to the semi-insulating substrate 1. The diagonal ion milling method is used to mill the conductive layer 34 by irradiating the conductive layer 34 from an oblique direction while rotating the conductive layer 34. A gate electrode 4 similar to that shown in FIG.
.

Next, on both sides of the groove 3 on the semiconductor layer 2,
Source electrodes 6 and 7, respectively, similar to those described above in FIG.
is not attached by a method known per se (FIG. 3I).

In the manner described above, the lateral field effect transistor according to the first invention of the present application described above with reference to FIG. 1 is manufactured.

The above is the first embodiment of the method for manufacturing a lateral field effect transistor according to the second invention of the present application.

According to the method for manufacturing a lateral field effect transistor according to the first invention of the present application, as is clear from the above, a lateral field effect transistor having the excellent features described above in FIG. 1 can be easily manufactured. be able to.

Next, a second embodiment of the lateral field effect transistor according to the second invention of the present application is manufactured, and a second embodiment of the lateral field effect transistor according to the first invention of the present application described above in FIG. 2 is manufactured. Let me explain the case.

First, although not shown, a semi-insulating substrate 1 similar to that described above in FIG. 2 is prepared in advance in the same manner as described above in FIG. 3A,
Then, on the semi-insulating substrate 1, a semiconductor layer 2 similar to that described above with reference to FIG. 2 is formed by a method similar to that described above with reference to FIG. 3B.

Next, although not shown in the same way, on the semiconductor layer 2, as shown in FIG.
A mask layer 32 similar to that described above in FIG. formed by

Next, although not shown, an insulating layer 33 similar to that described above in FIG. 3E is formed by a similar method, and then an insulating layer 33 similar to that described above in FIG. membrane 2
1 and 22 are formed by a method similar to that described above in FIG. 3F.

Next, the semiconductor FrI2 is introduced into the semiconductor layer 2 as described above in FIG. Form a semiconductor region 8 similar to (
Figure 6A).

Next, the grooves 13 on the mask layer 32 and the insulating films 21 and 22 are
A groove 13 is continuously formed on the surface opposite to the a and 13b sides.
The conductive layer 34, which is later extended to the gate electrode 4 described above in FIG. jt1f+! 6B), and then conductive Ff! From J3/l, a gate electrode 4 similar to that described above in FIG. 2 is formed by a method similar to that described above in FIG. 3, and then the mask layer 32 is removed (FIG. 6C).

Next, source electrodes 6 and 7 similar to those described above in FIG. 2 are formed on the semiconductor layer 2 by the same method as described above in FIG. 3 (FIG. 6D). , the lateral field effect transistor according to the first invention of the present application as described above in FIG. 2 is manufactured.

The above is the second embodiment of the method for manufacturing a lateral field effect transistor according to the second invention of the present application.

As described above, according to the method for manufacturing a lateral field effect transistor according to the first invention of the present application, a lateral field effect transistor having the excellent features described above in FIG. 2 can be easily manufactured. be able to.

In the above description, only a few embodiments have been described for the lateral field effect transistor and its manufacturing method according to the first invention of the present application, and various modifications and variations may be made without departing from the spirit of the present invention. changes could be made.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a lateral field effect transistor according to the first invention of the present application. FIG. 2 is a cross-sectional view showing a second embodiment of the lateral field effect transistor according to the first invention of the present application. FIG. 3 shows the horizontal field effect 1- according to the second invention of the present application.
FIG. 3 is a line cross-sectional view of successive steps without showing the first embodiment of the transistor manufacturing method. FIG. 4 is a line sectional view showing the sequential steps of a second embodiment of the method for manufacturing a lateral field effect transistor according to the second invention of the present application. FIG. 5 is a dimensional cross-sectional view of an example of a conventional lateral field effect transistor. FIG. 6 is a schematic cross-sectional view of another example of a conventional horizontal field effect transistor. 1... Semi-insulating substrate or semi-insulating layer 2
......Semiconductor layer 3...Full 4...Gate electrode 5...Schottky junction 6... ......Source electrode 7...Drain electrode 8...Semiconductor region 9...Pn junction 31... ...Window 32...Mask layer 33...Insulating layer 34...Conductive layer Fig. 2 Fig. 6 Figure 3 Figure 8 Figure 8 Figure 8 Figure 4 Figure 4

Claims (1)

[Claims] 1. On a semi-insulating substrate or semi-insulating layer, n-type or p-type
a groove extending in the width direction of the semiconductor layer, a gate extending in the direction of extension of the groove on the bottom surface of the groove; In a lateral field effect transistor in which an electrode is attached, and a source electrode and a drain electrode are attached on the semiconductor layer at both positions across the groove, on the inner surface of the groove on the source electrode and drain electrode side. The first groove extends above the bottom surface of the groove.
and a second insulating film are formed, and a side surface of the gate electrode on the side of the source electrode and the drain electrode is connected to the first and second insulating films, respectively. 2. The lateral field effect transistor according to claim 1, wherein the gate electrode is attached to the semiconductor layer so as to form a Schottky junction therebetween. transistor. 3. In the lateral field effect transistor according to claim 1, a semiconductor region having a conductivity type opposite to that of the semiconductor layer is formed in the semiconductor layer below the gate electrode, and the gate electrode is ohmically attached to the semiconductor region. 4. On the semi-insulating substrate or semi-insulating layer, n-type or p-type
a step of forming a semiconductor layer having a mold; a step of forming a mask layer having a window extending in the width direction of the semiconductor layer; and an etching process for the semiconductor layer using the mask layer as a mask. Therefore, the step of forming a groove extending in the width direction of the semiconductor layer, and forming first and second grooves extending up to the bottom surface of the groove on opposing inner surfaces of the groove. a step of forming an insulating film; a step of forming a gate electrode connected to the first and second insulating films in the trench; and a step of forming a gate electrode on the semiconductor layer at both positions across the trench. A method for manufacturing a lateral field effect transistor, comprising the step of forming a source electrode and a drain electrode. 4. The lateral field effect transistor according to claim 3, wherein the gate electrode is formed such that a Schottky junction is formed between the gate electrode and the semiconductor layer at the bottom of the groove. Method for manufacturing lateral field effect transistors. 5. In the lateral field effect transistor according to claim 3, after forming the first and second insulating films and before forming the gate electrode, a portion of the semiconductor layer under the gate electrode is provided. . A method for manufacturing a lateral field effect transistor, comprising forming a semiconductor region having a conductivity type opposite to that of the semiconductor layer.