JPS59222970A - P-i-n diode pellet - Google Patents

P-i-n diode pellet

Info

Publication number
JPS59222970A
JPS59222970A JP9712883A JP9712883A JPS59222970A JP S59222970 A JPS59222970 A JP S59222970A JP 9712883 A JP9712883 A JP 9712883A JP 9712883 A JP9712883 A JP 9712883A JP S59222970 A JPS59222970 A JP S59222970A
Authority
JP
Japan
Prior art keywords
layer
electrode
approximately
main surface
joining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9712883A
Other languages
Japanese (ja)
Inventor
Kaoru Nakagawa
中川　薫
Noboru Yamamoto
昇 山本
Nobutaka Matsuoka
信孝 松岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP9712883A priority Critical patent/JPS59222970A/en
Publication of JPS59222970A publication Critical patent/JPS59222970A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain a P-I-N diode pellet having small capacitance and low-operation resistance by forming an approximately mushroom-shaped projecting electrode to a reverse conduction type impurity layer plane-combining in parallel with a main surface and reducing the diameter of the joining of the electrode. CONSTITUTION:A P<+> layer 13 and an SiO2 film 14 form approximately the same plane in their main surfaces, the P<+> layer 13 extends to the N<->VG layer 11 side in approximately 1.0mum diffusion depth from the main surface, and the SiO2 film 14 surrounding the P<+> layer 13 extends to the N<->VG layer 11 side in approximately 1.2mum extension depth from the main surface. A surface electrode 15 is formed on the P<+> layer 13 while an annular region intruding by approximately 20mum from the periphery of the layer 13 is exposed. Approximately a mushroom- shaped projecting electrode 16 is formed on the surface electrode 15 so as to coat the upper section of the SiO2 film 14. The projecting electrode 16 is shaped by the quality of a material such as Ag, and a back electrode 17 consisting of AuGe-Au is formed on the exposed back side of an N<+> semiconductor substrate 12. Accordingly, the capacitance of the peripheral section of the joining of a P-I- N diode pellet 20 can be brought to zero, and the diameter of its joining can be reduced efficiently.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、　ＰＩＮダイオード被レフレットする。[Detailed description of the invention] [Technical field of invention] The present invention reflects a PIN diode.

〔発明の技術的背景〕[Technical background of the invention]

周波数バンド切換え用のＰＩＮダイオードペレットは、
例えば第１図に示す構造を有している。The PIN diode pellet for frequency band switching is
For example, it has the structure shown in FIG.

図中Ｉは、Ｎ＋半導体基板２上に形成されたＮ−ＶＧ層
である。Ｎ−ＶＧ層１の所定領域には、Ｐ型不純物で形
成されたＰ＋層３が形成されている。I in the figure is an N-VG layer formed on the N+ semiconductor substrate 2. A P+ layer 3 made of P-type impurities is formed in a predetermined region of the N-VG layer 1.

１層３及びＮ”−ＶＧ層１上には、所定の膜厚のＳＩＯ
□−膜４が形成されている。５ｉｎ２−膜４には、１層
３に通じる窓５が開口されている。窓５内には、１層３
の露出表面を覆う表面電極６が形成されている。Ｓ　１
０２−膜４上に“は、表面電極６を介してＰ＋層３に接
続する突起電極７が形成されている。Ｎ＋半導体基板１
の露出した裏面側には、裏面電極８が形成されている。1 layer 3 and N''-VG layer 1, SIO of a predetermined thickness is formed.
□-Membrane 4 is formed. A window 5 communicating with the first layer 3 is opened in the 5in2-membrane 4 . Inside window 5, 1 layer 3
A surface electrode 6 is formed to cover the exposed surface of. S1
02- A protruding electrode 7 connected to the P+ layer 3 via the surface electrode 6 is formed on the film 4.N+ semiconductor substrate 1
A back electrode 8 is formed on the exposed back side.

而して、突起電極７は、Ｐ＋層３とＮ−ＶＣ層Ｉとで形
成された接合周辺部よりも太きく形成されている。Thus, the protruding electrode 7 is formed to be thicker than the peripheral part of the junction formed between the P+ layer 3 and the N-VC layer I.

〔背景技術の問題点〕[Problems with background technology]

上述のように構成されたＰＩＮダイオード波レッしｌＯ
は、次式（１）で示される動作抵抗（ｒＦ）を有してい
る。The PIN diode waveform configured as described above
has an operating resistance (rF) expressed by the following equation (1).

Ｗ”　　１　　　　　（、。W”　　　　　　　　(,.

Ｆ１ａ　Ｉτ ここで、Ｗ　：　Ｎ”−ＶＧ層１０幅 μ：電子・ホール平均移動度 Ｉ：バイアス電流 τ：電子・ホールライフタイム （ＩＦ、ＥＥ、ＴＲＡＮＳＡＣＴＩＯＮＳ　ＯＮ　ＥＬ
ＥＣＴＲＯＮ　ＤＥＶＩＣＥ８１９６４　、　Ｆｅｂ参
照　Ｐ５４〜）而して、ＰＩＮダイオードペレット丈１
の低素子容量（ＣＴ）を達成しようとすると次の問題が
ある。F1a Iτ Where, W: N”-VG layer 10 width μ: Average electron/hole mobility I: Bias current τ: Electron/hole lifetime (IF, EE, TRANSACTIONS ON EL
ECTRON DEVICE81964, Feb p.54~) Then, PIN diode pellet length 1
When trying to achieve a low element capacitance (CT) of 1, the following problem arises.

■　接合径を単に小さくして行くと、接合周辺部は接合
深さくＸｊ）を半径とする曲面を持ち、この接合周辺部
の接合容量（Ｃｐｅｒｉ）が接合全体容量（Ｃρに占め
る割合が大きくなる。■ If the junction diameter is simply made smaller, the periphery of the junction will have a curved surface whose radius is the junction depth .

■　接合径を単に小さくして行くと、接合周辺部のもれ
電流と動作抵抗通路が犬となる。また、接合周辺部電流
（Ｉｐｅｒｉ）がバイアス電流（丁）に占める割合が大
きくなる。その結果、動作抵抗が非常に大きくなる。■ If the junction diameter is simply made smaller, the leakage current and operating resistance path around the junction will become smaller. Furthermore, the ratio of the junction peripheral current (Iperi) to the bias current (Iperi) increases. As a result, the operating resistance becomes very large.

〔発明の目的〕 本発明は、小容量で低動作抵抗のＰＩＮダイオードペレ
ッＩｆ提供することをその目的とするものである。[Object of the Invention] An object of the present invention is to provide a PIN diode pellet If with a small capacity and low operating resistance.

〔発明の概要〕[Summary of the invention]

本発明は、雌きの千秋の突起電極を設けてその接合径を
小さくしたことにより、小容量でしかも低動作抵抗を有
するＰＩＮダイオード被レッドである。The present invention is a PIN diode that has a small capacity and low operating resistance by providing a female chiaki protruding electrode and reducing its junction diameter.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.

第２図は、本発明の一実施例の断面図である。FIG. 2 is a cross-sectional view of one embodiment of the present invention.

図中１１は、例えばＮ＋半導体基板１２上に形成されｆ
ＣＮ−半導体層からなるＮ−ＶＧ層である。Ｎ−ＶＧ層
１１の略中央部には、その主面から約１０μｍの拡散深
さで、これと逆導電型の不純物層からなるＰ＋層１３が
形成されている。ｒ層Ｉ３は、絶縁膜である。In the figure, 11 is formed on an N+ semiconductor substrate 12, for example.
This is an N-VG layer made of a CN-semiconductor layer. At approximately the center of the N-VG layer 11, a P+ layer 13 made of an impurity layer of the opposite conductivity type is formed at a diffusion depth of approximately 10 μm from the main surface thereof. The r layer I3 is an insulating film.

−例えばＳｉＯ□膜１４で囲まれている、Ｓ　ｉＯ２膜
１４は、Ｐ＋層１３の底部より約０．２μｍ深くＮ””
ＶＧ層１１内に延出している。つまり、Ｐ＋層１３とＳ
　ｉＯ２膜１４は、その主面でほぼ同一平面を形成し、
Ｐ＋層１３はこの主面から約１．０μｍの拡散深さでＮ
−ＶＧ層１１側に延出し、Ｐ　層１３’を囲ム５ｉＯ７
膜１４はこの主面から約１．２μｍ＋７）延出深さでＮ
ＶＧＩ？！１１１１１に延出している。Ｐ＋Ｒ１３上に
は、その周囲から約２０μｍ入り込んだ現状の領域を露
出するようにして表面電極１５が形成されている。表面
電極１５は、　ＡｕＧａ等で形成されており、その肉厚
は約３０００Ｘに設定されている。表面電極１５上には
、ＳｉＯ２膜１４膜上４′（ｉ−覆うようにして略きの
千秋の突起電極Ｉ６が形成されている。突起電極Ｉ６は
、Ａｇ等の材質で形成されている。Ｎ＋半導体基板Ｉ２
の露出した裏面側には、厚さ約３μｍのＡｕＧｅ−Ａｕ
からなる裏面電極Ｉ７が形成されている。-For example, the SiO2 film 14 surrounded by the SiO□ film 14 is approximately 0.2 μm deeper than the bottom of the P+ layer 13 by N""
It extends into the VG layer 11. In other words, P+ layer 13 and S
The iO2 film 14 forms substantially the same plane on its main surface,
The P+ layer 13 has N at a diffusion depth of about 1.0 μm from this main surface.
- Extends to the VG layer 11 side and surrounds the P layer 13' 5iO7
The membrane 14 has an extension depth of approximately 1.2 μm + 7) from this main surface.
VGI? ! It extends to 11111. A surface electrode 15 is formed on the P+R 13 so as to expose the current region extending about 20 μm from the periphery. The surface electrode 15 is made of AuGa or the like, and its thickness is set to about 3000X. On the surface electrode 15, a protruding electrode I6 is formed to cover the SiO2 film 14 (4'). The protruding electrode I6 is made of a material such as Ag. N+ semiconductor substrate I2
On the exposed back side of the
A back electrode I7 is formed.

このように構成されたＰＩＮダイオードペレット２０Ｖ
ｃよれば、Ｐ＋層１３とＮ−ＶＧ層１１間に形成された
接合は、平面接合になっているので、次式（２）で表わ
される接合周辺部容量（Ｃｐｅｒｉ）は、零となる。こ
のため極めて効率良く接合径を小さくすることができる
。PIN diode pellet 20V configured like this
According to c, since the junction formed between the P+ layer 13 and the N-VG layer 11 is a planar junction, the junction peripheral capacitance (Cperi) expressed by the following equation (2) becomes zero. Therefore, the joint diameter can be reduced extremely efficiently.

Ｃｐｅｒｉ＝（・ｄ・ε０εｇｉ　’　Ａｎ（循囚了（
２）ここで、ｄ：接合径 ε；真空中誘電率 ε８．：シリコンの比誘電率 Ｗ　：　Ｎ−ＶＧ層ＩＩＯ幅 ｘｊ：接合深さ また、１層１３によって平面接合が形成されているので
、表面電流（Ｉｓｕｔ）が少なく、シかも接合周辺部の
電流（Ｉｐｅｒｉ）にバイアスされた動作抵抗（ｒＦ、
）は無いので、バイアス電流（工。）による動作抵抗は
、全部真下方向で効率良く、面積縮少にもかかわらず小
さい値である。Cperi=(・d・ε0εgi ' An(circulation prisoner completed)
2) Here, d: junction diameter ε; dielectric constant in vacuum ε8. : Relative dielectric constant of silicon W : N-VG layer IIO width xj : Junction depth In addition, since a planar junction is formed by one layer 13, the surface current (Isut) is small, and the current (Isut) around the junction is small. operating resistance (rF,
), the operating resistance due to the bias current (d) is efficient in the downward direction, and has a small value despite the area reduction.

また、突起電極１６は、略きの千秋をなしており、８１
０□膜１４から離間しているので、　ＭＯ８容量が無く
なり効率良く低容量にすることができる。このことは第
３図から明らかである。なお図中（Ｉ）は実施例のＰＩ
Ｎダイオ−トイレットのダイオード容量（Ｇ）のばらつ
きを示し、（■）は、従来のＰＩＮダイオード（レット
のダイオード容量（Ｇ）のばらつきを示している。また
、ＭＯ８容量が無くなったので、突起電極１６の大きさ
のばらつきは、製品の品質にほとんど影響を及ぼさない
。更に、このようｒ、ｉ’ＰＩＮダイオードペレット１
１の構造から降伏電圧（ＶＲ）の絶対値を大きくするこ
とができる。Further, the protruding electrode 16 has an abbreviated shape, 81
Since it is spaced apart from the 0□ film 14, the MO8 capacity is eliminated and the capacity can be efficiently reduced. This is clear from FIG. Note that (I) in the figure is the PI of the example.
(■) shows the variation in the diode capacitance (G) of the conventional PIN diode (RET). Also, since the MO8 capacitance has been eliminated, the protruding electrode The variation in the size of 16 has little effect on the quality of the product.Furthermore, such r, i' PIN diode pellet 1
From the structure of No. 1, the absolute value of the breakdown voltage (VR) can be increased.

なお、このよう４「構造のＰＩＮダイオードベレット２
０は、例えば次のようにして得られる。In addition, the PIN diode bellet 2 with a 4" structure like this
0 can be obtained, for example, as follows.

まず、Ｎ＋半導体基板１１上に気相成長法により所定の
厚さのＮ−ＶＧ層１２を形成する。次いで、Ｎ−ＶＧ層
１２の主面に所謂ＬＯＣＯ８法による選択酸化を施すた
めに、所定の膜厚の窒化けい素ＳｉＮ膜等を形成し、こ
れに２１層形成予定領域が残存するようにｄ’ターニン
グを施す。・々ターニングされた５ｉＮＩＩ！Ｘ等をマ
スクにして選択酸化を施し、Ｎ−ＶＧ層１２内に約１，
２μｍの延出深さで延出するＳ　ｉ　Ｏ２膜１４を形成
する。First, an N-VG layer 12 of a predetermined thickness is formed on an N+ semiconductor substrate 11 by a vapor phase growth method. Next, in order to selectively oxidize the main surface of the N-VG layer 12 by the so-called LOCO8 method, a silicon nitride SiN film or the like is formed with a predetermined thickness, and d is etched so that a region where the 21st layer is to be formed remains. 'Apply turning.・5iNII has been turned! Selective oxidation is performed using X as a mask, and about 1,
A SiO2 film 14 extending to an extension depth of 2 μm is formed.

次に、マスクの役目をなしたＳｉＯ２膜等を除去し、露
出されたい層形成予定領域内に、熱拡散法、イオン注入
法等により拡散深さが約１．０μｍのＰ＋層１３を形成
する。Next, the SiO2 film, etc. that served as a mask is removed, and a P+ layer 13 with a diffusion depth of about 1.0 μm is formed in the exposed region where the layer is to be formed by thermal diffusion, ion implantation, etc. .

次に、Ｐ＋層１３及びｓｉｏ□膜１４に真空蒸着法によ
りＡｕＧａ層を厚さ約３０００１形成し、これにＰ＋層
１３の周囲から約２０μｍの環状領域及びＳｉＯ膜Ｉ４
の表面′が露出するように写真蝕刻法にてパターニング
を施し、表面電極１５を形成する。Next, an AuGa layer with a thickness of about 30,000 mm is formed on the P+ layer 13 and the sio□ film 14 by vacuum evaporation, and an annular region of about 20 μm from the periphery of the P+ layer 13 and a SiO film I4 are formed on this.
A surface electrode 15 is formed by patterning by photolithography so that the surface ' is exposed.

次いで、Ｎ＋半導体基板Ｉ２の裏面側に厚さ１５０μｍ
のラッピング処理を施した後、ＡｕＧｅ−Ａｕ層からな
る裏面電極Ｉ７を約３μｍ形成する。Next, a layer with a thickness of 150 μm was formed on the back side of the N+ semiconductor substrate I2.
After the lapping process, a back electrode I7 made of an AuGe-Au layer is formed to a thickness of about 3 μm.

然る後、表面電極１５及びＰ＋層１３　ｒ　５Ｉ０２膜
ｘ４の露出表面を覆う厚肉のレジスト膜を形成し、この
レジスト膜に表面電極１５に通じる窓を開口する。次い
で、この窓を介して表面電極１５に接続する突起電極１
６を例えばＡｇを用いてレジスト膜上に形成する。この
後、レジスト膜を除去して略きの予病の突起電極１６が
表面電極Ｉ５上に形成されｆ′ｃ、ＰＩＮダイオードペ
レッ　　ト−１し−ρ１（ヒ得　る　。Thereafter, a thick resist film is formed to cover the exposed surfaces of the surface electrode 15 and the P+ layer 13 r 5I02 film x4, and a window communicating with the surface electrode 15 is opened in this resist film. Next, the protruding electrode 1 is connected to the surface electrode 15 through this window.
6 is formed on a resist film using, for example, Ag. Thereafter, the resist film is removed, and a protruding electrode 16 is formed on the surface electrode I5.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明に係るＰＩＮダイオードペレ
ットによれば、小容量でしかも低動作抵抗を有する等顕
著な効果を有するものである。As explained above, the PIN diode pellet according to the present invention has remarkable effects such as small capacity and low operating resistance.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、従来のＰＩＮダイオードベレットの断面図、
第２図は、本発明の一実施例のＰＩＮダイオードベレッ
トの断面図、第３図は、ダイオード容量と個数の関係を
示す特性図である。 １１・・・Ｎ−ＶＧ層、Ｉ２・・・耐半導体基板、１３
・・・Ｐ＋層、１４・・・Ｓ　ｉＯ２膜、１５・・・表
面電極、１６・・・突起電極、１７・・・裏面電極、１
Ｌ・・・ＰＩＮダイオードペレット。 出願人代理人　　弁理士　鈴　江　武　彦第１図 秒 第２図 辺 第３図 イ固壺シＬ（Ｎ）（個）Figure 1 is a cross-sectional view of a conventional PIN diode pellet;
FIG. 2 is a cross-sectional view of a PIN diode pellet according to an embodiment of the present invention, and FIG. 3 is a characteristic diagram showing the relationship between diode capacitance and number. 11... N-VG layer, I2... semiconductor resistant substrate, 13
... P+ layer, 14... SiO2 film, 15... Surface electrode, 16... Projection electrode, 17... Back electrode, 1
L...PIN diode pellet. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Second Figure 2 Side Figure 3 Hardware L (N) (pcs)

Claims (1)

【特許請求の範囲】[Claims] 一導電型の半導体層と、該半導体層の所定領域にその主
面から所定の深さで延出して該主面に平行な平面接合を
形成する逆導電型の不純物層と、該不純物層を囲み、か
つ前記主面から前記半導体層内に該不純物層よりも深く
延出した絶縁膜と、該絶縁膜から離間して前記不純物層
に接続された略きの子状の突起電極とを具備することを
特徴とするＰＩＮダイオードペレット。a semiconductor layer of one conductivity type; an impurity layer of an opposite conductivity type that extends in a predetermined region of the semiconductor layer at a predetermined depth from the main surface of the semiconductor layer to form a planar junction parallel to the main surface; an insulating film surrounding the main surface and extending deeper into the semiconductor layer than the impurity layer; and a substantially mushroom-shaped protruding electrode spaced apart from the insulating film and connected to the impurity layer. A PIN diode pellet characterized by:
JP9712883A 1983-06-01 1983-06-01 P-i-n diode pellet Pending JPS59222970A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9712883A JPS59222970A (en) 1983-06-01 1983-06-01 P-i-n diode pellet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9712883A JPS59222970A (en) 1983-06-01 1983-06-01 P-i-n diode pellet

Publications (1)

Publication Number Publication Date
JPS59222970A true JPS59222970A (en) 1984-12-14

Family

ID=14183922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9712883A Pending JPS59222970A (en) 1983-06-01 1983-06-01 P-i-n diode pellet

Country Status (1)

Country Link
JP (1) JPS59222970A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429515B1 (en) * 2001-12-27 2004-05-03 삼성전자주식회사 Fabrication method for optical communication elements with mushroom type plating layer
KR100464378B1 (en) * 2002-01-08 2005-01-03 삼성전자주식회사 Photodiode for ultra high speed optical communication and fabrication method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4830790A (en) * 1971-08-23 1973-04-23
JPS4864887A (en) * 1971-11-26 1973-09-07
JPS517033A (en) * 1974-06-03 1976-01-21 Ford Motor Co Konseisuiseitoryo oyobi sonoseizohoho
JPS53104164A (en) * 1977-02-23 1978-09-11 Hitachi Ltd Bump electrode production in semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4830790A (en) * 1971-08-23 1973-04-23
JPS4864887A (en) * 1971-11-26 1973-09-07
JPS517033A (en) * 1974-06-03 1976-01-21 Ford Motor Co Konseisuiseitoryo oyobi sonoseizohoho
JPS53104164A (en) * 1977-02-23 1978-09-11 Hitachi Ltd Bump electrode production in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100429515B1 (en) * 2001-12-27 2004-05-03 삼성전자주식회사 Fabrication method for optical communication elements with mushroom type plating layer
KR100464378B1 (en) * 2002-01-08 2005-01-03 삼성전자주식회사 Photodiode for ultra high speed optical communication and fabrication method thereof

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