JP2961805B2 - Superconducting element and method of manufacturing the same - Google Patents

Superconducting element and method of manufacturing the same

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Publication number
JP2961805B2
JP2961805B2 JP2102440A JP10244090A JP2961805B2 JP 2961805 B2 JP2961805 B2 JP 2961805B2 JP 2102440 A JP2102440 A JP 2102440A JP 10244090 A JP10244090 A JP 10244090A JP 2961805 B2 JP2961805 B2 JP 2961805B2
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JP
Japan
Prior art keywords
superconducting
electrode
semiconductor substrate
region
concave portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2102440A
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Japanese (ja)
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JPH042180A (en
Inventor
一郎 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
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Publication date
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Priority to JP2102440A priority Critical patent/JP2961805B2/en
Publication of JPH042180A publication Critical patent/JPH042180A/en
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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は超伝導体と半導体とにより構成される超伝導
素子およびその製造方法に関する。
Description: TECHNICAL FIELD The present invention relates to a superconducting element composed of a superconductor and a semiconductor, and a method for manufacturing the same.

〔従来の技術〕 従来の超伝導体−半導体結合素子では、例えばティー
ニシノら(T.NISHINO et al.)により アイ イー
イー イー トランザクションズ オン エレクトロン
デバイシズ レターズ(IEEE Transactions On Elect
ron Devices Letters)10巻,1989年2月号,61ページに
報告されているように、2つの超伝導体から半導体へ侵
入した超伝導状態の侵入長程度の領域でスイッチング動
作を実行する。その結果、2つの超伝導体間の距離を上
記の侵入長程度にし、かつ、その間で半導体のキャリア
濃度を制御していた。
[Prior art] In a conventional superconductor-semiconductor coupling device, for example, T. NISHINO et al.
IEEE Transactions On Electron Devices Letters
As reported in Vol. 10, 1989, February 61, pp. 61, the switching operation is performed in a region where the superconducting state penetrates into the semiconductor from two superconductors. As a result, the distance between the two superconductors is set to the above-described penetration length, and the carrier concentration of the semiconductor is controlled between them.

半導体内のキャリア濃度の制御は、半導体に電界を印
加した電界効果を使う場合と、PN接合を使う場合とが考
えられている。いずれの場合も、ゲート電極は、半導体
基板表面に対して超伝導電極と同じ側にあっても反対側
にあってもよい。
It is considered that the carrier concentration in the semiconductor is controlled by using an electric field effect in which an electric field is applied to the semiconductor or by using a PN junction. In any case, the gate electrode may be on the same side as or opposite to the superconducting electrode with respect to the surface of the semiconductor substrate.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

上述の従来の超伝導素子の超伝導状態の侵入長は通常
の半導体を用いた場合0.1μm以下であり、ゲート電極
を半導体基板表面に対して超伝導電極と同じ側に設ける
場合には、0.1μm程度の間隔の超伝導電極間にこれを
設けなければならず、現在の微細加工技術では非常に困
難であった。
The penetration length of the superconducting state of the above-mentioned conventional superconducting element is 0.1 μm or less when a normal semiconductor is used, and when the gate electrode is provided on the same side as the superconducting electrode with respect to the surface of the semiconductor substrate, 0.1 μm This must be provided between superconducting electrodes at intervals of about μm, which has been extremely difficult with the current fine processing technology.

また、ゲート電極を半導体基板表面に対して超伝導電
極の反対側に設ける場合には、素子の集積化に必要なプ
レーナー構造を実現できなかった。
Further, when the gate electrode is provided on the opposite side of the superconducting electrode with respect to the surface of the semiconductor substrate, a planar structure required for element integration cannot be realized.

本発明の目的は、従来技術でも充分余裕のある微細加
工技術を適用してプレーナー構造を実現することが可能
な超伝導体−半導体結合素子およびその製造方法を提供
することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a superconductor-semiconductor coupling device capable of realizing a planar structure by applying a microfabrication technology having a sufficient margin even in the conventional technology, and a method of manufacturing the same.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の超伝導素子は、半導体基板の表面の所定領域
に設けられた所定深さを有する凹部に所定深さより小さ
な値の所定膜厚を有する第1の超伝導電極が埋め込ま
れ、半導体基板の表面に一端が凹部の上端部と一致する
第2の超伝導電極が設けられ、第1の超伝導電極上の一
部,第2の超伝導電極上の一部,並びに凹部側壁表面に
おいて第1の超伝導電極および第2の超伝導電極に挟ま
れて形成された一定の値の幅を有する間隔領域の表面上
を含めた領域に絶縁層が設けられ、絶縁層上における少
なくとも前記間隔領域上を含めた領域にゲート電極が設
けられている。
In the superconducting element of the present invention, a first superconducting electrode having a predetermined thickness smaller than the predetermined depth is embedded in a concave portion having a predetermined depth provided in a predetermined region on the surface of the semiconductor substrate, A second superconducting electrode whose one end coincides with the upper end of the concave portion is provided on the surface, and a portion on the first superconducting electrode, a portion on the second superconducting electrode, and a first superconducting electrode on the concave portion side wall surface. An insulating layer is provided in a region including the surface of the interval region having a constant value width and formed between the superconducting electrode and the second superconducting electrode. The gate electrode is provided in a region including the.

また、本発明の超伝導素子の製造方法は、半導体基板
の表面の所定領域に所定深さを有する凹部を設ける工程
と、凹部を含む半導体基板に超伝導体膜を垂直入射によ
る電子銃蒸着により所定膜厚堆積して凹部に第1の超伝
導電極を形成する工程と、第1の超伝導電極上を覆い第
2の超伝導電極の形状に対応する形状を有するフォトレ
ジスト膜を形成して半導体基板表面上に残留した超伝導
膜をエッチングすることにより前記第2の超伝導電極を
形成する工程と、絶縁層を形成する工程と、絶縁層上に
ゲート電極を形成する工程とを有している。
Further, the method for manufacturing a superconducting element of the present invention comprises the steps of: providing a concave portion having a predetermined depth in a predetermined region on the surface of a semiconductor substrate; Forming a first superconducting electrode in the concave portion by depositing a predetermined film thickness, and forming a photoresist film covering the first superconducting electrode and having a shape corresponding to the shape of the second superconducting electrode; Forming a second superconducting electrode by etching a superconducting film remaining on a surface of a semiconductor substrate, forming an insulating layer, and forming a gate electrode on the insulating layer. ing.

〔作用〕[Action]

本発明の超伝導素子の構造は、半導体基板表面の一部
に形成された凹部に埋め込まれた第1の超伝導電極と、
一端が凹部の上端部と一致して半導体基板表面に設けら
れた第2の超伝導電極とは、凹部側壁表面において分離
されている。更に、第1の超伝導電極上の一部,第2の
超伝導電極上の一部,並びに凹部において第1の超伝導
電極および第2の超伝導電極に挟まれて形成された一定
の値を有する間隔領域(この領域は凹部側壁表面に形成
される)の半導体基板表面は絶縁層で被覆されており、
絶縁層上に設けられたゲート電極と半導体基板および第
1,第2の超伝導電極とは電気的に絶縁されている。
The structure of the superconducting element of the present invention comprises: a first superconducting electrode embedded in a concave portion formed on a part of the surface of a semiconductor substrate;
The second superconducting electrode, one end of which coincides with the upper end of the concave portion, is separated from the second superconducting electrode provided on the surface of the semiconductor substrate at the surface of the concave portion side wall. Further, a certain value formed between the first superconducting electrode and the second superconducting electrode in a part on the first superconducting electrode, a part on the second superconducting electrode, and the recess. The surface of the semiconductor substrate in the interval region having (the region is formed on the surface of the side wall of the concave portion) is covered with an insulating layer,
A gate electrode provided on an insulating layer, a semiconductor substrate,
1. It is electrically insulated from the second superconducting electrode.

従って、ゲート電極に電圧を印加することにより生ず
る電界効果により、第1および第2の超伝導電極の間の
間隔領域における半導体基板内のキャリア濃度を制御す
ることができる。その結果、第1および第2の超伝導電
極の間の超伝導状態が制御され、これにより第1および
第2の超伝導電極の連結される状態,連結が切断される
状態を作りだすことができる。
Therefore, the carrier concentration in the semiconductor substrate in the space between the first and second superconducting electrodes can be controlled by the electric field effect caused by applying a voltage to the gate electrode. As a result, the superconducting state between the first and second superconducting electrodes is controlled, so that a connected state and a disconnected state of the first and second superconducting electrodes can be created. .

本発明の超伝導素子の構造においては、第1,第2の超
伝導電極の形状形成(パターンニング)とは独立に第1
および第2の超伝導電極の間の間隔領域の幅(すなわ
ち、電界効果による超伝導状態を形成,抑制する領域の
幅)を設定することが可能であり、また、ゲート電極の
形成に特殊な微細加工技術を要することなしにプレーナ
ー構造を実現している。
In the structure of the superconducting element according to the present invention, the first and second superconducting electrodes have the first
And the width of the space between the second superconducting electrodes (that is, the width of the region where the superconducting state is formed and suppressed by the electric field effect) can be set. A planar structure is realized without requiring fine processing technology.

次に、本発明の超伝導素子の製造方法は、半導体基板
表面の所定領域に所定深さの凹部を形成し、全面に凹部
の深さより薄い膜厚の超伝導膜を垂直入射による電子銃
蒸着により堆積して凹部に第1の超伝導電極を形成し、
第1の超伝導電極上を覆い第2の超伝導電極の形状に対
応する形状を有するフォトレジスト膜を形成して半導体
基板表面上に残留した超伝導膜をエッチングすることに
より第2の超伝導電極を形成し、絶縁層を形成し、絶縁
層上にゲート電極を形成する。
Next, the method for manufacturing a superconducting element of the present invention comprises the steps of: forming a concave portion having a predetermined depth in a predetermined region on a surface of a semiconductor substrate; and depositing a superconducting film having a thickness smaller than the depth of the concave portion on the entire surface by electron gun evaporation by perpendicular incidence. To form a first superconducting electrode in the recess,
A second superconducting film is formed by forming a photoresist film covering the first superconducting electrode and having a shape corresponding to the shape of the second superconducting electrode and etching the superconducting film remaining on the surface of the semiconductor substrate. An electrode is formed, an insulating layer is formed, and a gate electrode is formed over the insulating layer.

第1,第2の超伝導電極の0.1μm程度の間隔は前述の
ように凹部側壁表面に第1の超伝導電極および第2の超
伝導電極に挟まれて形成された一定の値を有する間隔領
域の幅により規定されるが、この領域の形成には特に高
度な微細加工技術は必要としない。また本発明において
は、第1,第2の超伝導電極の間には微細な構造を有する
溝が形成されていないため、ゲート電極の形成には何ら
支障を来たさない。
The distance of about 0.1 μm between the first and second superconducting electrodes is a distance having a constant value formed between the first and second superconducting electrodes on the surface of the concave side wall as described above. Although defined by the width of the region, the formation of this region does not require a particularly sophisticated fine processing technique. Further, in the present invention, since no groove having a fine structure is formed between the first and second superconducting electrodes, there is no hindrance to the formation of the gate electrode.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図は本発明の第1の実施例の超伝導素子の構造を
示す断面図である。
FIG. 1 is a sectional view showing the structure of a superconducting element according to a first embodiment of the present invention.

例えばシリコンに5×1025m-3の濃度の砒素をドープ
した半導体基板1の表面の所定領域に形成された深さ40
0nmの凹部に、300nmの膜厚の例えばニオブが埋め込まれ
て第1の超伝導電極3が設けられる。この凹部は、3μ
m×5μmの大きさとした。この凹部の上端部と一端が
一致して半導体基板1の表面上に膜厚300nmのニオブか
らなる第2の超伝導電極5が配置される。
For example, a depth 40 formed in a predetermined region on the surface of the semiconductor substrate 1 in which silicon is doped with arsenic at a concentration of 5 × 10 25 m −3.
The first superconducting electrode 3 is provided by embedding, for example, niobium having a thickness of 300 nm in the recess of 0 nm. This recess is 3μ
The size was m × 5 μm. A second superconducting electrode 5 made of niobium having a thickness of 300 nm is arranged on the surface of the semiconductor substrate 1 so that one end of the concave portion coincides with one end.

凹部の側壁表面に第1の超伝導電極3と第2の超伝導
電極5とにより挟まれて形成される間隔領域の幅は、0.
1μmとなる。
The width of the interval region formed between the first superconducting electrode 3 and the second superconducting electrode 5 on the side wall surface of the concave portion is 0.
1 μm.

少なくとも第1の超伝導電極3の表面上の一部,少な
くとも第2の超伝導電極5の表面上の一部,並びに第1
の超伝導電極3と第2の超伝導電極5とに挟まれて形成
される間隔領域の凹部側壁表面からなる半導体基板1表
面上を含む領域に、例えば膜厚10nmの2酸化シリコンか
らなる絶縁層6が配置される。
At least a portion on the surface of the first superconducting electrode 3, at least a portion on the surface of the second superconducting electrode 5, and the first
In a region including the surface of the semiconductor substrate 1 including the surface of the recessed side wall of the interval region formed between the superconducting electrode 3 and the second superconducting electrode 5, for example, an insulating film made of silicon dioxide having a thickness of 10 nm is formed. Layer 6 is arranged.

少なくとも第1の超伝導電極3と第2の超伝導電極5
とに挟まれて形成される間隔領域の半導体基板1表面上
を含む絶縁層6上に、例えばアルミニウムを用いたゲー
ト電極7が設けられている。
At least a first superconducting electrode 3 and a second superconducting electrode 5
A gate electrode 7 made of, for example, aluminum is provided on the insulating layer 6 including the surface of the semiconductor substrate 1 in the interval region formed between the two.

第2図(a)〜(e)は本発明の第2の実施例の製造
方法を説明するための工程順の断面図である。
2 (a) to 2 (e) are sectional views in the order of steps for explaining a manufacturing method according to a second embodiment of the present invention.

まず、シリコンに5×1025m-3の濃度の砒素をドープ
した半導体基板1の表面の所定領域に、イオンミーリン
グ法により深さ400nm,大きさ3μm×5μmの凹部を形
成する〔第2図(a)〕。
First, a recess having a depth of 400 nm and a size of 3 μm × 5 μm is formed in a predetermined region of the surface of a semiconductor substrate 1 in which silicon is doped with arsenic at a concentration of 5 × 10 25 m −3 by ion milling [FIG. (A)].

続いて、ニオブからなる膜厚300nmの超伝導膜2を、
垂直入射の電子銃蒸着法により堆積する。半導体基板1
とニオブ蒸着源との間を100cm離して蒸着したところ、
半導体基板1の水平表面上と凹部とで超伝導膜2は分離
して堆積し、凹部においては超伝導膜2からなる第1の
超伝導電極3が形成される〔第2図(b)〕。
Subsequently, a 300 nm thick superconducting film 2 made of niobium is
It is deposited by a normal incidence electron gun evaporation method. Semiconductor substrate 1
And between the niobium deposition source and 100cm apart,
The superconducting film 2 is separately deposited on the horizontal surface of the semiconductor substrate 1 and the recess, and a first superconducting electrode 3 made of the superconducting film 2 is formed in the recess [FIG. 2 (b)]. .

次に、第2の超伝導電極の形成予定領域,および第1
の超伝導電極3を覆う領域に、フォトレジスト膜4によ
るパターンを形成する〔第2図(c)〕。このとき、フ
ォトレジスト膜4の端部の一部は、第1の超伝導電極3
を覆う領域の端部の一部と一致させるかあるいは内側に
設定することが必要である。
Next, a region where the second superconducting electrode is to be formed, and
Is formed in a region covering the superconducting electrode 3 of FIG. 2 (FIG. 2 (c)). At this time, a part of the end of the photoresist film 4 is
It is necessary to match with or set inside a part of the end of the region covering the.

続いて、フォトレジスト膜4をマスクに超伝導膜2を
エッチングし、フォトレジスト膜4を剥離することによ
り、超伝導膜2からなる膜厚300nmの第2の超伝導電極
5が、一端を凹部の上端部の一端と一致させて半導体基
板1の表面上に形成される〔第2図(d)〕。
Subsequently, the superconducting film 2 is etched using the photoresist film 4 as a mask, and the photoresist film 4 is peeled off, so that the second superconducting electrode 5 made of the superconducting film 2 and having a thickness of 300 nm has one end recessed. Is formed on the surface of the semiconductor substrate 1 so as to coincide with one end of the upper end [FIG. 2 (d)].

更に、第1の超伝導電極3と第2の超伝導電極5との
間を含めた領域に例えばCVD法により堆積した膜厚10nm
の2酸化シリコンからなる絶縁層6を形成し、絶縁層6
上の第1の超伝導電極3と第2の超伝導電極5との間を
含む領域にアルミニウムからなるゲート電極7を形成す
る〔第2図(e)〕。
Further, in a region including a region between the first superconducting electrode 3 and the second superconducting electrode 5, a film thickness of 10 nm
An insulating layer 6 made of silicon dioxide is formed.
A gate electrode 7 made of aluminum is formed in a region including between the first superconducting electrode 3 and the second superconducting electrode 5 (FIG. 2E).

第3図(a)〜(c)は,本発明の第3の実施例の製
造方法を説明するための主要工程の断面図である。
3 (a) to 3 (c) are sectional views of main steps for explaining a manufacturing method according to a third embodiment of the present invention.

第2図(b)に示した工程までは第2の実施例と同じ
に作製た後、全面に例えばネガ型のフォトレジスト膜8
を塗布する〔第3図(a)〕。
After the same process as in the second embodiment is performed up to the step shown in FIG. 2B, for example, a negative type photoresist film 8 is formed on the entire surface.
[FIG. 3 (a)].

次に、半導体基板1の表面に堆積した超伝導膜2の表
面が完全に露出するまでフォトレジスト膜8のエッチバ
ックを行なう〔第3図(b)〕。
Next, the photoresist film 8 is etched back until the surface of the superconducting film 2 deposited on the surface of the semiconductor substrate 1 is completely exposed [FIG. 3 (b)].

続いて、第2の超伝導電極の形状に対応した形状を有
しフォトレジスト膜8上に延在した形状の例えばポジ型
によるフォトレジスト膜9を形成する〔第3図
(c)〕。
Subsequently, a positive type photoresist film 9 having a shape corresponding to the shape of the second superconducting electrode and extending on the photoresist film 8 is formed (FIG. 3C).

更に、フォトレジスト膜8,フォトレジスト膜9をマス
クに超伝導膜2をエッチングし、フォトレジスト膜8,フ
ォトレジスト膜9を剥離することにより、第2の実施例
における第2図(d)に示した形状となる。以降の工程
は第2の実施例と同じである。
Further, the superconducting film 2 is etched by using the photoresist film 8 and the photoresist film 9 as a mask, and the photoresist film 8 and the photoresist film 9 are peeled off, as shown in FIG. 2D in the second embodiment. The shape is as shown. The subsequent steps are the same as in the second embodiment.

本実施例は、第2の超伝導電極の形成工程が第2の実
施例に比べて容易である。
In this embodiment, the process of forming the second superconducting electrode is easier than in the second embodiment.

なお、本発明の第1,第2,第3の実施例では、超伝導膜
にニオブ,半導体基板にシリコンを用いたが、本発明の
主旨はこれらの材料に限定されず、超伝導膜としては
鉛,窒化ニオブ,イットリウム系超伝導材料,バリウム
系超伝導材料,タリウム系超伝導材料などが、半導体基
板としてはInAs,InGaAs,Ge等の半導体材料が適用でき
る。
In the first, second and third embodiments of the present invention, niobium is used for the superconducting film and silicon is used for the semiconductor substrate. However, the gist of the present invention is not limited to these materials. For example, lead, niobium nitride, yttrium-based superconducting materials, barium-based superconducting materials, and thallium-based superconducting materials can be used. As the semiconductor substrate, semiconductor materials such as InAs, InGaAs, and Ge can be used.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明の超伝導素子およびその製
造方法は、超伝導電極間における半導体基板に超伝導状
態を発生させる領域の構造,およびゲート電極の構造が
従来のように複雑な,かつ微細な構造を必要とせず、プ
レーナー構造を実現できる。また、用いる製造プロセス
もプロセス余裕度の向上の困難な微細加工技術は不要で
あることから、大きなプロセス余裕度を持って製造する
ことが可能となる。
As described above, the superconducting element and the method of manufacturing the same according to the present invention have a structure in which a superconducting state is generated in a semiconductor substrate between superconducting electrodes, and a structure of a gate electrode which is complicated and fine as in the prior art. A planar structure can be realized without requiring a simple structure. In addition, since the manufacturing process to be used does not require a fine processing technique for which it is difficult to improve the process margin, it is possible to manufacture with a large process margin.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の第1の実施例を説明するための断面
図、第2図(a)〜(e)は本発明の第2の実施例を説
明するための工程順の断面図、第3図(a)〜(c)は
本発明の第3の実施例を説明するための主要工程の断面
図である。 1……半導体基板、2……超伝導膜、3……第1の超伝
導電極、4,8,9……フォトレジスト膜、5……第2の超
伝導電極、6……絶縁層、7……ゲート電極。
FIG. 1 is a cross-sectional view for explaining a first embodiment of the present invention, FIGS. 2 (a) to 2 (e) are cross-sectional views in the order of steps for explaining a second embodiment of the present invention, 3 (a) to 3 (c) are cross-sectional views of main steps for explaining a third embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Superconducting film, 3 ... First superconducting electrode, 4,8,9 ... Photoresist film, 5 ... Second superconducting electrode, 6 ... Insulating layer, 7 ... Gate electrode.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板の表面の所定領域に設けられた
所定深さを有する凹部に前記所定深さより小さな値の所
定膜厚を有する第1の超伝導電極が埋め込まれ、前記半
導体基板の表面に一端が前記凹部の上端部と一致する第
2の超伝導電極が設けられ、前記第1の超伝導電極上の
一部,前記第2の超伝導電極上の一部,並びに前記凹部
側壁表面において前記第1の超伝導電極および前記第2
の超伝導電極に挟まれて形成された一定の値の幅を有す
る間隔領域の表面上を含めた領域に絶縁層が設けられ、
前記絶縁層上における少なくとも前記間隔領域上を含め
た領域にゲート電極が設けられたことを特徴とする超伝
導素子。
A first superconducting electrode having a predetermined thickness smaller than the predetermined depth is embedded in a concave portion having a predetermined depth provided in a predetermined region on a surface of the semiconductor substrate; A second superconducting electrode, one end of which coincides with the upper end of the concave portion, a part on the first superconducting electrode, a part on the second superconducting electrode, and a surface of the side wall of the concave portion. The first superconducting electrode and the second superconducting electrode
An insulating layer is provided in a region including on the surface of the interval region having a fixed value width formed between the superconducting electrodes,
A superconducting element, wherein a gate electrode is provided on at least a region on the insulating layer including the space region.
【請求項2】請求項1記載の超伝導素子において、前記
半導体基板の表面の所定領域に所定深さを有する前記凹
部を設ける工程と、前記凹部を含む前記半導体基板に垂
直入射による電子銃蒸着により所定膜厚の超伝導体膜を
堆積して前記凹部に前記第1の超伝導電極を形成する工
程と、前記第1の超伝導電極上を覆い前記第2の超伝導
電極の形状に対応する形状を有するフォトレジスト膜に
より前記半導体基板表面上の前記超伝導膜をエッチング
して前記第2の超伝導電極を形成する工程と、前記絶縁
層を形成する工程と、前記絶縁層上に前記ゲート電極を
形成する工程とを有することを特徴とする超伝導素子の
製造方法。
2. A superconducting device according to claim 1, wherein said step of providing said concave portion having a predetermined depth in a predetermined region on a surface of said semiconductor substrate, and electron gun vapor deposition by perpendicular incidence on said semiconductor substrate including said concave portion. Forming a first superconducting electrode in the concave portion by depositing a superconducting film having a predetermined thickness, and corresponding to the shape of the second superconducting electrode by covering the first superconducting electrode. Forming the second superconducting electrode by etching the superconducting film on the surface of the semiconductor substrate with a photoresist film having a shape to be formed; and forming the insulating layer. Forming a gate electrode.
JP2102440A 1990-04-18 1990-04-18 Superconducting element and method of manufacturing the same Expired - Fee Related JP2961805B2 (en)

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JP2102440A JP2961805B2 (en) 1990-04-18 1990-04-18 Superconducting element and method of manufacturing the same

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Application Number Priority Date Filing Date Title
JP2102440A JP2961805B2 (en) 1990-04-18 1990-04-18 Superconducting element and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH042180A JPH042180A (en) 1992-01-07
JP2961805B2 true JP2961805B2 (en) 1999-10-12

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