GB2164205A

GB2164205A - Charge-coupled device

Info

Publication number: GB2164205A
Application number: GB08520752A
Authority: GB
Inventors: Burghard Korneffel
Original assignee: Werk fuer Fernsehelektronik GmbH
Current assignee: Werk fuer Fernsehelektronik GmbH
Priority date: 1984-08-21
Filing date: 1985-08-19
Publication date: 1986-03-12
Also published as: DD231896A1; GB2164205B; DE3527949A1; GB8520752D0; JPS6187370A; FR2569486A1

Abstract

The invention relates to a charge-coupled device which finds application in microelectronics and in optoelectronics both in the form of individual rows and also as rows grouped together in flat arrangements. All the area not masked by electrodes 12 is doped. Thereafter, a second set of electrodes 15, not insulated from electrodes 12, and a mask are used with electrodes 12 for compensation doping to override part of the first doped regions, giving separated areas 14. A third insulated electrode 18 is then provided to give a two-phase CCD, or channel stops formed between adjacent areas 14 (figure 2, not shown). The doped zones are self-aligned with the electrodes. <IMAGE>

Description

SPECIFICATION Charge-coupled device (CCD) The invention relates to a novel concept aimed at providing a charge-coupled device. Such components are widely used in microelectronics and optoelectronics, both in the form of individual rows and also rows grouped together to form planar arrangements.

Of the various types of CCD known, those with two phases are particularly advantageous in terms of activation. In the case of one known alternative, see for example the Fairchild range of CCD types, and also the L 110, L 133 and L 211 devices made by VEB WF, Berlin, the storage electrodes are made with a first poly-Si plane and the transfer electrodes with a second poly-Si plane. In this case, the transfer electrodes bridge the structured gap between the storage electrodes. Prior to separation of the second poly-Si plane, a dopand of the substrate conducting type is implanted into the gaps, automatically adjusted by the edges of the storage electrodes, so establishing the potential barrier zones necessary for the subsequent two-phase operation. In each case a pair of electrodes will comprise a storage electrode and a transfer electrode.The pairs of electrodes are alternately connected to the first and second clock phase. To this end, each of the storage electrodes must be electrically isolated from its neighbour storage electrodes. The same requirement applies to the transfer electrodes.

Furthermore, the insulation between storage electrode and the transfer electrode which overlaps it but which is connected to the other clock phase must be perfect.

These last-mentioned requirements cannot always be easily met in the technological process.

Electrical separation of the transfer electrodes from one another is often unattained due to the formation or continued existence of so-called poly-Si threads.

The technical literature available in the field already contains suggestions, e.g. U.S. Patents Nos.

4027381,4027382 and 4035906, whereby, in the case of a two-phase CCD, the electrodes of each clock phase are adjusted out of in each case only one applied electrode plane, in order thus to obviate problems such as the formation of poly-Si threads.

In the main, two basic variations are applied: 1. Gate oxide stages in conjunction with barrier implantation, and 2. Prior to application of the first electrode planes, a first barrier implantation, the implant being in certain partial zones subsequently and for the major part dissipated by the oxide as a result of an oxidation process, and also a subsequent second barrier implantation. Technologies of this type are complicated. Since the dissipation of a barrier implant by an oxide is not complete, problems are created due to lack of potential homogeneity in the CCD cell which is produced.

The smallest possible grid is, in the case of the technology mentioned at the outset, where transfer electrodes bridge the structured gaps between storage electrodes, is determined by minimum viable gap length and minimum required overlap between storage and transfer electrode. For instance, if the minimum gap length between the transfer electrodes is 4 pm, and the minimum overlap 2pom, then the minimum length of storage electrode will be 8 pm. In the case of a 4 pm gap between the storage electrodes a minimum grid of 12 pm will result.

The object of the invention is to avoid the disadvantages indicated with reference to the known stage of the art without this giving rise to an unacceptable increase in technological cost and complication.

The invention was based on the problem of constructing a two-phase CCD with self-adjusting barrier zones, whereby with relatively uncomplicated technology, no electrical separation of electrodes structured from one plane is necessary and where a smaller grid is made possible.

In order to resolve this problem, the invention proposes the use of three electrode planes, the second electrode plane not being isolated from the first electrode plane. Furthermore, in parts of the substrate where initially there had been a barrier implant, a subsequently introduced compensating implant again produces a potential appropriate to the storage of charge carriers.

A semi-conductor substrate is coated with a film of suitable insulant on which a first electrode plane is deposited. Priortothis, in orderto guarantee transport of signal charge in a volume channel (BCCD), a doping zone may have been incorporatd into the substrate and may be of a type offering reverse conductance to that of the substrate. If this doping zone is not provided, then the charge will be transported on the surface. Suitable channel stopper zones may likewise have been previously incorporated.

Afirst electrode configuration is structured out of the first electrode plane. This first electrode plane will in subsequent operation monitor storage zones.

Afterwards, there will be large area implanting of a dopand of the substrate conductance type. The first electrode configuration serves thereby as an implant mask. Rate and energy of this implantation will advantageously be so chosen that areas provided with this implantation and which are not covered by the compensating doping which will be discussed later can serve as transfer zones when the future CCD register is used, i.e. in these zones, a potential barrier will be created vis-a-vis the storage zones. Afterwards, a second electrode plane is deposited and need not be insulated from the first electrode configuration.The second electrode configuration is structured out of the second electrode plane so that in each case on electrode of the second configuration has an edge overlapping an electrode of thefirst configuration. In the direction of transport of the CCD register, there is at this stage an area which is free from electrode material between the individual pairs of electrodes of the first and second planes. Now, through a suitable mask, which may be made for instance from photo resist, a dopand of a conductance opposite to that of the substrate, may be implanted into a part of the zone which is not covered by any electrode material.

Dose rate and implantation energy are thereby so dimensioned that the potential barrier producing effect of the previously implanted dopand of the substrate conductor type (in the case of this last implantation) is compensated. For this compensation, there is no need for the implantation profile of the compensating doping to be identical to the profile of the previously implanted dopand which was of the substrate conduction type.It is sufficient of the potential in the zones covered by the compensating doping attains in the event of operation of the future CCD register, a value which is adequate for the storage of charge carriers, i.e. it is sufficient if, in case of operation, these zones can serve as storage zones The implantation mask is in principle positioned as follows in relation to the first and second electrode configuration: what is masked is a strip which is adjacent those sides of the electrode of the first configuration which are not covered by the electrodes of the second configuration.After the compensating doping has been carried out, the following sequence of zones will extend along the direction of transport of the CCD register: electrode of the second configuration with barrier doping underneath it, first configuration electrode with "store" doping underneath it, an electrode free zone with barrier doping, electrode free zone with barrier doping plus compensating doping, a second configuration electrode with barrier doping underneath it, etc.

Now the pairs of electrodes of the first and second plane are coated with a suitable film of insulant.

Then the first electrode level is applied and the third electrode configuration is structured out of it. This structuring is relatively coarse and this third configuration can remain cohesive along the transport direction of the CCD register.

For the rest, the conventional steps are carried out, such as incorporation of source and drain zones, possible deposition of further insulating layers, structuring of contact windows and the application and structuring of a guide path plane.

During operation of the CCD register, all pairs of electrodes comprising first and second plane are connected to one clock phase while the entire third electrode configuration is connected to the second clock phase. Since each of the applied electrode planes is connected to a standard clock phase, there is no need for any electrical isolation of the individual electrodes from one another within one and the same plane.

Problems such as occur with the abovementioned prior art constructions, due to poly-Si threads, do not occur with this invention.

The third electrode configuration does not require any "fine structuring" along the CCD register.

This fact simplifies manufacture.

The potential barriers effective in the CCD register are, as emerges clearly from the foregoing, incorporated in self-aligned manner. Atwo-phase CCD would have excessively adverse disadvantages without any such self-alignment.

However, contacting is space-saving and simplified, too. In the absence of "fine structuring" there is no problem contacting the third electrode configuration in the region of the active face of the register. The width of the CCD register can thus be made minimal, which is particularly advantageous in the case of flat CCD registers in which there are between the individual rows electrodeless photo sensors so that the CCD registers can only be contacted individually along the direction of transport.

The above-explained idea of compensating doping, the term compensation referring to the potential, can also be more generally applied within the meaning of this invention. For example, it is often necessary to provide among individual electrodes self-aligned potential barrier producing zones. For such a purpose, the aforesaid second electrode configuration would not within the abovedescribed cycle overlap the first configuration, or alternatively there need not be any first electrode configuration. After what is known as the compensating doping has been carried out, then, self-aligned potential barrier producing zones are present among the electrodes of the second configuration.

Applying the thoughts so far expressed in this specification, it is particularly advantageous to construct BCCDs, in which partial zones are covered by flat (vertical) channel stopper layers. A representative of such BCCDs is described in U.S.

Patent No. 4229752, where the extremely thin channel-stopper layer used is termed a "virtual phase".

Manufacture of the BCCD is thereby (as described above) carried out in that the first electrode configurations which are not insulated from one another are structured and the compensation implant incorporated. Then, without an additional mask, a dopand of the conductance type opposite to that of the substrate and of high energy, and a dopand of the same conduction type as the substrate and of low energy are implanted. The substrate conduction type dopand is positiond in the surface zone of the semiconductor. The resultant flat channel stopper layer screens the interior of the semiconductor against external fields. Any additional third electrode plane is superfluous. The additionally incorporated dopand of the opposite conduction type to the substrate provides the necessary potential in the volume channel of the area covered by the flat channel stopper layer.

The clock voltage is applied to the first two electrode configurations which are not insulated from each other. Attention is drawn expressly to the fact that no stages are required in the gate isolator for the two-phase CCD constructed according to this invention. For example, it is possible to work with a double layer of oxide and nitride applied to the substrate at one go. If a flat (vertical) channel stopper layer is provided, then a single deposit of oxide would suffice as a gate isolator.

A minimal grid can be assessed as follows: the overlap of the second-level electrodes with those of the first level is a minimal 2 pm. Since the edge of the second level electrodes can be adjusted to the centre of the first level electrodes, the minimum gate length for the electrodes on the first level will be 4 pm. With a barrier zone 4 pm long, this results in a minimal grid of 8 pm.

Example of embodiment The invention will be explained hereinafter with reference to an example of embodiment shown in the accompanying drawings, in which: Fig. 1 shows individual stages in the manufacture of a first embodiment, and Fig. 2 shows a second embodiment.

In the example of embodiment illustrated, the premise adopted is a p-conductive Si-substrate. Of course, the invention can also be implemented using n-conductive substrates. The dopings which then have to be incorporated are in each case of the opposite type of conductance. Furthermore, the electrode material indicated is poly-crystalline silicon. Of course, other suitable materials, particularly silicides, may also be used.

Figs. 1 a to c show cross-sections taken along the direction of transport of what will subsequently become the charge-coupled shift register. An ndoping 11 is incorporated (Fig. la) over a large area of what will later on be the active zones of a pconductive Si substrate 10. The dosage of thes ndoping 11 was so dimensioned that in subsequent operation of the CCD shift register the zone 11 can be completely depleted of movable charge carriers.

The channel stopper zones needed for lateral definition of the shift register cannot be represented in the sectional drawings in Figs. 1 and 2. The channel stopper zones are sufficiently highly pdoped zones or a combination of high p-doping with a thick field oxide. The active zones have been coated with the gate isolator 13. A most suitable gate isolator 13 is a double later of thermally deposited SiO2 and chemically deposited Si3N4. The first electrode configuration 12 was structured out of the first deposited and doped poly/Si layer. This was followed by a large-area boron implantation, the electrodes 12 serving as a mask, and the result was the slightly p-doped zones 14. These zones 14 produced the potential barriers needed for subsequent two-phase operation.

The next stage is application of the second poly-Si layer which is doped and out of which the electrode configuration 15 is structured (see Fig. 1b). No insulation is required between the electrodes 15 and the electrodes 12. Once the photo resist mask 16 has been produced, there is an implantation of phosphorous. By reason of the masking by means of the electrodes 12 and 15 and the photo resist mask 16, the implant only reaches the zones 17 in the semiconductor substrate.

Dosage and energy of this phosphorous implantation are so dimensioned that the potential barrier-producing effect of the zones 14 is compensated by the zones 17 reached by the phosphorous implant.

For this compensation, it is not necessary for the implantation profile of this phosphorous implantation to be identical to the profile of the boron implantation which produces the zones 14. It is sufficient if the potential in the zones 17, by reason of the action of the phosphorous and boron implantation and the channel doping incorporated in an earlier stage of the process, to achieve in CCD operating mode approximately the same value as in the zones 11.

After removal of the photo resist mask 16, the electrodes 12 and 15 are jointly coated with an insulating film 28. This can be carried out by thermal oxidation of the poly-Si., Now the third poly-Si layer is applied and the electrode configuration 18 is structured out of it (see Fig. 1 c). Doping of the poly Si electrodes 18 can take place during the later source and drain diffusion.

Structuring of the third poly-Si later is relatively coarse and the electrode 18 can remain cohesive along the transport direction of the CCD register.

For further preparation of the CCD register, there are the usual stages such as source and drain diffusion, deposition of silox, structuring of contact windows and application of an Al guide path plane.

For operation, one clock phase is applied to the electrode 18 while the other clock phase is applied to the conductively inter-connected electrodes 12 and 15. Fig. 1d shows the maximum potentials in the empty charge transport channel if it is assumed that a DC potential (e.g. 6 V) is applied to the electrodes 12 and 15 and an impulse voltage (e.g.

Utow = O V, Uhigh = 12 V) is applied to the electrode 18. Under the electrodes 12 and 15, then, the potential exhibits the pattern 19 while in the area monitored by the electrode 18, the potential changes in rhythm with the clock tension from pattern 20 for U,Ow to pattern 21 for Uhigh.

Illustrated diagrammatically in Fig. 2a is the construction of a second embodiment in which partial zones are covered by a flat channel stopper layer. Afterwards, as described above for the first embodiment, the CCD is produced as far as the stage illustrated in Fig. 1 b. After separation of the photo resist mask 16, phosphorous implantation is carried out at high energy. The electrodes 12 and 15 serve thereby as a masking. The dosage is so dimensioned that in the event of subsequent use, maximum potential in the empty charge transport channel of the zone 22 attains a value 25 which is approximately that which would be obtained in the zone 11 if the electrode 12 were connected to a DC potential (e.g. 6 V), which would correspond to the arithmetical mean of high and low levels of the clock voltage travel required. The subsequently performed boron implantation at low energy produces a flat p-conductive channel stopper layer 24 in the immediate surface zone of the unmasked semiconductor zones which are only coated with the gate isolator. The layer 24 is connected to the channel stopper zones which serve for lateral demarcation and is thus electrically at substrate potential. A third electrode configuration is superfluous. The doping zones 23 produce virtually the same potential barriers as the zones 14 if the layer 24 is wafer thin. If the extent of the depression in the layer 24 is not negligible in comparison with the depth of the doping zone 14, then the potential barrier generated by the zone 23 is smaller than that produced by the zone 14. By way of further production of the CCD register shown diagrammatically in Fig. 2a, the normal stages follow as described above with reference to the first embodiment. It should be emphasised that the electrodes 12 and 15 do not have to be thermally oxidised. The layer of silox usually applied is sufficient to provide insulation from the Al guide path plane.

When the second embodiment is operating, the clock phase is applied to the electrodes 12 and 15 (which are connected to each other).

Fig. 2b shows the patterns of maximum potential in the empty transport channel. The pattern 26 occurs when the low level of clock voltage is present at the electrodes 12 and 15 while the pattern 27 results from the action of the high level. The pattern 25 is determined by the thin p-conductive layer 24 which is at substrate potential and the dopings located under it.

Claims

1. Charge-coupled device, characterised in that after structuring of a first electrode plane (with the first electrode configuration serving as a mask), there is large-area potential barrier-producing doping (doping of the same conductance type as the substrate) followed by application of a second electrode plane, the electrodes structured out of this second plane partially overlapping those of the first plane and not requiring to be insulated from these latter, and in that in certain zones of the substrate where there was initially barrier doping, a so-called compensation doping is incorporated (of the conductance type which is oppposite to the substrate), and in that the masking employed is constituted by the first two electrode configurations and an additional mask, dosage and profile of the last-mentioned compensation doping being so chosen that those areas covered by the compensation doping can function as storage zones of a CCD shift register, i.e. in that in subsequent use of the component, it is possible to produce in the charge transport channel of the areas covered by the compensation doping a potential which is suitable for storing charge carriers.

2. Charge-coupled device according to Claim 1, characterised in that to adjust the necessary potential in the active zones not covered by the first and second electrode plane, a third electrode plane is applied, this third electrode configuration preferably being constructed as one cohesive layer over the entire CCD shift register area.

3. Charge-coupled device according to Claim 1, characterised in that to adjust the necessary potential in the active zones not covered by the first and second electrode plane, a flat channel-stopper layer (of the same conductance type as the substrate) is incorporated into the surface zone of the semiconductor, so that a covering electrode becomes unnecessary in these zones.

4. Charge-coupled device according to Claim 1 and 2 or 1 and 3, characterised in that potential barrier producing zones are produced in self-aligned form under individual electrodes in that after (largearea) incorporation of a barrier doping (doping of the same conductance type as the substrate), an electrode plane is applied, the individual electrodes are structured out of it and finally the so-called compensation doping mentioned in para. 1 in incorporated, the individual electrodes (and possible other structured layers) serving as a masking.

5. Charge-coupled device as claimed in Claim 1, substantially as described herein with reference to and as illustrated by the example shown in the accompanying drawings.