GB2070858A - A shallow channel field effect transistor - Google Patents

A shallow channel field effect transistor Download PDF

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GB2070858A
GB2070858A GB8102529A GB8102529A GB2070858A GB 2070858 A GB2070858 A GB 2070858A GB 8102529 A GB8102529 A GB 8102529A GB 8102529 A GB8102529 A GB 8102529A GB 2070858 A GB2070858 A GB 2070858A
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field effect
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H01L29/6678—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates on sapphire substrates, e.g. SOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H01L29/7832—Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8086—Thin film JFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8126—Thin film MESFET's

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A field effect transistor has an elongate buried region 30, of opposite conductivity to the semiconductor layer 12, formed below the gate electrode 44. The buried region which forms a bottom gate electrically connected to the top gate electrode, where it breaks through to the electrode at the edges of the mesa layer. With this arrangement the channel of the FET has a shallow depth in the semiconductor between the gate electrode 44 and the buried layer 30. The top gate may be of the insulated, Schottky or junction type. The FET is fabricated by forming a pair of masking strips 14, 16 of insulating material on the surface of the semiconductor, forming an ion implantation masking layer between the pair of masking strips and implanting particles to establish the source and drain regions 22, 24. With such method a single masking step is used to define the source, drain and gate regions of the device, namely the masking to define the strips 14 and 16. The buried layer is formed by deep ion implantation with the source and drain masked or without masking so that there is shallow implantation under the strips 14, 16 and deep implantation elsewhere. Gate oxide may be deposited between the strips before implantation. The device may be formed in a semiconducting mesa on a sapphire or similar substrate. <IMAGE>

Description

SPECIFICATION Semiconductor devices and manufactuneg methods This invention relates to field effect semiconductor devices and manufacturing methods therefor.
As is known in the art, metal gate and junction gate field effecttransistors, sometimes referred to as MESFET and JFET devices, have been formed on high resistivity silicon, gallium arsenide, or silicon on sapphire substrates. In order to achieve efficient operation at microwave frequencies in excess of 1 GHzthe gate length should be 1 micrometer or less, the gate capacitance should be small, the depth of the conducting channel should be substantially smaller than the length of the gate in order to avoid increasing the effective conductive channel length of the device because of fringing fields, the conductive channel doping should be relatively high, (e.g. Nl = 1017 atoms/cm3), the carrier mobility in the conduc- tive channel region should be high to achieve a low on-resistance of the device, the source-drain spacing should be small (e.g. less or equal to 3 micrometers), the contact impedance should be small, and the gate leakage current should be small in order to avoid excessive loading of a drive circuit While the requirement of a very shallow conductive channel depth of 0.2 to 0.3 micrometers may be met using gallium arsenide material by forming an appropriately doped, shallow epitaxial layer on an insulating gallium arsenide substrate, and using silicon by an epitaxial or ion implanted layer on a highly resistive single crystal silicon substrate, meeting such shallow channel depth requirement is difficult where the epitaxial layer is of one material, such as silicon, and the substrate is of a different material such as sapphire. That is, complications arise in forming very shallow conductive channel depths for MESFETorJFETdevices using silicon on sapphire substrates because of the factthatthe electrical properties of the silicon film on the sapphire substrate are generally poor at and nearthe siliconsapphire interface.Consequently, while silicon on sapphire devices are theoretically highly desirable since they have greatly reduced parasitic capacitances and readily lend themselves to the fabrication of microwave monolithic integrated circuits, when such devices utilize the full thickness of the silicon the minimum thickness of the silicon, and hence the minimum thickness of the channel depth, is typically 6000 A and therefore the depth of such conductive channel is only slightly shorter than the gate length.
i#owever, if the conductive channel depth is only slightly shorter than the gate length fringing fields spread, increase the effective gate length of the device, and thereby reduce the operating frequency bandwidth of the device.
As is also known in the art, devices of the type described above are generally made by positioning a gate, 1 micrometer or less in width, with a very high degree of masking accuracy precisely between the source and drain regions, which are typically spaced 3 micrometers apart. This is a particularly difficult mask, especially if the device is shaped so that registration in two dimensions must be achieved, eg in an interdigitated structure. Such technique is usually a so-called "lift-off" technique where a layer of photoresist is deposited on the surface of the semiconductor and patterned to expose the gate of the semiconductor region.Metal is then deposited over the pbxotoresist and onto the exposed gate region. The photorneletwith metal on its surface is then lifted off.
to leave the metal gate on the semiconductor. Such technique may be useful in some applications. Flov- ever in those applications where it is desired to form a Schottky contact using a platinum deposition and a high temperature process to form platinurn-silicide priorto deposition of an aluminium metal gate con tact, the photoresist is not generally capable o7*\nri"Lh-of with standing such high temperature process thereby limiting the use of this "liFt-oT' technique.
In accordance with the present invention them is provided a field effect semiconductor device, comprising source and drain regions disposed in a semi- conductor body, a gate electrode disposed over a portion of the semiconductor body between the source and drain regions, a buried doped region hav ing a conductivity type opposite to the conductivity type of the semiconductor body disposed in the semiconductor body under, and spaced from, the said portion of the surface of the semiconductor.
In a preferred embodiment of the invention the semiconductor body is disposed on an insulating substrate, preferably a semiconductor of silicon on a sapphire substrate. A region in the semiconductor disposed between the gate and the buried doped region provides the conductive channel tor the device. The buried doped region may be formed by implanting particles deeply through the surFace of the semiconductor. During subsequent heat treat- mentthe separation between the portion of the sur face of the semiconductor body disposed over the conductive channel and the buried doped region is controlled to provide the desired, very small conductive channel depth.With such an arrangement a shallow conductive channel in a silicon on sapphire device has the conductive channel spaced from the silicon-sapphire interface so as to obtain increased operating bandwidth.
In the preferred practice of the invention, two spaced, masking members, preferably thick insulating strips, are formed on the surface of the semiconductor. A mask is deposited between the spaced insulating strips. Particles are introduced into unmasked surface portions of the semiconductor to provide the source and drain regions. The mask is then removed and a complementary mask is then formed to cover the previously unmasked portions of the semiconductor surface and to expose the region of the semiconductor surface between the insulating strips. This complementary mask provides an ion implantation mask and particles capable of establishing a conductivity type opposite to the conductivity type of the semiconductor are ion implanted through the exposed portion of the semiconductor into the underlying semiconductor to form the buried doped region of such particles spaced from the exposed portion of the semiconductor surface An additional mask is then formed bet- ween a portion of the pair of strips and overa central portion of the car:::- ---::-- capable of establishing the opposite type conductivity of the semiconductor are for implanted into exposed sur- face por:o::s of the semiconductor to provide a conductive region along the exposed surface portions of the semiconductor and into exposed portions of the buried doped region. Source and drain electrodes are provided for the source and drain regions. A gate electrode is provided having a first portion thereof disposed on the surface of the semiconductor between the insulating strips, a second adjacent portion thereof disposed on the surface of the insulating strips and a third portion thereof electrically connected to the buried doped region through the conductive region formed along surface portions of the semiconductor.
With such arrangement the gate electrode capacitance is keptto a minimum since the portion of the gate electrode extending beyond the gate region is deposited on the thick insulating strips adjacent to the gate area. In addition, alignments of the gate region with respect to the source and drain regions is facilitated since these regions are defined simultaneously by a single mask made up of the spaced masking strips and which allows one level of masking in forming the source, drain and gate regions of the device.
Further, the use of a pair of spaced, thick masking strips enables the fabrication of a self-aligned gate MOS structure where, after forming the thick masking surfaces with vertical walls and before or after implanting source and drain contact regions, a thin gate oxide layer is grown over the gate area between the spaced masking strips. Particles are then implanted at energy levels which place them in a shallow region directly under the thick masking surfaces but at a much greater depths in other regions of the semiconductor, including the gate region.
Therefore the doping characteristics of the gate region of the semiconductor are retained. The gate elec trode is then formed on the thin oxide layer formed in the region between the spaced masking strips and the source and drain regions are electrically connected to the gate region by the portions of the ion implanted region which were implanted at a shallow depth in the semiconductor beneath the thick masking surfaces.
The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which: Figs 1Ato 6A are plan views of a field effect device embodying the invention at various steps in the manufacture thereof; Figs 1 B to 6B are cross-sectional elevation views of the field effect device at various steps in the manufacture thereof, such cross-sectional elevation views being taken along the lines 1 B-1 B to 6B-6B respectively in Figs 1Ato 6A; Figs 3C to 6C are cross-sectional elevation views of the field effect device at various steps in the manufacture thereof, such cross-sectional elevation views being taken along the lines 3B-3B to 6B-6B respectively in Figs 3A to 6A; and Figs 7A to 7F are sectional views of a MOSFET device according to an alternative embodiment of the invention r stages in the manufacture thereof.
Referring now to Figs 1A and IB, a single crystai insulating substrate 10 Orsapphire, having thereon a sirnglecrystal semiconductorfilm 12 of silicon, is shown. The silicon film is an initially undoped epitax ial layer of silicon having a thickness of 0.5 to 1.5 micrometers. The silicon film 12 is next implanted with phosphorus (having a dose range of N = 2 to 8 X 1012 atoms per cm2) through a thin, 800 Athick, thermally grown silicon dioxide layer, not shown.
The implant annealed out by heaíing r the substrate @@@@@@gon, for approximately twenty minutes at 1000 C, and at the same time the phos phorus deposit is driven deeper into the silicon film to form an N type conductivity epitaxial layer or film of silicon. The 800 A thick silicon dioxide layer, not shown, is then #hotolithographically etched to serve as a mask for forming a mesa structure of silicon in a conventional manner, shown as the silicon layer 12 in Figs 1A and 1 B.
Next, the 800 A thick silicon dioxide layer is removed and the exposed surfaces of the mesashaped silicon layer 12 are oxidized in steam at 850C to form a new 800 A thick insulating layer of silicon dioxide. Thereafter a 1 micrometerto 1.5 mic rometerthick layer of silicon dioxide is chemically vapour deposited at 450% overthe entire structure, the combined silicon dioxide layers being shown in Fig 1 B as layer 13. A photoresist mask 15, is then applied to the surface of this thick silicon dioxide layer 13 and patterned to protect a pair of strip shaped surface portions of the deposited silicon dioxide layer 13.Then this silicon dioxide layer 13 is etched into silicon dioxide strips 14, 16 having a separation of 0.7 to 1.0 micrometers, a height H of 1 to 1.6 micrometers, and each one having a width W of 1.0 to 1.5 micrometers across the mesa structure and portions of the sapphire substrate 10 as shown in FIGS. 2A and 2E, using reactive ion etching in a CHF atmosphere.When done in a parallel plate ion etchw ing system the silicon dioxide layer 13 is formed into silicon dioxide strips 14, 16 having substantially ver- tical walls without undercutting the photoresist mask Because of the vertical etching the relativeiy small dimensions of the photoresist mask 15 are accurately transferred onto the silicon dioxide layer 13. As will be described hereinafter the pair of silicon dioxide strips 14, 16 are used to provide a pair of masking surfaces during formation of the source region, the drain region, and the gate region, the region 18 disposed between the strips 14,16 providing a gate window. It is noted that the relative posi tions of the source, drain and gate regions are defined to a very high degree of accuracy by a single mask, here of photoresist layer 15.
Referring now to FIGS. 3A, 3B, 3C, the region 18 FIG. 2B) is next covered by a relatively noncritical photoresist mask 20 using conventional techniques.
The source and drain regions 22, 24 are formed in the upper exposed surface portions of the silicon film 12, as shown in FIG. 38, by ion implanting arsenic or phosphorus with a dose of N 5 5 :~ 104" atoms percm2 to form N - type conductivity regions 22, 24.
Referring now to FIGS. 4A, 4B and 4C, the photoresist layer 20 is removed and a photoresist mask 26, complementary to photoresist mask 20 (FIG. 3A) is formed over the structure as shown and is used to provide an ion implantation mask to cover the source and drain regions 22,24. Boron ions are implanted into the portion of the silicon film exposed by the photoresist mask 26, i.e. into the portion exposed by window 28 to form a buried region 30.
The photoresist mask 26 thereby provides a cover or mask to shield such source and drain regions 22,24 against the deep boron implant. The buried region 30 is thus formed in the silicon film 12 beneath the portion of the surface of such silicon film disposed between strips 14, 16 and exposed by a window 28 formed in mask 26. It is noted that the buried region 30 is buried beneath the exposed surface of the silicon film 12 and is separated from such surface a depth D, here =5000 A. The boron is implanted into the exposed portion of the silicon film 12 with a dosage of N =5 5 x 1013 atoms per cm2 at an implantation energy level of 180 KeV.It is also noted that portions 30a of such regions are actually implanted into the sapphire substrate, as indicated, because the silicon film is thinner at the side peripheral portions than in the central, upper portions.
Referring now to FIGS. SA, 5B and 5C, a photoresist mask 32 is formed over the central surface portion of the silicon mesa, as shown, with the photo resist layer 26 remaining on the structure as shown. That is, the mask 32 covers a portion of the window 28 FIGS. 4A, 4B in mask 26 to expose separated upper and lower portions 28a, 28b of the surface of the silicon film 12, as shown in FIG. 5A. The masks 26,32 together provide an ion implantation mask.In particular, boron is implanted into upper surface portions of the exposed upper and lower portions 28a, 28b of the silicon film to provide conductive regions 38 which extend over portions of the upper surface and side surfaces of the silicon film 12 and onto electrical connecting peripheral portions of the buried region 30, as shown in FIG. SC.
Any implant damage resultirfg is then annealed again by heating the structure in argon at 1000 C.
During this heating step the implanted boron is activated to form a p-type conductivity region. The p-type doped regions diffuse into the silicon film 12 and, in particular, the portion of the p-type doped region buried beneath the silicon surface, i.e. region 30, diffuses towards the upper outer surface of the silicon film 12. The heating is terminated when the depth of the junction between buried region 30 and the silicon film 12 has moved to a depth D', equal to the desired conductive channel depth, here 2000 to 3000 A below such outer surface as shown in FIG.
6B. It is noted thatthe channel depth D', here 2000 to 3000 A is much smaller than the gate length, here 7000 to 10,000 A with the conductive channel region 31 being disposed between the upper surface of the silicon film 12. It is further noted that the buried region 30 is spaced from the silicon film 12-sapphire substrate 10 interface and hence such conductive channel region 31 is in the portion ofthe silicon film 12 having good electrical characteristics.
Referring now to FIGS. 6A, 6B and 6C, source and drain electrodes 40, 42 are formed in ohmic contact with the source and drain regions 22, 24, respectively, using conventional techniques. A gate electrode 44 is formed with a Schottky contact to the portion of the surface of the silicon film disposed between silicon dioxide strips 14,16, as shown. It is noted that such gate electrode 44 is in ohmic contact with the p-type doped regions 38 and hence is electrically connected to the buried p-type buried doped region 30 as shown in FIG. 6C.
Here the gate electrode 44 is formed by first depositing a layer of platinum, not shown, heating such platinum to form platinum silicide in the gate region, removing the remaining portions of the platinum layer and then depositing a titaniumtungsten layer followed by an aluminium layer, all in accordance with well known practice to form a Schottky barrier contact.
Because of the use of a pair of relatively thick masking surfaces, i.e. because of the use of insulating silicon dioxide strips 14, 16 (FIG. 2B), it has been found that it is possible to confine the gate metallization entirely to the narrow gate region even through the photoresist mask for the gate metal may be somewhat wider than the gate length. This is accomplished by using photoresist of relatively low viscosity. When this is spun on at sufficient speed, the photoresist layer is correspondingly thin.
Because of the vertical and deep silicon dioxide strips 14,16 adjacent to the gate region, photoresist is drained into the narrow space between the strips 14, 16 forming a thicker coating over the gate, and a very thin or discontinuous coating on the surface of the thick silicon dioxide strips. When the metal is etched, the thin portion of the photoresist coating offers little protection, and thus the metal overlap on the surface of the strips is automatically removed but the metal between the strips is additionally protected by the drained photoresist.
Instead of platinum silicide, other methods can be used to form Schottky barriers. One consists of simply depositing aluminium, silicon doped aluminium, Ti-W-AI, or CrAu onto the bare silicon in the gate region. A more reliable Schottky contact offering a reduced leakage current can be made by first forming a very thin oxide layer, 20-60A thick, on the silicon before deposition of the metal. This thin oxide layer can be formed conveniently in an oxygen plasma, or by thermal oxidation (e.g. in steam at S00-600#C). In another variation of gate formation a very shallow p-n junction may be formed instead of a Schottky barrier to provide a JFET device.
The device described in this disclosure is also suitable for enhancement type MESFET's orJFET's. To this end, the depth of the channel region is made sufficiently shallow, and the doping of the active channel region is made sufficiently light so that the channel is depleted at zero applied gate voltage on account of the contact potential between the gate and the n-type channel. With the buried region present, the depletion of the channel region is very efficient since it occurs from two sides.
The fabrication method and structure described in this disclosure can be employed to fabricate self aligned gate MOS structures. Referring to FIG. 7A a p-type conductivity silicon film 12' is shown formed as a mesa type structure on a sapphire substrate 10' as shown using processing techniques described above in connection with FIGS. A and 1 B. A layer of silicon dioxide 13' is formed over the surface of the structure as shown.A mask is formed of a layer 15' of photoresist as shown in FIG. 7A. A suitable etchant is then brought into contact with the portions of the silicon dioxide layer 13' exposed by the photoresist layer 15' to form a pair of silicon dioxide strips 14', 16' as shown in FIG. 7B. Here such etchant is the reactive ion etching process described above in connection with FIGS. 2A and 2B. As noted above the mask provided by the photoresist layer 15' defines the source, drain and gate regions of the device.
Next, a layer 20' of photoresist is disposed in the region between the pair of strips 14', 16' as shown in FIG. 7C. Phosphorus or arsenic ions are then implanted to form the n-type conductivity source and drain regions 22', 24' of the device as shown in FIG. 7C. A gate oxide, here a layer 50 of silicon dioxide, is grown over the surface and then removed except from the portion of the surface over the gate region to provide the structure shown in FIG. 7D.
Phosphorus ions 52 are then ion implanted at an energy which puts them into shallow regions 54 of the silicon film 12' located directly under the thick silicon dioxide strips 14', 18' as shown in FIG. 7E. In contrast, since the gate region is covered only by a thin silicon dioxide layer 50, the implant will go deep into the gate region and beneath the source and drain regions 22', 24' as shown. Therefore, the p-type conductivity of the silicon 12' is retained in a region underthe gate oxide and it will determine the threshold of the MOSFET. The source, drain and gate electrodes are applied in any conventional manner as shown in FIG. 7F. Having described preferred embodiments of this invention, it is now evident that other embodiments incorporating these concepts may be used. For example, while the devices described herein are silicon on sapphire devices, a field effect device formed with a buried doped region may be formed on devices made of other materials such as gallium arsenide epitaxial layers formed on semi-insulating gallium arsenide substrates. Further, while the insulating strips are here shown as silicon dioxide strips, they may be formed of insulating polycrystalline silicon material.

Claims (16)

1. A field effect semiconductor device, comprising source and drain regions disposed in a semiconductor body, a gate electrode disposed over a portion of the semiconductor body between the source and drain regions, a buried doped region having a conductivity type opposite to the conductivity type of the semiconductor body disposed in the semiconductor body under, and spaced from, the said portion of the surface of the semiconductor.
2. Afield effect device according to claim 1, including a substrate supporting the semiconductor body, the substrate being of a material different from the material of the semiconductor.
3. A field effect device according to claim 2, wherein the substrate and the semiconductor body are single crystal materials.
4. A field device according to claim 3, wherein the semiconductor body is a mesa layer on the substrate and the buried doped region is an elongated region extending right across the mesa layer.
5. A field effect device according to any of claims 1 to 4, wherein the gate electrode is electrically connected to the buried doped region.
6. A field effect device according to claim 5, wherein the buried doped region is electrically connected to the gate electrode by a further conductive region in the semiconductor body.
7. A field effect device according to claim 6, insofar as dependent on claim 4, wherein the further conductive region is at the or each end of the buried doped region, at the edge of the mesa layer where it breaks through to contact the gate electrode.
8. A field effect device according to any of claims 1 to 7, wherein the source and drain regions flank two insulating, spaced strips disposed on the semiconductor body, the said portion being defined between the strips.
9. A field effect device according to claim 8, wherein a gate oxide insulator is disposed between the strips on the said portion.
10. A method of making a field effect device, comprising the steps of forming a pair of spaced insulating members on the surface of a semiconductor body, forming a masking layer over a region of the surface of the semiconductor body between the insulating members, implanting particles to establish source and drain contact regions through portions of the surface of the semiconductor not covered by the masking layer, removing the masking layer, and forming a gate electrode over the region between the insulating members.
11. A method according to claim 10, wherein the semiconductor body is silicon and the spaced insulating members are a compound of silicon.
12. A method according to claim 10 or 11, wherein a buried doped layer is formed in the region between the insulating members by ion implantation after removing the masking layer.
13. A method according to claim 12, wherein the ion implantation is effected with the source and drain regions masked.
14. A method according to claim 12, wherein the ion implantation is effected with the source and drain regions unmasked and at an energy level such that shallow implantation occurs under the insulating members and deep implantation elsewhere.
15. A method of making a field effect device, comprising the steps of forming a pair of spaced insulating members on the surface of a semiconductor body, implanting particles in the regions of the semiconductor body under the insulating members to electrically connect the source and drain regions of the device to a gate region disposed under a region of the surface of the semiconductor between the insulating members, and forming a gate electrode between the pair of spaced insulating members.
16. A method of making a field effect device substantially as hereinbefore described with reference to and as illustrated in Figs 1Ato 6C or Figs 7 to 7F of the accompanying drawings.
GB8102529A 1980-03-03 1981-01-28 Shallow channel field effect transistor Expired GB2070858B (en)

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US12678780A 1980-03-03 1980-03-03

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GB08326563A Expired GB2140616B (en) 1980-03-03 1983-10-04 Shallow channel field effect transistor

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GB (2) GB2070858B (en)

Cited By (3)

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FR2527385A1 (en) * 1982-04-13 1983-11-25 Suwa Seikosha Kk THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY PANEL USING THIS TYPE OF TRANSISTOR
GB2133621A (en) * 1983-01-11 1984-07-25 Emi Ltd Junction field effect transistor
FR2663464A1 (en) * 1990-06-19 1991-12-20 Commissariat Energie Atomique INTEGRATED CIRCUIT IN SILICON-ON-INSULATION TECHNOLOGY COMPRISING A FIELD-EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD.

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JPS5873165A (en) * 1981-10-27 1983-05-02 Sumitomo Electric Ind Ltd Schottky gate field effect transistor and manufacture thereof
JPS5879771A (en) * 1981-11-06 1983-05-13 Sumitomo Electric Ind Ltd Semiconductor device and manufacture thereof

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GB1155578A (en) * 1965-10-08 1969-06-18 Sony Corp Field Effect Transistor
US4063271A (en) * 1972-07-26 1977-12-13 Texas Instruments Incorporated FET and bipolar device and circuit process with maximum junction control
GB1507091A (en) * 1974-03-29 1978-04-12 Siemens Ag Schottky-gate field-effect transistors
JPS5381087A (en) * 1976-12-27 1978-07-18 Fujitsu Ltd Gallium aresenide field effect transistor
NL184552C (en) * 1978-07-24 1989-08-16 Philips Nv SEMICONDUCTOR FOR HIGH VOLTAGES.
JPS55153377A (en) * 1979-05-18 1980-11-29 Matsushita Electronics Corp Production of semiconductor device
FR2460543A1 (en) * 1979-06-29 1981-01-23 Radiotechnique Compelec FIELD-TYPE FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
JPS5658259A (en) * 1979-10-18 1981-05-21 Toshiba Corp Semiconductor device and production thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2527385A1 (en) * 1982-04-13 1983-11-25 Suwa Seikosha Kk THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY PANEL USING THIS TYPE OF TRANSISTOR
GB2133621A (en) * 1983-01-11 1984-07-25 Emi Ltd Junction field effect transistor
FR2663464A1 (en) * 1990-06-19 1991-12-20 Commissariat Energie Atomique INTEGRATED CIRCUIT IN SILICON-ON-INSULATION TECHNOLOGY COMPRISING A FIELD-EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD.
EP0462882A1 (en) * 1990-06-19 1991-12-27 Commissariat A L'energie Atomique Thin film field effect transistor with buried gate and its method of fabrication
US5130770A (en) * 1990-06-19 1992-07-14 Brevatome Integrated circuit in silicon on insulator technology comprising a field effect transistor

Also Published As

Publication number Publication date
GB2140616B (en) 1985-06-19
DE3107909A1 (en) 1982-03-25
GB2070858B (en) 1985-02-06
GB8326563D0 (en) 1983-11-02
JPS56135977A (en) 1981-10-23
GB2140616A (en) 1984-11-28

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