JPS5879771A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve a high-frequency characteristic, to increase gate reverse dielectric resistance and to ameliorate yield by thinning only an operating layer just under a gate and forming the operating layer and a gate electrode at the same position. CONSTITUTION:A gate metal 25 is shaped at the inside and electrodes 23, 24 at the outside while being fast stuck to walls through the walls 27 consisting of an insulating inorganic compound at a high aspect ratio to an operating layer 22. Each electrode is formed through self-alignment to the walls, and a distance between the electrodes can minutely be controlled with high accuracy according to the film thickness of the walls 27. The titled device is molded in structure, in which the thickness of the operating layer 22' just under the gate is made thinner than the thickness of an operating layer 22'' between a source and a drain, and on the basis of a pattern of which the layer 22' and the electrode 25 are composed of the same insulating material. Accordingly, the positional relationship of the electrode 25 and the layer 22' is automatically determined, and yield is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same.

The present invention is not limited in any way to materials, and can be applied to a wide range of general semiconductor materials such as single-element semiconductors such as Si or compound semiconductors. Explanation will be given using GaAs among semiconductors as an example.

The general structure of a conventional Schottky gate field effect transistor is as shown in the cross-sectional view of FIG.
After forming an n-type active layer 12 with a thickness similar to - on the surface of a semi-insulating semiconductor substrate 11 such as by epitaxial growth or ion implantation, a source electrode i18, etc. is formed by depositing metal on the surface of this active layer, etc. Rain Electric [i14
and a Schottky gate electrode 15 are formed.

In such a conventional Schottky gate field effect transistor, if the gate-source resistance is large,
It is known that the microwave characteristics, particularly the noise characteristics, of this transistor deteriorate. To improve microwave characteristics, it is necessary to lower the gate-source resistance.
To achieve this objective, it is necessary to increase the carrier concentration in the active layer 12 or to increase the thickness of the active layer, but either method causes the problem that the pinch-off voltage becomes excessive. Further, when the carrier concentration is increased, another problem arises in that the breakdown voltage of the gate decreases.

In order to solve this problem, as illustrated in FIG.
A structure has been proposed in which the thickness of the active layer 12' near the source electrode is increased while the thickness of the active layer 12' is maintained at a desired value. This structure is achieved by first forming an active layer with a uniform thickness corresponding to the thickness directly under the source electrode 18 and drain electrode 14, and then thinning only the portion 12' that should be directly under the gate electrode 15 by etching or the like. , forming respective electrodes 18, 14 and 15.

However, such a structure has the disadvantage that the yield is low because extremely strict precision is required for etching control of the active layer.

In addition, since the surface of the active layer is not flat, it becomes difficult to perform fine photolithography for forming electrodes, which causes the following problems in improving the characteristics of field effect transistors (hereinafter abbreviated as MESFET). be.

In order to improve the high frequency characteristics of a MESFET, it is necessary to reduce the gate length as much as possible, which requires extremely fine precision machining in device fabrication.

However, in the manufacturing method shown in FIG.
When forming a pattern in the resist, a source electrode 18 and a drain electrode 1 are formed in the vicinity of the gate pattern.
4 exists in addition to the step in the mesa region 12'', the resolution of the photoresist pattern is lower than that on a flat surface, making it difficult to reliably form a gate pattern as short as IItm. Especially Ga
In compound semiconductors such as As, it is common practice to perform alloy treatment on the source electrode 18 and drain electrode 14 before forming the gate electrode 15 in order to lower the contact resistance. If the alloying process is carried out at a sufficiently high temperature and for a long period of time, the source and drain electrode metals will agglomerate, resulting in the formation of extremely large steps, which also causes a deterioration in the resolution of the gate photoresist pattern. ing.

Further, the gate electrode 15 needs to be formed between the already formed source electrode 18 and drain electrode 14 with a positional accuracy of ±0.21 tm or less. Furthermore, the source electrode 18
The distance between the gate electrode 15 and the gate electrode 15 is in the electrical characteristics of the MESFET and directly affects the parasitic resistance and capacitance between the source and gate, so the distance between the two electrodes must be kept as small as possible and controlled with high precision. The above-mentioned positional accuracy is also required in terms of the distance between the electrodes. However, it is extremely difficult to form such fine patterns with high precision using conventional techniques, and therefore there is a problem in that the manufacturing yield is extremely low.

As described above, with conventional methods, it is extremely difficult to manufacture with a high yield and a gate length of less than lItm and a source-to-gate distance with an accuracy of l/10 μm.

The present invention aims to improve these drawbacks of the conventional method, and its purpose is to manufacture MESFETs with high precision and high yield, having a gate length of 1 μm or less and a source-to-gate distance. Furthermore, in the present invention, only the active layer directly under the gate is thin, and the active layer directly under the gate electrode and the gate electrode are formed in the same position, so high frequency characteristics are good, the gate reverse breakdown voltage is high, and the yield is low. Good MES
The FET can be realized through a simpler process than the conventional method.

The details of the present invention will be explained below with reference to Examples.

FIG. 3 shows a semiconductor device as an example of the present invention. In the figure, a gate metal 25 is placed inside the wall through a pair of walls 27 made of an insulating inorganic compound formed with a high aspect ratio on an active layer 22 formed on a semiconductor substrate 21, and a gate metal 25 is placed on the outside of the wall. A source electrode 23 and a drain electrode 24 are formed in close contact with the walls, respectively. Each electrode is formed in self-alignment with respect to the wall, and the distance between the electrodes can be precisely controlled by adjusting the thickness of the insulating compound. Further, as illustrated in FIG. 3, the MESFET of the present invention has a structure in which the thickness of the active layer 22' directly under the gate is smaller than the thickness of the active layer 22' between the source and drain, and the active layer 22' directly under the gate The gate electrode 22' and the gate electrode 25 are formed using a so-called self-alignment method in which the gate electrode 22' and the gate electrode 25 are formed based on patterns made of the same insulating material. Therefore, the positional relationship between the gate electrode 25 and the first layered portion 22' is automatically determined. Therefore, the structure of the present invention has manufacturing advantages such as simplifying the manufacturing process, improving yield, and enabling fine processing.

Next, FIG. 4 shows an example of the semiconductor manufacturing method of the present invention.
The explanation will be based on.

First, as shown in FIG. 4(4), an active layer 22 having a uniform thickness is formed on the surface of a GaAs semi-insulating substrate 21 by vapor phase or liquid phase growth or by implantation of ions such as Si+. The thickness and carrier concentration of this active layer are selected to such a value that the depletion layer extending to a portion other than directly below the gate does not increase the gate-source resistance. Next, when the active layer is formed by ion implantation, the implanted elements are activated by annealing.

Next, as shown in FIG. 4(B), a wall of an inorganic compound is provided on the active layer 22. First, the surface of the operating layer 22 has a thickness of 1.6 μm.
An inorganic compound film 27 of m is formed (B-a in the same figure). In this case, in order to increase the aspect ratio with a fine pattern, reactive sputter etching was used in this embodiment, which can form a nearly vertical wall pattern. SiOg is deposited by sputtering as an inorganic inorganic compound film 27, and a metal mask pattern 28 with a spacing of 0.4 μm and 0.6 μm is formed thereon by lamination and lift-off, such as electron beam exposure technology (FIG. 1B). -b). 5
For inH, etching was performed using a 15ooX Al mask as a mask and a plasma containing CF mixed with 5% O11 and gas at 0.8 Torr (B-C in the same figure). Similar fine processing is possible for other inorganic compound films by appropriately selecting the combination of etching gas and mask material, and the material is not limited to Sing. Thereafter, if necessary, the metal mask 28 was removed to obtain a pair of walls of inorganic compound films with a high aspect ratio and a vertical cross section necessary for the present invention (FIGS. 4(B)-(d)).
.

After this (as shown in FIG. 4(C), an Au-Ge-Ni alloy was vacuum-deposited on the mesa region other than the part sandwiched between the pair of walls 27 by an oblique evaporation method at 375°C.
Heat treatment is performed in N gas (including 596 Hz) for -2 minutes to improve the ohmic properties of the source electrode ε8 and the drain electrode 24.

Next, as illustrated in FIG. 4 (9), inactivation ions are implanted using the source electrode 23, drain electrode 24, and insulating inorganic compound film 27 as masks, and inactivation is performed in the unmasked areas. Then, a working layer 26 is formed. Visit,
The ions to be implanted are ions capable of inactivating the active layer, and the object of the present invention is met if the inactivating function is not lost even after the step of forming the gate electrode 25.

In this example, oxygen was used as the inactivation ion, but
FIG. 5 shows a situation in which an active layer having a sheet resistance of 150 Ω10 is made to have a high resistance by O+ ion implantation.

Note that as the inactivation ion, chromium or boron can also be used in addition to oxygen.

By implanting these passivating ions, the pinch-off voltage can be set to a desired value by reducing the effective thickness of the active layer 22' or by reducing the carrier concentration.

Finally, as shown in FIG. 4(6), Schottky electrode metal 25 is deposited to form an FET. In the example, 400OA
of Ti was formed by a vacuum evaporation method.

In the above embodiments, GaAs is used as the semiconductor crystal, but if necessary, InP or other materials may be used.
-V group compound semiconductors, Si, and other arbitrary semiconductors can be used, and the present invention can be broadly applied to these materials. The metal for the Schottky electrode can also be selected depending on the respective semiconductor material. The same applies to ohmic electrodes.

On the other hand, for etching, 1 μm with vertical walls
It is necessary to form a fine pattern of a certain size in a thick film, and for this purpose, the use of reactive gas plasma or active grasshopper etching is most suitable. In the examples, the Sing film was etched with CF 410 s gas, but it is also possible to use other inorganic compounds, such as CHF.

Reactive grasshopper etching with gas is also possible.

Further, as the material for forming the insulating inorganic compound film, it is also possible to use a metal that forms an insulating compound film on the surface.

The metal that serves as the base material for forming a pair of walls made of an insulating inorganic compound film can be processed into a thick film pattern with a vertical cross section, and an insulating compound film made of itself can be formed on the surface. required to obtain. As long as this requirement is met, the choice of material is arbitrary.Ts sMo g
kl gW etc. can be considered. Methods for forming an insulating compound on the metal or semiconductor itself include forming an oxide film by anodic oxidation, plasma oxidation, thermal oxidation, etc., and forming a nitride film by plasma nitridation. The purpose of the present invention can only be achieved by selecting a method that can form a compound film that is excellent in mechanical strength and heat resistance, chemically stable, uniform, and electrically insulating. , any method is possible.

Next, to explain the relationship between the length of the active layer 22' and the length of the gate electrode 25, in the normally-on type where the active layer 22' is relatively thick, the length of the active layer 22' is the same as that of the gate electrode 25.
Practically sufficient characteristics can be obtained even if the length is slightly longer than .

This is because the active layer 22' is relatively thick, so the thickness of the depletion layer that spreads from the surface into the inside of the device does not account for the entire thickness of the active layer 22'. This is because the problem of extremely increasing source-to-source resistance does not occur. On the other hand, in the normally-off type in which the depletion layer thickness from the surface occupies the entire layer thickness of the active layer 22', the length of the active layer 22' is the length of the electrode 25, as illustrated in FIG. If it is larger than The problem arises that it is blocked.

Therefore, in the normally-off type, the length of the gate electrode 25 must be longer than the operating layer 22'. However, in the overlapping portion of the gate electrode 25 and the active layer 22', that is, in the gate electrode 25, the active layer 22'
A portion that is longer than the capacitance simply increases the capacitance and has no effective effect. Therefore, it is effective to shorten this portion as much as possible in order to increase the operating speed of the element. be. That is, ideally, as illustrated in FIG. 8, it is an effective means to form the length of the gate electrode 25 and the length of the active layer 22' to be equal, especially in the normally-off type.

In the present invention, the length of the insulating film 27 and the length of the gate electrode Q5 are equal to each other due to the self-line.
In addition, since they are formed at the same position, normally-off characteristics are significantly improved.

As described above, according to the present invention, the gate length is 1 μm or less, the source-gate distance is 1 μm or less, and the active layer directly under the gate has a thickness that provides a predetermined pinch-off voltage.
An MBSFET having a structure in which the active layer between the source and drain is thicker can be manufactured with a high yield.

[Brief explanation of the drawing]

1 and 2 are cross-sectional views of a conventional example, FIG. 8 is a cross-sectional view of an embodiment of the present invention, and FIGS. FIG. 5 is a diagram showing the dependence of the implantation amount of passivating ions to increase the resistance due to the implantation of passivating ions. 21... Semi-insulating semiconductor substrate, 8B... Operating layer, 2
2'... First part of the active layer, 22'... Second part of the active layer, 28... Source electrode, 24... Drain electrode, 25... Gate electrode, 26... - Inactivated operating layer, 27... Insulating inorganic compound film, 28...
・Metal pattern for etching. Figure 72Figure 3Figure 74 (A) (B) (C) CD) (E) Patent Application No. 178536 2. Name of the invention: Semiconductor device and method of manufacturing the same. 3. Relationship with the amended person's case. Patent applicant address: Name (21), 5-15 Kitahama, Higashi-ku, Osaka.
B) President and Representative Director of Sumitomo Electric Industries, Ltd. Kamei
Tadashi Futun Agent Address: 6, Sumitomo Electric Industries, Ltd., 1-1-8 Shimaya, Konohana-ku, Osaka City, Detailed description of the invention in the specification subject to amendment, Brief description of the drawings, and Drawing 7. Contents of the amendment (1) In the first line of page 7 of the specification, "Fig. 3 is" was changed to "Fig. 3 is".
and correct it. (2) "Fig. 4" on page 8, line 8 of the specification is corrected to 1, 4, and 1. (8) Page 8 of the specification, lines 14 to 15 [(B-
a) Correct J to "(in Figure 4))". (4) "(B-b in the same figure), 1" on page 9, line 2 of the specification
is corrected to "(Figure 4 (q)").
Figure 4: 0)”. (6) 1 (Figure 1゜ (uniform (d)) J in lines 11 to 12 on page 9 of the specification is corrected to "(Figure 4 @)". (7) Page 9 of the specification Correct “(Fig. 4 0)” in line 13 to [Fig. 4 [F]]. (8) Correct “(Fig. 4 [F]” on page 9 of the specification, (9) 1 boron 1 on page 10, line 11 of the specification is corrected to 1 boron.
Correct it to "Fig. 4 0". (b) Page 14 of the specification, line 14, Figure 1)~(+;
+ + is corrected to "Fig. 4 (2) to 0". 7'r4 Figure (A) (B) (E) Chibu (G) de] 23~F Gate Lr Yajuzuki) 1r]. Mi 4 2 I 4 2

Claims (2)

[Claims] (1) In a Schottky gate field effect transistor comprising a semi-insulating semiconductor substrate, an active layer formed on the surface of the semiconductor substrate, and a source electrode, a Schottky gate electrode, and a drain electrode formed on the active layer, The active layer has a first portion formed directly under the gate electrode and has a thickness such that a predetermined pinch-off voltage is applied by implanting passivation ions, and a thickness larger than the thickness of the first portion. (1) a second part having a gate electrode formed at the same position as the first part; A pair of walls extending in one direction, a Schottky barrier electrode formed between the walls,
A semiconductor device comprising ohmic electrodes formed on both sides of the wall in close contact with the wall. (2) On the surface of the semiconductor material) A step of forming a pair of walls made of a ζ inorganic compound film, a step of forming ohmic electrodes only on both sides of the walls, and implanting inactivation ions with the ohmic electrodes as a substitute. 1. A method for manufacturing a semiconductor device, comprising a step and a step of forming a Schottky electrode.