GB2133621A - Junction field effect transistor - Google Patents
Junction field effect transistor Download PDFInfo
- Publication number
- GB2133621A GB2133621A GB08334364A GB8334364A GB2133621A GB 2133621 A GB2133621 A GB 2133621A GB 08334364 A GB08334364 A GB 08334364A GB 8334364 A GB8334364 A GB 8334364A GB 2133621 A GB2133621 A GB 2133621A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- gate
- source
- field effect
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 9
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims description 15
- 230000003064 anti-oxidating effect Effects 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910007277 Si3 N4 Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009828 non-uniform distribution Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
A junction field effect transistor has a substrate 10 forming a junction with a layer of semiconductor material 9 which has a gate 14, a source 12 and a drain 13 therein, the thickness of the layer underlying the source 12 is substantially greater than that underlying the gate 14 (for example the ratio of layer thickness below the gate to that below the source is 1 to 2.53) in order to reduce the parasitic resistance as compared to conventional JFETs. <IMAGE>
Description
SPECIFICATION
Junction Field Effect Transistor
The present invention relates to a junction field effect transistor (JFET) and to a method of manufacturing a
JFET.
A known form of JFET has a P±type silicon substrate on which an n-type silicon channel has been epitaxially grown. Spaced along the upper, exposed surface of the n-type layer are diffusion regionsforming a source, a top gate and a drain. The portion of the n-type layer between the source and the top gate forms a parasitic resistance effectively in series with the channel and can cause degrading of the JFET's performance, particularly concerning its transconductance and thermal noise characteristics.
The present invention provides a junction field effect transistor comprising a substrate of semiconductor material forming a junction with a layer of semiconductor material which has a gate, a source and a drain therein, the thickness of semi-conductor layer underlying the source being substantially greater than that underlying the gate.
in this way, the thickness of semi-conductor material (for example n-type material) below the gate is at the magnitude necessary for the JFET to perform while ensuring that elsewhere the thickness of the n-type material is greater; as the parasitic resistance between the source and gate is inversely proportional to the thickness of n-type material below the source, the present invention provides a JFET with a lower parasitic resistance than previously.
Although conventional JFETs have some increase in n-type thickness below the source as compared to below the gate due to the thickness of the gate itself, the amount of increase (less than 1,um) is small com- pared to that of the present invention; also the increase in the conventional JFET is not intended to, and does not, have any significant effect on the parasitic resistance. In the present invention, the ratio of n-type layerthickness below the gate to that thickness below the source may be between 1 to 1.75 and 1 to 3.5, preferably between 1 to 2 and 1 to3.
Another aspect of the present invention provides a method of manufacturing ajunctionfieldeffecttrans- istor comprising:
depositing a first layer of semiconductor material on a substrate of semiconductor material to produce a junction,
forming an anti-oxidation layer over the first layer such that a portion ofthefirst layer remains exposed,
effecting diffusion of the layered substrate under oxidation conditions to provide the first layer with a
region of substantially greater thickness than that underlying the exposed portion.
Preferably the anti-oxidation layer is formed by applying (e.g. by sputtering or evaporating) a suitable
material on the first layer, and then removing a portion of the anti-oxidation layer (e.g. by photolithography).
In one method, particularly suited to mass production, the first layer and anti-oxidation layer are applied to a wafer of substrate and then portions of the anti-oxidation layer are removed such that a number of transverse windows, exposing the top of the n-type layer, extend across the strip. An initial diffusion step is then made in order to at least partially split the n-type layers into separate segments corresponding to the segments of anti-oxidation layer between the windows. Then a further window (which eventually results in formation of the gate) is cut in each segment of the anti-oxidation layer, and the final diffusion step is done. If not already achieved, this diffusion step completes formation of the n-type layer into segments separated by p±type material.Finally, the substrate and the layers are cut along the axes of the transverse windows, thereby resulting in a number of completed JFETs.
Preferably the anti-oxidation layer comprises silicon nitride.
In any form of the invention, a layer may be disposed between the first layer and the anti-oxidation layer to minimise stress at the interface of these layers which might otherwise occur. This layer may be silicon oxide.
In order that the invention may be more readily understood, a description is now given, by way of example only, reference being made to the accompanying drawings in which Figures 1 to 4 show schematically a silicon wafer in cross-section during stages in the manufacture of a JFET embodying the present invention.
A p±type silicon wafer of ( 100) orientation is used as a substrate 1 for construction of a number of J FETs embodying the present invention. An epitaxial layer 2 of n-type silicon is grown on one side of substrate to a thickness of 6,um such that a p-n junction is formed between them. The exposed surface of layer 2 is then covered by a layer 3 of silicon oxide (Si 02) which is used to minimise the stress that would otherwise occur due to the interface between layer 2 and subsequent layer 4 of silicon nitride (Si3 N4). This layer 4 of thickness 0.1#m prevents oxidation of the upper surface of layer 2 and inhibits diffusion of the layer 2 in the later stages of the manufacture.
Using conventional photo-lithographic techniques, strips of the layers 3 and 4 are cut out such that a lattice pattern of exposed layer 2 exists, the resulting segments of layers 3 and 4 corresponding to what will eventually be individual components.
Thus the layers 3 and 4 now form a mask with windows 5, the substrate being as schematically shown in Figure 1. Boron is then deposited on the wafer by evaporation for one hour while the wafer is maintained at a temperature in the range of 950 to 1250 C, sothat diffusion occurs at the exposed portions of the n-type layer 2 resulting in regions 6 of p-type silicon within the n-type layer 2 (see Figure 2).
This Figure also shows the completion of the next stage, in which a window 7 is cut in each segment of layers 3 and 4 so that more of the layer 2 is exposed.
Each window 7 will result in the formation of a gate region in due course.
Then the wafer is submitted to the main diffusion step under oxidising conditions. The material underlying the nitride layers has the intrinsic value of diffusion coefficient for that material. However enhanced diffusion occurs in the material underlying the surfaces of the n-type layer 2 which are oxidising i.e.
those- which have no overlying nitride layer 4; the diffusion coefficient in this material is three times the intrinsic value. Thus as the end of the diffusion step there is a non-uniform distribution of p-type material in the wafer (see Figure 3), the enhanced diffusion underlying windows 5 having partitioned the n-type layer 2 into isolated segments which in due course will form individual JFETS. Also the enhanced diffusion underlying window7 has produced a region 8 of a p-type material extending into the n-type material relative to the remainder of the p-type material. A conventional JFET of identical characteristics (except, of course, for parasitic resistance) to the illustrated JFET would have a n-type la#yer of uniform thickness equivalent to the thickness of the n-type
layer between window 7 and region 8.By providing a J FET with a n-type layer of non-uniform thickness, the present invention results in a reduced parasitic resistance for a transistor of a given performance.
A mask exposing substantially only window 7 is
placed over the layer4 and boron is then deposited on the n-type material by evaporation to form the gate.
The silicon nitride layer 4 is stripped off the source
and drain regions are then formed and the substrate
is cut along the axes of the windows 5 thereby
separating the completed JFETs. Figure 4 shows
schematically a completed JFET prior to cutting; the
JFET has a n-type layer 9 ofthickness3.8#mwhich is
enclosed in a p-type layer 10 and a silicon oxide layer 11. Regions ofthe n-type layer 9 form a source 12 and
a drain 13. Some p-type material also extends into
this n-type layer 9 to form a gate 14. Each of the.
source 12, drain 13 and gate 14 has an aluminium
contact 15. The n-type layer 9 has a thickness of 1 .5#m underlying the gate 14, so the ratio ofthickness
under the gate to thickness under the source is 1 to 2.53. In a conventional JFET without a region 8, there would be a slightly greaterthickness#underthp#sour,ce than that under the gate due to the thickness of the
p-type material (0.7,am) forming gate 14, butthispro-
duces a ratio of only 1 to 1.47.
Thus, the parasitic resistance of the above
described JFET embodying the present invention is
0.58 that of the described cnventional JFET.
A transistor made by the process described above
may generate less low frequency noise than a con
ventional transistor. It is believed that this is because
the silicon nitride layer acts as a form of barrier
against impurities contaminating the silicon layers
below; thus there may be a reduction in the number
of defects produced in the material ofthe transistor as compared to a conventionally made-transistor,-such
defects being responsible for the generation of low
frequency noise. For example, taking the comparison
of transistors mentioned above the JFET embodying
the invention has approximately a 20% reduction in
the low frequency noise as compared to the conven
tional JFET.
A JFET embodying the present invention can have a p-type epitaxial layer on an n±type silicon
substrate.
Claims (9)
1-. ~ A junction field effect transistor comprisirlg asubstrate of semiconductor material forming a junction with a layer of semiconductor material which has a gate, a source and a drain therein, the thickness of semi-conductor layer underlying the source being substantially greater than that underlying the gate.
2. A transistor according to Claim 1, wherein the ratio of semiconductor layerthickness below the gate to that thickness below the source is in the range between 1 to 1.75 and 1 to 3.5.
3. A transistor according to Claim 1, wherein the ratio ofsemiconduc;tor layerthickness below the gate to that thickness below the source is in the range between 1 to 2 and 1 to 3.
4. A junction field effect transistor substantially as hereinbefore described with reference to and as illustrated in Figure 4 of the accompanying drawings.
5. A method of manufacturing a junction field effect transistor comprising:
depositing a first layer of semiconductor material on a substrate of semiconductor material to produce a junction,
forming an anti-oxidation layer over the first layer such that a portion ofthe first layer remains exposed,
effecting diffusion of the layered substrate under oxidation conditions to provide the first layer with a region of substantially greater thickness than that underlying the exposed portion.
6. A method according to Claim 5 wherein the antioxidation layer is formed by applying a suitable material on the first layer, and then removing a portion of the anti-oxidation layer.
7. A method according to Claim 5 or Claim 6, wherein a layer is disposed between the first layer and the anti-oxidation layer, thereby to minimise stress at the interface of these layers.
8. A method substantially as hereinbefore described with reference to and as illustrated in the accompanying Figures.
9. A junction field effect transistor made by the method of any one of Claims 5 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08334364A GB2133621B (en) | 1983-01-11 | 1983-12-23 | Junction field effect transistor |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB838300617A GB8300617D0 (en) | 1983-01-11 | 1983-01-11 | Junction field effect transistor |
| GB08334364A GB2133621B (en) | 1983-01-11 | 1983-12-23 | Junction field effect transistor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8334364D0 GB8334364D0 (en) | 1984-02-01 |
| GB2133621A true GB2133621A (en) | 1984-07-25 |
| GB2133621B GB2133621B (en) | 1987-02-04 |
Family
ID=26284879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08334364A Expired GB2133621B (en) | 1983-01-11 | 1983-12-23 | Junction field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2133621B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1279395A (en) * | 1968-10-11 | 1972-06-28 | Nat Res Dev | Improvements relating to field effect transistors |
| GB1400040A (en) * | 1971-10-29 | 1975-07-16 | Thomson Csf | Field effect transistor having two gates for functioning at extremely high frequencies |
| GB1442693A (en) * | 1973-04-20 | 1976-07-14 | Matsushita Electronics Corp | Method of manufacturing a junction field effect transistor |
| GB1530145A (en) * | 1974-12-13 | 1978-10-25 | Thomson Csf | Method of manufacturing field-effect transistors designed for operation at very high frequencies using integrated techniques |
| GB2026240A (en) * | 1978-07-24 | 1980-01-30 | Philips Nv | Semiconductor devices |
| GB1563913A (en) * | 1975-12-12 | 1980-04-02 | Hughes Aircraft Co | Method of making schottky-barrier gallium arsenide field effect devices |
| GB2070858A (en) * | 1980-03-03 | 1981-09-09 | Raytheon Co | A shallow channel field effect transistor |
| GB2094058A (en) * | 1981-03-03 | 1982-09-08 | Standard Telephones Cables Ltd | Fabricating integrated circuit field effect transistors |
-
1983
- 1983-12-23 GB GB08334364A patent/GB2133621B/en not_active Expired
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1279395A (en) * | 1968-10-11 | 1972-06-28 | Nat Res Dev | Improvements relating to field effect transistors |
| GB1400040A (en) * | 1971-10-29 | 1975-07-16 | Thomson Csf | Field effect transistor having two gates for functioning at extremely high frequencies |
| GB1442693A (en) * | 1973-04-20 | 1976-07-14 | Matsushita Electronics Corp | Method of manufacturing a junction field effect transistor |
| GB1530145A (en) * | 1974-12-13 | 1978-10-25 | Thomson Csf | Method of manufacturing field-effect transistors designed for operation at very high frequencies using integrated techniques |
| GB1563913A (en) * | 1975-12-12 | 1980-04-02 | Hughes Aircraft Co | Method of making schottky-barrier gallium arsenide field effect devices |
| GB2026240A (en) * | 1978-07-24 | 1980-01-30 | Philips Nv | Semiconductor devices |
| GB2070858A (en) * | 1980-03-03 | 1981-09-09 | Raytheon Co | A shallow channel field effect transistor |
| GB2094058A (en) * | 1981-03-03 | 1982-09-08 | Standard Telephones Cables Ltd | Fabricating integrated circuit field effect transistors |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8334364D0 (en) | 1984-02-01 |
| GB2133621B (en) | 1987-02-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |