JPS60235445A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60235445A JPS60235445A JP9212384A JP9212384A JPS60235445A JP S60235445 A JPS60235445 A JP S60235445A JP 9212384 A JP9212384 A JP 9212384A JP 9212384 A JP9212384 A JP 9212384A JP S60235445 A JPS60235445 A JP S60235445A
- Authority
- JP
- Japan
- Prior art keywords
- field effect
- effect transistor
- layer
- forming
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 230000005669 field effect Effects 0.000 claims abstract description 23
- 239000013078 crystal Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 238000005224 laser annealing Methods 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 13
- 238000010894 electron beam technology Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 5
- 238000010276 construction Methods 0.000 abstract 1
- 238000001259 photo etching Methods 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 241000270281 Coluber constrictor Species 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- OQZCSNDVOWYALR-UHFFFAOYSA-N flurochloridone Chemical compound FC(F)(F)C1=CC=CC(N2C(C(Cl)C(CCl)C2)=O)=C1 OQZCSNDVOWYALR-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2636—Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置、特に電界効果トランジスタの製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, particularly a field effect transistor.
（従来技術）
従来、電界効果トランジスタの形状は、単結晶基板上に
チャネル領域、ソース領域、ドレイン領域を形成し、通
常それらは基板とは反対等電型として、ＰＮ接合により
絶縁していた。すなわち、８ｉを用いたＮチャネルＭＯ
８型電界効果トランジスタの例を取ると、第１図に示す
様に、 Ｐ−８ｉ基板１上に所望の深さ及び不純物濃度
のＮチャネル領域２、Ｎ＋＋ソース領域３およびＮ＋型
トドレイン領域４拡散により形成し、その上に薄いケー
ト酸化膜５を介して形成したゲート電極６とソース電極
７およびドレイン電極８とを形成していた。(Prior Art) Conventionally, a field effect transistor has a shape in which a channel region, a source region, and a drain region are formed on a single crystal substrate, and these are usually of the opposite isoelectric type to the substrate and insulated by a PN junction. In other words, N-channel MO using 8i
Taking the example of an 8-type field effect transistor, as shown in FIG. 1, an N-channel region 2, an N++ source region 3, and an N+-type drain region 4 are diffused to a desired depth and impurity concentration on a P-8i substrate 1. A gate electrode 6, a source electrode 7, and a drain electrode 8 were formed thereon with a thin gate oxide film 5 interposed therebetween.
この場合、ソース接地動作においては、ｓｉ基板ｌおよ
びソース領域３は接地されることより、チャネル領域２
及びドレイン領域４はＳｉ基板１に対してＰＮ接合で分
離された状態となり、接合容菫が付加されることとなる
。このため、高周波動作では特性劣化の大きな壷内とな
っていた。In this case, in the source grounding operation, since the Si substrate l and the source region 3 are grounded, the channel region 2
The drain region 4 is separated from the Si substrate 1 by a PN junction, and a junction violet is added. For this reason, high-frequency operation has resulted in significant characteristic deterioration.
（発明が解決しようとする問題点）
本発明の目的は、上記欠点を改善し、高周波特性の向上
を可能にした半導体装置の製法を提供するものである。(Problems to be Solved by the Invention) An object of the present invention is to provide a method for manufacturing a semiconductor device that improves the above-mentioned drawbacks and makes it possible to improve high frequency characteristics.
（問題点を解決するための手段）
本発明による半導体装−の製法は、単結晶上に絶縁膜を
形成し、この絶縁膜に開口を形成し、その上に開口部を
含んで多結晶層を形成した後、レーサーアニールもしく
は電子ビームアニールにより、多結晶層を単結晶化し、
絶縁層上の単結晶化された部分に不純物導入、酸化膜形
成および電極金属の形成等により電界効果トランジスタ
を形成するものである。電界効果トランジスタ等の素子
形成部以外の単結晶化された部分を酸化膜に変換する工
程を追加し°Ｃも良い。(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention involves forming an insulating film on a single crystal, forming an opening in the insulating film, and forming a polycrystalline layer on the insulating film including the opening. After forming, the polycrystalline layer is made into a single crystal by laser annealing or electron beam annealing,
A field effect transistor is formed by introducing impurities into a single crystallized portion on an insulating layer, forming an oxide film, forming an electrode metal, and the like. It is also possible to add a step of converting the monocrystalline part other than the part where elements such as field effect transistors are formed into an oxide film at 0.degree.
（発明の効果）
この結果、電界効果トランジスタの底面は、基板に対し
て絶縁層により分離されているため、その間の容量が非
常に小さくなり、高周波動作の良好な電界効果トランジ
スタを得ることができる。(Effect of the invention) As a result, the bottom surface of the field effect transistor is separated from the substrate by the insulating layer, so the capacitance therebetween is extremely small, making it possible to obtain a field effect transistor with good high frequency operation. .
（実施例）
以下、本発明の一実施例を図面を参照して説明する。Ｎ
チャネル型ＭＯ８電界効果トランジスタを例とする。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. N
Let us take a channel type MO8 field effect transistor as an example.
第２図（ａ）に示す様に、Ｓｉ単結晶基板９上に絶縁層
１（ｌ形成し、通常の写真食刻法で開ロラ°る。As shown in FIG. 2(a), an insulating layer 1 (1) is formed on a Si single crystal substrate 9, and is opened by a conventional photolithography method.
この開口は後に素子を形成する領域以外の場所又はその
場所のうち選択された所に形成する。その上に第２図（
ｂ）に示す様に、所望の厚さ及び不純物濃度のＮ型多結
晶７９３７層１１を気相成長法等で全面に形成した後、
レーザーアニールまたは電子ビームアニールにより、第
２図（Ｃ）の様に多結晶層１１を単結晶化し、単結晶化
層１２とする。この単結晶化の過程では、第２図（ｂ）
で、絶縁層１０の開口部内にある多結晶１１が、レーザ
ーアニールもしくは電子ビームアニールにより、Ｓｉ基
板９の結晶方向に再結晶化をまずはじめ、多結晶層１１
の全体に及ぶととＫなる。従って、レーサーアニールも
しくは電子ヒールアニールはこの開口部から行う。その
後、第２図（ｄ）に示す様に、絶縁層ｌＯ上の単結晶化
層１２上に、窒化シリコン膜１３を電界効果トランジス
タ等の素子が形成されるべき部分をおおうように形成す
る。そαＬ窒窒化シリコ模膜１３マスクとして選択酸化
し、島状に単結晶化層１２を残す。以後は、窒化シリコ
ン膜１３を取り除いた後、従来と同様に、第２図（ｅ）
に示す様に、ゲート酸化膜５及びゲート電極６を形成し
、ゲート電極６をマスクとして、イオン注入法でＮ型の
ソース領域３及びドレイン領域４を形成した後、第２図
（ｆ）の様に１ゲート酸化膜５の一部を通常のエツチン
グにより開口し、ソース電極７及びドレイン電極８を形
成する。This opening is formed at a location other than the area where the element will be formed later, or at a selected location. Above that is Figure 2 (
As shown in b), after forming an N-type polycrystalline 7937 layer 11 of a desired thickness and impurity concentration over the entire surface by vapor phase epitaxy or the like,
The polycrystalline layer 11 is single-crystalized by laser annealing or electron beam annealing to form a single-crystalline layer 12 as shown in FIG. 2(C). In this single crystallization process, as shown in Fig. 2(b)
Then, the polycrystalline 11 in the opening of the insulating layer 10 first recrystallizes in the crystal direction of the Si substrate 9 by laser annealing or electron beam annealing, and the polycrystalline layer 11
If it covers the entire area, it becomes K. Therefore, racer annealing or electronic heel annealing is performed through this opening. Thereafter, as shown in FIG. 2(d), a silicon nitride film 13 is formed on the single crystallized layer 12 on the insulating layer 1O so as to cover a portion where an element such as a field effect transistor is to be formed. Selective oxidation is performed using the αL silicon nitride pattern 13 as a mask, leaving an island-shaped single crystal layer 12. Thereafter, after removing the silicon nitride film 13, the process shown in FIG. 2(e) is performed in the same manner as before.
As shown in FIG. 2(f), a gate oxide film 5 and a gate electrode 6 are formed, and an N-type source region 3 and a drain region 4 are formed by ion implantation using the gate electrode 6 as a mask. Similarly, a part of the first gate oxide film 5 is opened by ordinary etching, and a source electrode 7 and a drain electrode 8 are formed.
以上の様に、第２図（ｆ）に示す電界効果トランジスタ
は、Ｓｉ基板９とは絶縁層１０により分離されているた
め、その間の容量は非常に小さく、第１図に示す様な従
来構造の電界効果トランジスタと比較して、同一のゲー
ト長、グー）１１１Ｍ及びゲート酸化膜厚でも、良好な
高周波特性を有する。また本発明の第２図（ｆ）に示す
電界効果トランジスタは、周辺も酸化膜で取り囲まれて
いるため、完全に絶縁分離しており、ただちに集積回路
へ適用可能なことは言うまでもない。As described above, since the field effect transistor shown in FIG. 2(f) is separated from the Si substrate 9 by the insulating layer 10, the capacitance therebetween is very small, and the field effect transistor shown in FIG. Compared to the field effect transistor of 2009, it has good high frequency characteristics even with the same gate length, 111M and gate oxide film thickness. Further, since the field effect transistor of the present invention shown in FIG. 2(f) is also surrounded by an oxide film, it is completely insulated and isolated, and it goes without saying that it can be immediately applied to integrated circuits.
ここでは、Ｎチャネル型ＭＯ８電界効果トランジスタを
例としたが、Ｐチャネル型ＭＯ８電界効果トランジスタ
及び接合型電界効果トランジスタへ本発明を適用できる
ことは明白である。また、ＳＲ単結晶基板９および多結
晶シリコン層１１′ｆｒ。Here, an N-channel type MO8 field effect transistor is taken as an example, but it is obvious that the present invention can be applied to a P-channel type MO8 field effect transistor and a junction type field effect transistor. Further, the SR single crystal substrate 9 and the polycrystalline silicon layer 11'fr.
同一導電型で、かつソース領域３およびドレイン領域４
と異なる導電型とすることによって、単結晶化層１２の
素子形成部以外の部分を酸化膜に変換せずそのまま残す
こともできる。Source region 3 and drain region 4 of the same conductivity type
By making the conductivity type different from that of the oxide film, it is possible to leave the portions of the single crystallized layer 12 other than the element forming portions as they are without converting them into an oxide film.
第１図は従来の電界効果トランジスタを説明するための
断面図、第２図（ａ）〜（ｆ）は本発明の一実施例によ
る電界効果トランジスタ製造方法の各工程に於ける断面
図である。FIG. 1 is a cross-sectional view for explaining a conventional field effect transistor, and FIGS. 2(a) to (f) are cross-sectional views at each step of a method for manufacturing a field effect transistor according to an embodiment of the present invention. .
Claims (1)
晶シリコンＮを形成する工程と、前記多結晶シリコン層
をレーザーアニールもしくは電子ビーヘアニールにより
単結晶化する工程と、前記絶縁膜の開口部以外の前記単
結晶化シリコン層中に電界効果トランジスタを形成する
工程とを含むことを特徴とする半導体装置の製法。a step of forming polycrystalline silicon N including the opening on an insulating film with an opening on a single crystal; a step of converting the polycrystalline silicon layer into a single crystal by laser annealing or electronic beam annealing; A method for manufacturing a semiconductor device, comprising the step of forming a field effect transistor in the single crystal silicon layer in a region other than the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9212384A JPS60235445A (en) | 1984-05-09 | 1984-05-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9212384A JPS60235445A (en) | 1984-05-09 | 1984-05-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60235445A true JPS60235445A (en) | 1985-11-22 |
Family
ID=14045652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9212384A Pending JPS60235445A (en) | 1984-05-09 | 1984-05-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60235445A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62296508A (en) * | 1986-06-17 | 1987-12-23 | Matsushita Electronics Corp | Semiconductor integrated circuit device |
| CN113972344A (en) * | 2020-07-22 | 2022-01-25 | Tcl科技集团股份有限公司 | Light emitting diode and preparation method thereof |
-
1984
- 1984-05-09 JP JP9212384A patent/JPS60235445A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62296508A (en) * | 1986-06-17 | 1987-12-23 | Matsushita Electronics Corp | Semiconductor integrated circuit device |
| CN113972344A (en) * | 2020-07-22 | 2022-01-25 | Tcl科技集团股份有限公司 | Light emitting diode and preparation method thereof |
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