FR2569486A1 - CHARGE COUPLING COMPONENT (CCD) IN PARTICULAR IN THE APPLICATION OF MICROELECTRONICS - Google Patents

Abstract

A.CCD LOAD COUPLING COMPONENT, ESPECIALLY IN THE APPLICATION OF MICRO-ELECTRONICS. B. COMPONENT CHARACTERIZED IN THAT AFTER STRUCTURING A FIRST LARGE-SURFACE ELECTRODE PLANE (WITH THE FIRST ELECTRODE CONFIGURATION AS A MASK) 12 A DOPING N11 GENERATING POTENTIAL BARRIERS IS INTRODUCED AND THEN A SECOND PLANE OF ELECTRODES 15 IS APPLIED, WHILE IN CERTAIN SUBSTRATE AREAS WHAT IS CALLED A COMPENSATION DOPING, THE DOSE AND PROFILE OF THE ABOVE COMPENSATION DOPING IS SELECTED SO THAT THE AREAS CONCERNED BY THE COMPENSATION DOPING CAN COMPLETE THE MEMORY ZONES FUNCTION OF A CCD OFFSET REGISTER. C. THE INVENTION RELATES TO A CCD CHARGE COUPLING COMPONENT, IN PARTICULAR IN THE APPLICATION OF MICRO-ELECTRONICS.

Description

1. - "Charge coupled component (CCD) in particular in the application

  The invention relates to a new concept

  for producing a charge-coupled component

  geso Components of this kind find multiple

  applications in microelectronics and opto-

  in the form of individual lines

  in the form of lines assembled to form

  sets occupying a certain area.

  Among the different known types of CCD, those with two phases are particularly advantageous

  from the point of view of their order. In a variant of

  For example, see the series of Fairchild-CCD types as well as the L 110, L 133 and L 211 components of the VEB WF Berlin, memory electrodes

  are made with a first plane of polycrystalline silicon

  tallin while the transfer electrodes are made

  with a second polycrystalline silicon plane. The transfer electrodes then cover the intervals

  structured between the memory electrodes. Before the

  In the second plane of polycrystalline silicon, a dopant of the conductivity type of the substrate is implanted in the intervals, self-adjusted by the edges of the memory electrodes, whereby the potential barrier areas necessary for the future operation in two phases. , are fixed. A memory electrode and a

  transfer respectively constitute a pair of electrodes.

  2. The pairs of electrodes are alternately connected to the first and second synchronization phases. For this purpose, each of the memory electrodes must be electrically separated from the neighboring memory electrodes. The same requirement applies for transfer electrodes. In addition, the insulation between the memory electrodes and the transfer electrodes that overlap them

  but which are, however, connected to the other phase of syncro-

must be perfect.

  These latter requirements are not always

  in a simple way during the technological process.

  cal. Electrical separation of transfer electrodes

  between them is often not obtained because of the aopari-

  or the persistence of so-called polycrystalline silicon wires. There is already in the literature

  proposals, for example according to the documents

  US Pat. No. 4,027,381, 4,027,382 and 4,035,906 to adjust in two-phase CCD the electrodes of each phase of

  synchronization from a single electricity plan respectively.

  trodes applied, and thus avoid this problem, just like

  that of the appearance of polycrystalline silicon son.

  Two basic variants are then applied:

  1. oxide gate stages in combination with an implanta-

  2. A first implantation of barriers before the removal of the first plane of electrodes, the implant being subsequently absorbed for the most part by the oxide on certain partial zones following an oxidation process, then

  following a second implantation of bar-

  riers. Technologies of this type are complicated. com-

  the absorption of a barrier implant by an oxide is not fully realized, problems arise from

  makes non-homogeneous potentials in the CCD cell

  Lisée. The smallest possible weft is determined 3, -

  in the aforementioned technology, where the electrodes de-trans-

  fertility cover the structured intervals between

  memory electrodes, by the interval lengths half

  possible to be made and by the overlap

  minimum required distance between memory electrodes

  and the transfer electrodes. If, for example, the length

  minimum distance between the transfer electrodes is 4 / m, the minimum overlap of 2 m,

  8 Nm is obtained as the minimum length for electri-

  memory trodes For an interval of 4 m between the memory electrodes, we thus have a minimum frame of 12 / m

  The object of the invention is to avoid

  related to the known state of the art without

  1 5 increase technology spending to an undue extent

tifiableo

  The problem with the invention is to

  tricking a two-phase CCD with barrier zones

  self-adjusted, in which case, with a relative technology

  uncomplicated, an electrical separation of electrical

  trodes structured from a plan is not necessary.

  re and can also obtain a small frame.

  To solve this problem, we use,

  according to the invention, three electrode planes, the second electrode plane not being isolated from the first electrode plane. In addition, on parts of the substrate o firstly was introduced a barrier implant,

  an appropriate potential for storing

  load port was again obtained by an implant of

  compensation introduced later.

  A semiconductor substrate is coated with a suitable insulating film on which a first electrode plane is deposited. Previously, we can introduce in the

  substrate a doping zone of the conductivity type in-

  poured from that of the substrate, to guarantee transport 4.-

  of the signal charge in a volume channel (CBOCD).

  If this doping zone is absent, the transport of

  will take place on the surface. Also previously, appropriate channel stop zones may have been introduced. A first configuration of electrodes is

  structured from the first plane of electrodes. This first

  first plane of electrodes control in operation

future areas of memory.

  Then, implantation with a dopant of the conductivity type of the substrate is carried out over a large area. The first electrode configuration

  then serves as an implantation mask. Dosage and energy

  of this implantation are preferably chosen so that the zones provided with this implantation and which are not concerned by the compensation doping to be examined later, can be used during

  exploitation of the future CCD register of trans-

  fertility, that is, a potential barrier vis-à-vis

  memory areas are generated in these areas.

  A second electrode plane is then deposited which does not need to be isolated from the first electrode configuration. The second electrode configuration is structured from this second plane of electrodes,

  way that respectively an electrode of the second con-

  figuration overlaps an electrode of the first configuration.

  ration on one side. In the transport direction of the

  CCD register, it is then foreseen at this stage between the different

  the first and second planar electrode pairs, a surface free of the electrode material. Then, by means of a suitable mask, which may for example be made of a photolayer, a dopant of a type of conductivity opposite to that of the substrate is implanted on a part of the zone not covered by the material.

electrode.

  5.- Dosage and implantation energy are

  measured in such a way that the effect

  potential of the dopant of conductivity type of the previously implanted substrate (during this last implantation) is compensated. For this compensation, he

  It is not necessary for the location profile of the

  page of compensation is identical to the profile of dopants

  previously implanted the conductivity type of the substrate.

  It is enough that the potential in the areas interested in

  the compensation doping reaches during the

  of the future CCD register, a sufficient value for the storage of charge support, ie that these zones in the event of exploitation, can serve as zones

of memory.

  The implantation mask has, for the first time

  and the second electrode configurations, position it

  following principle: we hide a band that

  rope next to the electrode of the first configuration

  which are not covered by the electrodes of the

  twelfth configuration. Along the transport direction

  of the CCD register, after completion of the doping com-

  thought, the succession of zones described below: electricity

  trode of the second configuration with doping barriers

  below, the electrode of the first configura-

  with "memory" doping below, free zone

  electrodes with doping of barriers, zone free from

  trode with doping of barriers more compensation doping,

  electrode of the second configuration with bar doping

below, etc.

  The pairs of electrodes of the first and second

  cond plans are now covered with an iso-film

  appropriate. Then the third plane of electrodes

  is applied and from it, the third configura-

  electrodes is structured. This structuring is relatively coarse, and this third configuration can remain consistent along the direction of transport

of the CCD register.

  Then, the conventional steps such as the introduction of source and drain zones, the possible deposition of other insulating layers, the structuring of contact windows and the deposition as well as the

  structuring of a plan of conductive tracks. In function

  the CCD register, all the pairs of elec-

  trodes of the first and second planes are connected to the first synchronization phase and all of the third electrode configuration is connected to the second synchronization phase. Since each of the deposited electrode planes is located on a single phase, it is not necessary to carry out inside a plane an electrical separation of the different electrodes.

the other.

  In the case of the present invention, there is no

  problems arising from

  polycrystalline silicon in the case of technical solutions

  previously known issues.

  The third electrode configuration does not need to present a "fine structuring" along

  of the CCDo register This simplifies the manufacture.

  Potential barriers of potential in

  the CCD register are, as is clear from the ex-

  previous pose, introduced in a self-adjusted manner. A

  Two-phase CCD without such self-adjustment would be

  too much inconvenience.

  However, the establishment of contacts is simplified and compact. The third configuration

  In the absence of a "fine structure"

  trouble-free contact in the area of the active area of the register. The width of the CCD register can thus be

  minimum, which has a particular advantage

  in assemblies forming a surface of CCD registers, 7V-, in which photodetectors without an electrode are arranged between the different lines, the CCD registers being thus only able to be put in contact with each other;

  individually along the direction of transport.

  The previously discussed concept of doping

  compensation, the term compensation for the

  may, in the spirit of this invention, be equal

  used in a general way. Thus, for example, it is often necessary to produce zones generating self-adjusted potential barriers under different electrodes. For such purpose, the second configuration

  evoked electrodes should not be inside the

  previously described, overlap the first

  guration, or there is no need for a first con-

  figuration of electrodes. After the completion of the compensating doping, there are then under the electrodes of the second configuration, zones generating barriers

potential self-adjusted.

  In a particularly advantageous way, thanks to the concept outlined in this document, it is possible to build

  BCCDs for which partial areas are

  green (superficial) layers of ar-

  channel end. An example of such a BCCD is described in US-PS 4,229,752 where the extremely thin channel stop layer used is referred to as

"virtual phase".

  The realization of the BCCD is then continued

  so that the first two configurations of electro-

  non-isolated from each other, are structured and the compensation implant is introduced. Then,

  without an additional mask, a dopant of a type of conductive

  In contrast to that of the substrate is implanted with a high energy and a dopant of the conductivity type of

  substrate is implanted with lower energy. The do-

  the conductivity type of the substrate is positioned 8. - in the superficial area of the semiconductor. The emerging surface channel barrier layer protects the interior of the semiconductor against the external fields. A third additional electrode plane is superfluous. The dopant of a type of conductivity opposite to that of the substrate introduced in addition provides the necessary potential in the volume channel of the zone

  covered by the superficial layer of channel stop.

  On the first two configurations of electricity

  trodes not isolated from each other, the

  synchronization. It should be noted that

  However, for the two-phase CCD made in accordance with the present invention, stages are not required in gate isolation. For example, one can operate with a double layer of oxide and nitride deposited at once on the substrate. In the case where a superficial (vertical) channel stop layer is provided, an oxide grown at one time would already be sufficient

as a door insulator.

  A minimal frame can be evaluated as follows: the overlap of the electrodes of the second plane by those of the foreground is at least 2 Fm. As the edge of the electrodes of the second plane can be adjusted on the middle of the electrodes of the first plane, the minimum gate length for the electrodes of the first plane is obtained a value of 4 μm. With a barrier area of 4 m in length, the result is a minimum frame of 8 m. The invention will be explained with reference to an exemplary embodiment with the aid of the accompanying drawings.

wherein: -

  FIG. 1 shows different stages in the fabrication of a first embodiment variant; FIG. 2 shows a second variant;

of realization.

  9.- In the exemplary embodiment, one starts from a conductivity silicon substrate p. Of course,

  the invention can also be carried out with

  conductivity trajectories n. Appropriate doping

  to produce are respectively of the opposite type of conductivity. In addition, polycrystalline silicon is indicated

  as electrode material. Of course, other materials

  Suitable silicides may also be used. Figures 1a to 1c are cross sections along the

  of the transport directorate of the future decommissioning register.

  charge coupled lage. On a p 10 conductivity silicon substrate, is introduced over a large area

  and on the future active zones, a doping n 11 (figure la).

  The dosage of this doping n 11 is measured so that during the future operation of the CCD shift register, the zone 11 can be completely depleted in mobile charge carriers The channel stop zones necessary for the lateral delimitation of the register to offset, can not be represented on the sectional views of the figures

  1 and 2. Channel stopping areas are areas with

  whether a sufficiently high p doping or a combination of

  p-doping sound with a thick field oxide. The active zones are coated with the door insulator 15. A double layer of thermally grown SiO 2 and chemically deposited Si 3 N 4 is very suitable as a door insulator 13. From the first polycrystalline silicon layer thus deposited and doped, the structure is the

  first configuration of electrodes 12. Then

  a large surface area kills a boron implantation, the electrodes 12 serving as a mask, resulting in the zones 14 having a slight doping p. With these areas 14 potential barriers required for future two-phase operation, are obtained. 10. At the next step the second polycrystalline silicon layer is deposited, doped and from it, the electrode configuration. 15 is structured

  (see Figure lb). Between the electrodes 15 and the electrodes

  trodes 12 no insulation is necessary. After realizing

  lacquer mask 16, an implantation of phos-

  phore is performed. As a result of the masking by

  12 and 15 as well as by the lacquer mask 16, the implant only reaches the zones 17

in the semiconductor substrate.

  The dosage and the energy of this implantation

  phosphorus levels are measured so that the effect of

  Zone 14 potential barriers be compensated

  in areas 17 affected by the implantation of phosphorus.

  For this compensation, it is not necessary

  that the implantation profile of this phosphorus implantation is identical to the profile of the implantation of boron generating the zones 14. It is sufficient that the potential in the zones 17 by action of the implantation of phosphorus and boron as well as the channel doping introduced into a

  previous stage of the process, reaches, during the

  CCD, roughly the same value as in zones 11.

  After dissolution of the lacquer mask 16, the

  electrodes 12 and 15 are co-coated with an insulating film

  This can be done by thermal oxidation of polycrystalline silicon. The third polycrystalline silicon layer is then deposited and, from it, the electrode configuration 18 is structured (see Figure lc). Doping of polycrystalline silicon electrodes

  18 can be carried out during the subsequent dissemination to

make the source and drain.

  The structuring of the third polycrystalline silicon layer is relatively coarse and

  the electrode 18 can remain coherent along the direction

  In order to complete the finishing of the CCD register, the conventional steps are carried out such as the diffusion of the source and the drain, the siloxane deposit, the struic turation of contact windows and the deposition of the CCD. a plan of aluminum conductive tracks X For operation. the first phase of

  synchronization is applied to the electrode 18 and the

  synchronization phase is applied to the electrodes

  12 and 15 connected so as to have a common conductivity

  born. Figure ld shows the maximum potentials

  evils in the empty channel of

  At the electrodes 12 and 15 a DC potential (for example 6 V) is applied and at the electrode 18 a pulse voltage is applied (for example U ha-s = 0V, UHigh = 12V). Under the electrodes 12 and 15,

  the potential then has the trace 19, in which the zone

  tr8lée by the electrode 18, changes the potential at the rate of the synchronization voltage of the plot 20 for 'ias the plot 21 for Uhaut'

  In Figure 2a, is sketched the constitution

  tion of a second embodiment in which partial areas are covered with a layer of stop channel superficial. The CCD is then, as described

  in the first variant carried out until the step

  felt in Figure ld. After dissolution of the lacquer mask 16, a high energy phosphor implantation is performed. The electrodes 12 and 15 then serve as

  masks. The dosage is measured so that during

  the maximum potential in the empty transport channel of the charge of zone 22, reaches approximately a value that we would like to maintain in

  zone 11 when the electrode 12 is at a potential

  tinu (for example 6 V) which corresponds to the arithmetic mean

  between the high and low levels of the

  necessary for the synchronization voltage. The implan-

  Subsequent boron deposition with lower energy results in a surface layer 24 of conductive conductivity p in the superficial portion.

  immediate unmasked areas of the semiconductor, uni-

  coated with the door insulator. The layer 24

  is connected to the channel stop zones used to delimit

  lateral maitement and is thus electrically at the pot

  the substrate. A third configuration of electricity

  trodes is superfluous. the doping zones 23 generate about the same potential barriers as the zones 14

  when the layer 24 is extremely thin. When the former

  depth of the layer 24 is not neglected.

  With respect to the depth of the doping zone 14, the potential barrier generated by the zone 23 is then smaller than that resulting from the zone 14. To complete the finishing of the CCD register sketched in FIG. conventional steps such as those mentioned above with respect to the first embodiment. Note that the electrodes 12

  and 15 must not be thermally oxidized. To help

  insulation against the plane of the conductive tracks.

  aluminum, usually the siloxane layer

filed is sufficient.

  During the operation of the second

  the synchronization phase is applied to electro-

12 and 15 (connected together).

  Figure 2b shows the plots of the maximum potential in the empty transport channel. The trace 26 is established when the low level of the synchronization voltage is applied to the electrodes 12 and the pattern 27 results from the action of the high level. The

  25 is determined by the thin film 24 with

  tibility p lying at the potential of the substrate and by

  the doping being below her.

13. -

Claims (4)

R E V E N D I C A T IO N S   1 - Charge-coupled component, characteristic   in that after structuring a foreground   of large surface electrodes (with the first mask as   re configuration of electrodes) (12), doping n 11 engenders   potential barriers (doping of the type of   substrate) is introduced and then a second   plane of electrodes (15) is applied, the structural electrodes   made from this second plane partially overlapping those of the foreground and do not need to be isolated from them, while in certain areas of the substrate, where doping of barriers has first been introduced, introduces a so-called compensating doping (of the conductivity type opposite to that of the substrate), the first two electrode configurations and an additional mask then being used for the masking, the dose and the doping profile said compensation being chosen so that the areas concerned by the compensation doping can fulfill the function of memory zones of a CCD shift register, that is to say   that, when the component is subsequently used, a potential   suitable for the storage of charge carriers can be obtained in the transport channel of   the areas concerned by compensatory doping.   2.- Charge coupled component according to   claim 1, characterized in that for adjusting   of the potential required in the active areas not covered by the first and second electrode planes, a third electrode plane is deposited, this third electrode configuration advantageously covering the entire area of the CCD shift register, the form of a coherent layer.   3.- Charge coupled component according to   claim 1, characterized in that for adjusting   potential in non-active areas.   covered by the first and second electrical   trodes, a channel stop surface layer (substrate conductivity type) is introduced into the zone.   superficial semiconductor, thanks to which we economise   placing in these areas a cover electrode. 4.- Charge coupled component according to   any of claims 1 to 3, characterized in that   below the different electrodes, self-adjusting zones generating potential barriers are produced, in that, after introduction (over a large surface) of a doping of barriers (doping of the conductivity type of the substrate), a plane is applied. electrodes, structure   from this plane the different electrodes and final-   The compensation doping referred to in claim 1 is introduced, the different electrodes (as well as other possible structured layers) being used. for masking.