JPS6254465A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the breaking current without affecting other device characteristics by a method wherein the final turn-off current is concentrated on the unit GTOs located nearer to the lead junction and the unit GTOs remaining not turned off until the 1st instant are turned off virtually at the same time. CONSTITUTION:A (p) emitter layer 11, (n) base layer 12, (p) base layer 13, and an (n) emitter layer 14 are formed, inside a semiconductor substrate 1. Between the layers, respectively, p-n junctions are built, for a thyristor to operate. An anode electrode 20 is connected to the (p) emitter layer 11, cathode electrode 2 to the (n) emitter layer 14, and a gate electrode 3 and a gate junction C1 to the (p) base layer 13. in this way, each of the unit GTOs located farther from the lead junction are turned off earlier than those located nearer to the lead junction. The current at the final phase of the turning-off process is in this way concentrated on the unit GTOs located nearer to the lead junction and the unit GTOs remaining not turned off until the last instant are turned off simultaneously, which allows the maximum breaking current to be greater.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor switching devices such as gate turn-off thyristors and transistors, and particularly to a semiconductor device suitable for increasing the maximum cutoff Ml flow.

(Background of the Invention) Large-capacity gate turn-off thyristors (hereinafter abbreviated as GTO) and transistors have an n-emitter layer consisting of one or more elongated strips of approximately constant width, and together with an adjacent base layer, a semiconductor One main electrode is in low resistance contact with each strip-shaped region and is exposed on one major surface of the substrate, and a pressure control electrode is provided in the base layer to substantially surround each strip-shaped region. The other main surface of the semiconductor substrate is further contacted with the other main electrode or with low resistance,
Each pole is connected to a pair of main terminal and control terminal, respectively.

Taking GTO as an example, its turn-off operation will be explained below.

The turn-off operation of the GTO having the above structure is as follows.

As is well known, this phenomenon occurs when excess carriers such as electrons and holes accumulated in the semiconductor substrate are rapidly expelled to the outside by a negative gate current.

Then, in order to make it as easy as possible to extract the gate current from the current conduction region and to speed up the turn-off, a long and thin strip-shaped canned emitter layer (hereinafter referred to as "cando emitter layer") surrounded by the gate electrode as described above is used.

A structure (abbreviated as unit GTO) is adopted, and a large number of these are arranged in parallel within a semiconductor substrate according to the current capacity.

As an arrangement of unit GTOs suitable for increasing capacity, a structure has been devised in the past in which unit GTOs are arranged in a concentric ring shape within a semiconductor substrate (Japanese Patent Application No. 54-84
964 and JP-A-56-131955, etc.).

However, the conventional structure as described above also has its limitations.

As the dimensions of the semiconductor substrate increase, the unit GT
A problem has arisen in that even if the number of O's is increased, the desired maximum breaking current cannot be obtained.

The inventors have determined that the maximum cutoff f! This is the result of investigating the reason why the L flow does not increase in proportion to the number of unit GTOs.

As the diameter of the semiconductor substrate becomes larger, the non-uniformity of the turn-off operation of the unit GTO within the plane of the semiconductor substrate becomes larger, and the current from the unit GTOK which is the most delayed in turn-off operation and the unit GTO which turned off first becomes larger. It turns out that this is because the current is concentrated, causing current concentration.

Furthermore, it has been found that there are two causes for increasing the non-uniformity of the turn-off operation between unit GTOs within a semiconductor substrate.

One is that the variations in the characteristics of the unit GTO itself are increasing. In the manufacturing process, the carrier life time at the outer periphery of a semiconductor substrate tends to be shorter than that at the center due to thermal strain, etc., and by increasing the diameter of the semiconductor substrate, the relationship between the outer periphery and the center is The distance is getting bigger.

The variation in characteristics also increases accordingly.

Another cause is that the gate current distributed to each unit GTO is non-uniform due to the difference in impedance of the control electrode of each unit GTO as seen from the control electrode connection portion (external 11 lead terminal).

As described above, in a large-capacity GTO, a main electrode and a control electrode are exposed on one main surface, and each is brought into low-resistance contact with an external lead terminal by pressure contact.

In this case, if you try to press the two together over the entire surface, it is necessary to miniaturize the pressure welding voltage and other parts, and it will be difficult to align them, so only the main electrode is pressed on the entire surface, and control 1! The poles are usually connected to external lead terminals by partial pressure welding.

Therefore, 1
Gate of unit GTO far away from partial pressure welding part'! The distance that the current flows through the control electrode provided on the semiconductor substrate increases, and due to the difference in impedance between them,
This causes non-uniformity in the gate current flowing through each unit GTO.

Due to the above-mentioned factors, in the conventional structure, even if the diameter of the semiconductor substrate is increased, the cutoff of 1'W is proportional to the diameter of the semiconductor substrate.
There was a problem that L flow could not be obtained.

(Object of the Invention) An object of the present invention is to provide a semiconductor device having a self-shutdown ability, in particular a semiconductor device that can increase the cut-off current without affecting the characteristics of the capacitor such as on-state voltage. There is a particular thing.

(Summary of the Invention) The present invention is characterized in that the conductivity types of the C grooves are alternately different between a pair of main surfaces of a semiconductor substrate. At least three semiconductor layers are 1! p-order stacked, one outermost layer is divided into strip-shaped regions and separated from each other and exposed on one main surface, and an intermediate layer adjacent to the outermost layer surrounds the strip-shaped region, 4 on one main surface, and 1 main on each strip-shaped outermost layer on one side and on the other outermost layer!
The electrodes are in low resistance contact, the control electrode is in low resistance contact with the intermediate layer, and each strip-shaped outermost layer is a control electrode. 31 t ti In a semiconductor device that is multiplexed with respect to lead connection portions, from each control electrode between each unit GTO including the strip-shaped one outermost layer arranged close to the lead connection portion. Based on the new finding that the impedance difference (variation) leading to the external lead terminal is inherently smaller than the impedance difference between the unit GTOs arranged apart from the lead connection part, the lead connection By making the lifetime of the carrier in each unit GTO arranged away from the lead connection part substantially shorter than the lifetime of the carrier in each unit GTO arranged near the lead connection part, Each unit GTO located far away from the lead connection turns off earlier than one located closer, thereby concentrating the current at the end of turn-off on each unit GTO located closer to the lead connection. The remaining GTO units are configured to be turned off substantially simultaneously.

According to the study results of the present inventors, the instantaneous breaking current of each unit GTO is extremely high, and if the parallel operation at the final turn-off is made uniform, the overall fast-breaking current can be greatly increased. Because I understand.

Another feature of the present invention is based on the fact that the narrower the width of one of the strip-shaped outermost layers, the more uniform the current during steady conduction between each unit GTO and the shared current at the final turn-off can be made. , the width of the one outermost layer of each unit GTO arranged in the vicinity of the lead connection part is configured to be narrower than that of each unit GTO arranged away from the lead connection part, thereby making it possible to particularly improve the final turn-off layer. The aim is to further equalize the shared current.

(Embodiment of the Invention) Hereinafter, an embodiment of the present invention applied to a GTO will be described with reference to the accompanying drawings.

1 and 2 show an embodiment of the present invention. Figure 1 is GT
This is a diagram showing the cathode side planar pattern of O in quarters, in the case of a so-called intermediate ring gate structure in which the gate connection portion C1 is provided in the middle of a unit GTO array arranged in a ring shape and a multi-i concentric circle. It shows. Figure 2 shows
FIG. 2 is a sectional view taken along line A-A' in FIG. 1;

As is well known to those skilled in the art, and as can be seen in the cross-sectional view of FIG. 2, inside the semiconductor body l there is a P emitter layer 11. n base layer 12. p base 1J113. and an n emitter layer 14 are formed, and a pn junction necessary for thyristor operation is formed between each layer.

Then, the p emitter layer 111C has an anode voltage [20,
The n emitter layer 14 trap has the cathode electrode 2, and the p bar 1
The layer 131C is conductively connected to the gate electrode 3 and the gate connection portion C1, respectively.

Here, as shown in the figure, if the area close to the gate connection part C8 is defined as area ■, and the other areas are defined as area engineering and area ■, then the area engineering and area It is configured to have a short lifetime.

Such lifetime control of area ■, area engineering, and ■ can be easily achieved by selective diffusion of heavy metals such as gold, i.e., lifetime killers, or selective irradiation with electron beams or gamma rays. is well known to those skilled in the art.

Further, as shown in FIG. 5(at(b)), a highly concentrated n+ layer region is provided in a part of the p emitter 11, so-called p
Practical lifetime control can also be easily achieved by creating an emitter short-circuit structure and changing the short-circuit width.

Figure 5 (&) is a cross-sectional view of head-mounted I and
is HARA'J, ll, i.e., C-C in Figure 1.

D-1:) The line has seven cross sections. As is clear from the comparison of these two figures, the short circuit M of p emitter 1dll
By increasing (the size of nlj), the time life can be shortened.

Next, a GTO having a structure as shown and explained above.
The turn-off operation will be explained.

At the beginning of this issue, we will explain the state immediately before the turn-off signal is input to the GTO. The current flowing in each unit GTO in the region (2) close to the gate connection portion and the other regions I and (2) is larger in the region (2) due to the substantial difference in lifetime.

In such a state, when a gate current for turn-off flows between the gate electrode 3 and the cathode electrode 2, each unit GTO in the region (2) and (2), which has a low current and a short lifetime, turns off first. The current flowing there is
It moves to O.

By the way, since the region (2) is located near the gate connection portion C, the difference (variation) in impedance from each control electrode to the external lead terminal between each unit GTO included in this region (2) is due to the gate connection i. It is inherently smaller than that between the area engineering and each unit GTO included in section CI, which are relatively far away from section CI.

Therefore, at the end of turn-off, the turn-off motion within the region ■ is made uniform, resulting in an overall maximum continuous connection of 1! You can improve your flow.

In the second embodiment of the present invention, the width of the outermost layer strip-shaped region of each unit GTO in the region (2) is determined.

By making the structure narrower than that of each unit GTO in area 2 and in area 2, and by equalizing the distribution of IL flow among each unit GTO in area 2 and equalizing the parallel operation at the final turn-off, the maximum This further increases the effect of improving the interrupting current.

A second embodiment of the present invention will be described below with reference to FIGS. 3 and 4. FIG. 3 is a cross-sectional view illustrating the structure of each unit GTO in each region 1 to (2) in the second embodiment of the present invention, and fa) and fb) in the same figure are BB and E in FIG. 1, respectively. -E line and c-c'.

It is a sectional view along the DD line.

As can be seen from the comparison of FIG. 3 (at (bl), the difference between the two is the width of the n emitter layer 14.
Shown in bl. The width X2 of the n-emitter layer 14 of the unit GTO belonging to the region ■ near the gate connection portion C and the IC is narrower than the width X1 of the n-emitter layer 14 of the unit GTO belonging to the regions I and ■ in the same figure (a). That is what we are doing.

In addition, in order to improve the gate breakdown voltage and widen the pressure contact area of the cathode electrode 2, 5tO
It forms a 1l absolute RM4, as shown in Figures 3(a) and (b).
) The widths of the cathode electrodes 2 are the same.

FIG. 4 is illustrated to explain parallel operation between unit GTOs. As shown in Figure 4, the unit GT
Everything between the two layers is common except for the n emitter layer 14.

Here, assuming that the anode current iA flowing through the element A is larger than the anode current iB flowing through the element BK, the potential vs, at the junction JH of the element A is higher than the potential V, □ at the junction J12 of the element B. Become.

For this purpose, a portion of IA flowing through the anode 1 of the element A flows into the junction J82 of the element B via the gate electrode 3. That is, for element B, an additional gate current iGA as shown in FIG. 4 flows.

As a result, the injection efficiency of element B increases, and the anode current iB flowing therein increases, while the injection efficiency of IA element A decreases, so that the anode current iA flowing therein decreases. In this way, the unit GTOKs connected in parallel have the function of trying to equalize the shared current between them.

The narrower the width X of the n-emitter layer 14, the greater the effect of making the shared current uniform.

In other words, JIll l Jfi! The potentials ``II'' and VS□ at the ends of the junction close to the gate electrode 3 are equalized by the gate electrode 3 as described above. There is a potential difference between the junction potentials v, 1' and v8□' due to a voltage drop caused by the lateral resistance of the p-bar 3 layer 13, and this is likely to weaken the shared current equalization effect. Or, by narrowing the width X of the n emitter layer 14,
This is because the potential difference can be made small and, therefore, the aforementioned shared X flow equalizing effect can be maintained.

As described above, narrowing the width X of the n-emitter layer 14 has the effect of correcting variations in characteristics that occur during the manufacturing process of the semiconductor substrate 1 and making the shared current of each unit GTO uniform. For this reason, each unit GTO in the area ① of the present invention
The current flowing in regions I and 2 is much more uniform than in regions I and II.

From this state, region (2) is attracted to regions I and (2) and turns off. Since region (2) is located close to the gate connection portion C1, the turn-off operation between each unit GTO is not affected by the difference (variation) in impedance between each control electrode and the external lead terminal pressure between each unit GTO. is also made uniform, so the shield 18'1TI
This is a major increase.

As described above, in the semiconductor device of the present invention, 1! Even though the flow was once concentrated in about 1/3 of the area■, block it 712! , the current was able to be increased from the conventional approximately 180 OA to over 3000 A.

A unit GTO consisting of one each of the rectangular strips shown in Figure 1.
The breaking current for each unit is as high as approximately 80A or more, due to improved parallel operation.

It is presumed that the above-mentioned improvement has been achieved.

Furthermore, if all the units G that make up 150 TO
If the width X of the TO n emitter layer 14 is narrowed, the share 111 flow of each unit GTO before turn-off will be equalized.

However, from t to tar/off, each control 1al
Since the impedance from the lfi pole to the external lead terminal differs depending on the position of each unit GTO, variations occur in the turn-off operation. For this reason, simply the unit G TO
It is not possible to sufficiently solve the conventional problems simply by narrowing the width of the n emitter.

Although the present invention has been described above for a case where it is applied to a GTO, it is clear that the present invention can also be applied to a transistor.

(Effects of the Invention) As explained above, according to the present invention, the lifetime of the carrier in each unit GTO arranged at a distance from the lead connection part is equal to the lifetime of the carrier in each unit GTO arranged in the vicinity of the lead connection part. By making the carry γ substantially shorter than the lifetime of the unit GTO, each unit GTO located further from the lead connection turns off earlier than one located closer, thereby causing the lead 1 at the final time of tar/off for each unit GTO which is 1 fK near the connection part! Concentrate the flow and each unit GTO remaining in #Lf
Since it is configured to turn on substantially simultaneously, the maximum breaking current can be increased.

Furthermore, each unit G arranged near the lead connection portion
The width of the force plate outer layer of the TO is narrower than that of each unit GTO arranged away from the lead connection part,
As a result, the maximum breaking current can be increased by making the shared currents more uniform especially at the final turn-off.

[Brief explanation of the drawing]

Fig. 1 is a plan view showing the cathode side plane pattern of a quarter of the GTO according to the present invention, Fig. 2 is a sectional view taken along the line A-A' in Fig. 1, and Fig. 3 (a) (bl is , the second aspect of the present invention
In the example, the first factor B-B', E-E line and C
-C, a cross-sectional view along line D-D; Figure 4 is a cross-sectional view of the GTO to explain the parallel operation of the unit GTO;
(bl is 1 in the embodiment of the present invention @1, Fig. 10)
B-B', B-E' lines and C-C, D-D
It is a sectional view along a line. l...Semiconductor base, 2...Cathode electrode, 3
...gate electrode, 13...p base layer, 1
4...N emitter layer, 20...Anode electrode,
C...Gate connection part

Claims (3)

[Claims] (1) At least three semiconductor layers having alternately different conductivity types are sequentially laminated between a pair of main surfaces of a semiconductor substrate, and one outermost layer is divided into strip-shaped regions and separated from each other. An intermediate layer exposed on the main surface and adjacent to the outermost layer is exposed on one main surface so as to surround the strip-shaped region, and each of the strip-shaped outermost layer and the other outermost layer includes:
The main electrodes are in low resistance contact with each other, and the control electrode is in low resistance contact with the intermediate layer, thereby forming a unit semiconductor element in each strip area, and the outermost layer of each strip area is a lead of the control electrode. In a semiconductor device that is arranged in multiple arrays with respect to a connection part, the lifetime of a unit semiconductor element portion including the strip-shaped outermost layer region arranged close to the lead connection part is determined by arranging the unit semiconductor element part away from the lead connection part. A semiconductor device characterized in that the length of the outermost layer is longer than that of a unit semiconductor element portion including the strip-shaped region of the outermost layer. (2) In claim 1, the lifetime of the unit semiconductor element portion including the strip-shaped outermost layer region arranged close to the lead connection portion and the life of the unit semiconductor element portion in other regions A short circuit region is provided in the outermost layer opposite to the outermost layer of each one of the strip-shaped strips with an adjacent intermediate layer, and the short circuit of the unit semiconductor element portions arranged close to the lead connection portion is determined. A semiconductor device characterized in that the size of a region is made smaller than that of a unit semiconductor element portion in another region. (3) In claim 1, the width of the strip-shaped region of the unit semiconductor element portion disposed in close proximity to the lead connection portion is narrower than that of the unit semiconductor element portion in other regions. A semiconductor device characterized by: