JPH0691246B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor switching device such as a gate turn-off thyristor and a transistor, and more particularly to a semiconductor device suitable for increasing its maximum breaking current.

(Background of the Invention) A large-capacity gate turn-off thyristor (hereinafter abbreviated as GTO) or transistor has an n-emitter layer composed of one or more strips each having a substantially constant width, and a semiconductor layer together with a base layer adjacent thereto. It is exposed on one main surface of the substrate, and one main electrode is brought into low resistance contact with each strip-shaped region,
A control electrode is brought into low resistance contact with the base layer so as to substantially surround each strip-shaped region, and the other main electrode is brought into low resistance contact with the other main surface of the semiconductor substrate. It is connected to a pair of main terminals and control terminals.

The turn-off operation will be described below by taking the GTO as an example.

The turn-off operation of the GTO having the above structure occurs, as is well known, by rapidly excluding excess carriers such as electrons and holes accumulated in the semiconductor substrate to the outside by a negative gate current.

Then, in order to make it easy to draw the gate current from the current conducting region as much as possible and to speed up the turn-off, an elongated strip-shaped cathode emitter layer (hereinafter, abbreviated as a unit GTO) is surrounded by the gate electrode as described above. ) Structure is adopted, and a large number of such structures are juxtaposed in the semiconductor substrate according to the current capacity.

As a unit GTO arrangement suitable for large capacity, a structure in which unit GTOs are arranged concentrically and in multiple rings in a semiconductor substrate has been devised conventionally (Japanese Patent Application No. 54-84964 and Japanese Patent Laid-Open No. Sho. 56-131955, etc.).

However, the conventional structure as described above also has a limit, and as the size of the semiconductor substrate increases, a problem arises in that the desired maximum breaking current cannot be obtained even if the number of unit GTOs is increased.

As a result of investigating the cause that the maximum cutoff current does not increase in proportion to the number of unit GTOs, the present inventors have found that as the semiconductor substrate has a larger diameter, the turn-off operation of the unit GTO in the plane of the semiconductor substrate is It was found that the nonuniformity became large and the current was transferred from the unit GTO that was turned off first to the unit GTO that was the most delayed in the turn-off operation, causing current concentration.

Further, it was found that there are two causes for increasing the nonuniformity of the turn-off operation between the unit GTOs in the semiconductor substrate.

One is that there is a large variation in the characteristics of the unit GTO itself. In the manufacturing process, the outer peripheral portion of the semiconductor substrate tends to have a shorter carrier lifetime than the central portion due to thermal strain and the like. By increasing the diameter of the semiconductor substrate, the distance between the outer peripheral portion and the central portion is increased. Becomes larger, the variation in the characteristics becomes larger accordingly.

Another cause is control electrode connection (external lead terminal)
This is because the gate current distributed to each unit GTO is nonuniform due to the impedance difference of the control electrodes of each unit GTO.

As described above, in the large-capacity GTO, the main electrode and the control electrode are exposed on one of the main surfaces, and each is brought into low resistance contact with the lead-out terminal to the outside by pressure welding.

In this case, when trying to press the both surfaces together, it is necessary to miniaturize the pressure contact electrodes, and it becomes difficult to align them.Therefore, only the main electrodes are pressed against the entire surface, and the control electrodes are connected to the external lead terminals by partial pressure contact. It is normal to

For this reason, the gate current of the unit GTO far away from the partial pressure contact portion has a longer distance to flow through the control electrode provided on the semiconductor substrate, and the impedance of the unit GTO near the partial pressure contact portion becomes longer. Due to the difference, the gate current flowing in each unit GTO becomes non-uniform.

Due to the above factors, there is a problem in the conventional structure that even if the diameter of the semiconductor substrate is increased, a desired breaking current proportional to the diameter cannot be obtained.

(Object of the Invention) An object of the present invention relates to a semiconductor device having a self-interrupting function, and in particular to provide a semiconductor device capable of increasing the interrupting current without affecting other characteristics such as ON voltage. It is in.

(Summary of the Invention) A feature of the present invention is that at least three semiconductor layers having different conductivity types are alternately laminated between a pair of main surfaces of a semiconductor substrate, and one outermost layer is , The strip-shaped regions are separated from each other and exposed on one main surface, and the intermediate layer adjacent to the outermost layer is exposed on the one main surface so as to surround the strip-shaped regions and strip-shaped. Each of the outermost layer and the other outermost layer of the main electrode has a low resistance contact with each other, the control electrode has a low resistance contact with the intermediate layer, each strip-shaped one outermost layer is a lead connection portion of the control electrode. In the case of multiple semiconductor devices arranged in parallel, the difference in impedance from each control electrode to the external lead terminal between each unit GTO arranged adjacent to the lead connection portion and including the strip-shaped one outermost layer. (Variation) is the lead connection part Compared to the impedance difference between each unit GTO arranged away from, based on the new finding that is originally small, the lifetime of the carrier in each unit GTO arranged away from the lead connection, By substantially shortening the carrier lifetime in each unit GTO arranged in the vicinity of the lead connecting portion, each unit GTO at a position far from the lead connecting portion
Turn off earlier than the closer ones, which results in each unit closer to the lead connection.
The point is that the current at the end of turn-off is concentrated on the GTO, and the last remaining unit GTOs are turned off at substantially the same time.

According to the results of the study by the present inventors, the instantaneous breaking current of each unit GTO is very large, and if the parallel operation at the final turn-off is made uniform, the entire breaking current can be greatly increased. Is.

Further, another feature of the present invention is based on the fact that the narrower the width of the strip-shaped one outermost layer is, the more uniform the current at the time of steady conduction between the unit GTOs and the shared current at the end of turn-off can be. The width of the one outermost layer of each unit GTO arranged in the vicinity of the lead connection part is configured to be narrower than that of each unit GTO arranged apart from the lead connection part. This is the point that the sharing current of 1 was further homogenized.

(Embodiment of the Invention) An embodiment in which the present invention is applied to a GTO will be described below with reference to the accompanying drawings.

1 and 2 show an embodiment of the present invention. Figure 1 shows GTO
FIG. 4B is a diagram showing a cathode side plane pattern of a quadrant, showing a case of a so-called intermediate ring gate structure in which a gate connection portion C ₁ is provided in the middle of a unit GTO array arranged in a ring shape and multiple concentric circles. ing. FIG. 2 is a sectional view taken along the line AA ′ of FIG.

As is well known to those skilled in the art, and as can be seen from the sectional view of FIG. 2, a p-emitter layer 11, an n-base layer 12, a p-base layer 13, and an n-emitter layer 14 are formed inside the semiconductor substrate 1. Is
A pn junction necessary for performing a thyristor operation is formed between the layers.

An anode electrode 20 is conductively connected to the p emitter layer 11, a cathode electrode 2 is conductively connected to the n emitter layer 14, and a gate electrode 3 and a gate connecting portion C ₁ are conductively connected to the p base layer 13, respectively.

Here, as shown in the figure, when the region close to the gate connection portion C ₁ is defined as the region II and the other regions are defined as the regions I and III, the lifetime of the region II corresponds to the regions I and III.
Is configured to have a substantially shorter lifetime.

Such lifetime control of the region II and the regions I and III can be easily realized by selectively irradiating an electron beam or γ-ray in addition to selective diffusion of heavy metal such as gold, that is, lifetime killer. Are well known to those skilled in the art.

In addition, as shown in FIGS.
By providing a high-concentration n ⁺ layer region in a part of the so-called p-emitter short-circuit structure and changing the short-circuit width, substantial life time control can be easily realized.

FIG. 5 (a) is a sectional view of regions I and III--that is, taken along line BB ', EE' in FIG. 1, and FIG. 5 (b).
2 is a sectional view of region II--that is, taken along the line CC ′, DD ′ in FIG. As is clear from the comparison between these figures, the time life can be shortened by increasing the short-circuit width of the p-emitter layer 11 (size of the n ⁺ layer).

Next, the turn-off operation of the GTO having the structure shown and described above will be described.

First, the state immediately before the turn-off signal is input to the GTO will be described. The current flowing in each unit GTO in the region II adjacent to the gate connection portion and the other regions I and III is larger in the region II due to the substantial difference in lifetime.

When a turn-off gate current flows between the gate electrode 3 and the cathode electrode 2 in such a state, the current is originally small and the regions I and III have a short lifetime.
Each unit GTO of 1 turns off first, and the current flowing there moves to each unit GTO of the region II close to the gate connection C ₁ .

By the way, since the region II is located near the gate connection portion C ₁ , the difference (variation) in impedance from each control electrode between each unit GTO included in this region II to the external lead terminal is equal to the above-mentioned gate connection. It is inherently smaller than that between the unit GTOs included in regions I and III relatively far away from section C ₁ .

Therefore, the turn-off operation in the region II at the end of turn-off is made uniform, and as a result, the overall maximum cutoff current can be improved.

The second embodiment of the present invention further configures the width of the outermost strip area of each unit GTO in the area II to be narrower than that of each unit GTO in the areas I and III. The equalization of the shared current among the unit GTOs and the equalization of the parallel operation at the end of turn-off make the effect of improving the maximum breaking current even greater.

The second embodiment of the present invention will be described below with reference to FIGS. FIG. 3 is a sectional view for explaining the structure of each unit GTO in each of the regions I to III in the second embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are respectively B- of FIG.
It is sectional drawing which follows the B ', EE' line and CC ', DD' line.

As can be seen from the comparison between FIGS. 3A and 3B, the difference between the two is the width of the n emitter layer 14. That is, FIG.
The width X2 of the n-emitter layer 14 of the unit GTO belonging to the region II adjacent to the gate connection portion C ₁ shown in FIG. 2 is the width of the n-emitter layer 14 of the unit GTO belonging to regions I and III of FIG. It is narrower than X1.

In order to improve the gate breakdown voltage and to widen the pressure contact area of the cathode electrode 2, an insulating film 4 of SiO ₂ is formed on a part of the p base layer 13 and the n emitter layer 14 on the exposed surface of the semiconductor substrate 1 on the side of the castor. Therefore, the widths of the cathode electrodes 2 shown in FIGS. 3A and 3B are the same.

FIG. 4 is shown in order to explain the parallel operation between unit GTOs. As shown in FIG. 4, all the GTOs are common except for the n emitter layer 14.

Assuming that the anode current iA flowing through the element A is larger than the anode current iB flowing through the element B, the potential V ₃₁ of the junction J ₃₁ of the element A is the potential V ₃₂ of the junction J ₃₂ of the element B. Get higher.

Therefore, a part of the anode current iA of the element A flows into the junction J ₃₂ of the element B via the gate electrode 3. That is, for the device B, an additional gate current iGA as shown in FIG. 4 flows.

As a result, the injection efficiency of the device B increases, the anode current iB flowing therethrough increases, and the injection efficiency of the device A decreases, so that the anode current iA flowing therethrough decreases. In this way, the unit GTOs connected in parallel have a function of trying to make the shared currents of both parties uniform.

Then, the narrower the width X of the n-emitter layer 14 is, the larger the effect of equalizing the shared current tends to be.

That is, the potentials V ₃₁ and V ₃₂ at the ends of the J ₃₁ and J ₃₂ junctions close to the gate electrode 3 are equalized by the gate electrode 3 as described above, but the width of each n emitter layer 14 is different. The potentials V ₃₁ ′ and V ₃₂ ′ of the J ₃₁ and J ₃₂ junctions in the central region of X are p base layer.
A potential difference is generated due to a voltage drop due to the lateral resistance of 13, and it is attempted to weaken the shared current equalizing effect due to this, but by narrowing the width X of the n emitter layer 14, This is because the potential difference can be reduced, and thus the shared current equalizing effect can be maintained.

As described above, narrowing the width X of the n-emitter layer 14 has the effect of correcting variations in characteristics that occur during the manufacturing process of the semiconductor substrate 1 and making the unit carrier currents of each unit GTO uniform. Therefore, the current flowing in each unit GTO in the region II of the present invention is much more uniform than in the regions I and III.

From this state, the region II is pulled to the regions I and III and reaches the turn-off state. Further, since the region II is in the region close to the gate connection part C ₁ , the turn-off between the unit GTOs is not affected by the difference (variation) in the impedance from each control electrode between the unit GTOs to the external lead terminal. Since the operation is also made uniform, the breaking current is greatly increased.

As described above, in the semiconductor device of the present invention, although the current at the time of turn-off is once concentrated in the region II of about 1/3 of the whole, the breaking current is about 1800A to 300
We were able to increase it to over 0A.

The cut-off current of a single unit GTO composed of each strip shown in Fig. 1 is as large as about 80 A or more, and the improvement in parallel operation has realized the above improvement. Presumed to be.

If all the unit GTOs that make up the large capacity GTO are n
If the width X of the emitter layer 14 is narrowed, the sharing current of each unit GTO before turn-off will be made uniform.

However, at the time of turn-off, the impedance from each control electrode to the external lead terminal varies depending on the position of each unit GTO, so that the turn-off operation varies. For this reason, the conventional problems cannot be sufficiently solved by simply narrowing the width of the n emitter of the unit GTO.

Although the case where the present invention is applied to the GTO has been described above, it is obvious that the present invention can also be applied to the transistor.

(Effect of the Invention) As described above, according to the present invention, the lifetime of the carrier in each unit GTO arranged apart from the lead connection unit is set to the unit GTO arranged in the vicinity of the lead connection unit. By substantially shortening the carrier lifetime in, the unit GTOs located far from the lead connection will turn off earlier than those located closer, thereby removing the lead connection from the lead connection. Since the current at the end of turn-off is concentrated on the unit GTOs located close to each other and the last-remaining unit GTOs are turned off substantially at the same time, the maximum breaking current can be increased.

Furthermore, each unit GT arranged near the lead connection portion
By configuring the width of the one outermost layer of O to be narrower than that of each unit GTO arranged apart from the lead connection portion, thereby further equalizing the shared current particularly at the end of turn-off. The maximum breaking current can be increased.

[Brief description of drawings]

FIG. 1 is a plan view showing a cathode side plane pattern of a quarter of a GTO according to the present invention, FIG. 2 is a sectional view taken along the line AA ′ of FIG. 1, and FIGS. 3 (a) and 3 (b). Are lines BB ', EE' and C- of FIG. 1 in the second embodiment of the present invention.
Sectional view taken along the lines C'and DD ', FIG. 4 is a sectional view of the GTO for explaining the parallel operation of the unit GTOs, and FIG. 5 (a).
(B) is B of FIG. 1 in the first embodiment of the present invention.
FIG. 6 is a cross-sectional view taken along the lines -B ', EE' and the lines CC ', DD'. 1 ... Semiconductor substrate, 2 ... Cathode electrode, 3 ... Gate electrode,
13 ... p base layer, 14 ... n emitter layer, 20 ... anode electrode, C ₁ ... gate connection part

Front Page Continuation (72) Inventor Hiroshi Fukui 4026 Kuji-machi, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi Co., Ltd. (56) Reference JP-A-57-201077 (JP, A) JP-A-59-86260 ( JP, A) JP 58-206159 (JP, A) JP 59-99769 (JP, A) JP 48-47779 (JP, A) JP 51-74586 (JP, A) JP 61-102065 (JP, A) JP-A-60-220971 (JP, A)

Claims (3)

[Claims] 1. At least three semiconductor layers alternately having different conductivity types are sequentially laminated between a pair of main surfaces of a semiconductor substrate, and one outermost layer is divided into strip regions and separated from each other. The intermediate layer exposed on one of the main surfaces and adjacent to the outermost layer is exposed on one of the main surfaces so as to surround the strip-shaped region, and each strip-shaped one outermost layer and the other outermost layer respectively. The main electrode is in low resistance contact, and the control electrode is in low resistance contact with the intermediate layer, whereby a unit semiconductor element is formed in each strip region, and each strip-shaped outermost layer is the gate lead of the control electrode. In a semiconductor device that is multiply arranged with respect to the connecting portion, the turn-off timing of the unit semiconductor element portion including the strip-shaped outermost layer region arranged in proximity to the gate lead connecting portion is set to the gate lead connecting portion. The width of the strip-shaped regions of the unit semiconductor element portions that are arranged closer to the gate lead connection portion than the width of the unit semiconductor element portion that includes the strip-shaped outermost layer regions that are arranged apart from each other. A semiconductor device characterized in that it is configured to be narrower than the width of the strip-shaped regions of the unit semiconductor element portions arranged apart from the lead connection portion so that the turn-off operations of the adjacent unit semiconductor element portions are made uniform. . 2. The control of the turn-off timing according to claim 1, wherein a lifetime of a unit semiconductor element portion including the strip-shaped outermost layer region arranged in proximity to the gate lead connecting portion is The semiconductor device is characterized in that it is made longer than that of the unit semiconductor element portion including the strip-shaped outermost layer region arranged apart from the gate lead connection portion. 3. The lifetime of a unit semiconductor device portion including the strip-shaped outermost layer region arranged in the vicinity of the gate lead connecting portion according to claim 2, and the unit semiconductor device of the other region. The difference between the lifetime of the part, the strip-shaped one outermost layer opposite to the outermost layer, a short-circuit region with the intermediate layer adjacent to it is provided, unit semiconductor elements arranged in proximity to the gate lead connection portion A semiconductor device realized by making the size of the short-circuited region of a part smaller than that of the unit semiconductor element part of the other region.