JPH0758777B2 - Gate turn-off thyristor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a gate turn-off thyristor (hereinafter referred to as “GTO thyristor”), and in particular, it has an element junction structure suitable for forcing a large current. Regarding GTO thyristors.

[Prior Art] Generally, a large capacity GTO thyristor is configured by arranging a large number of unit thyristors in a large diameter pellet and connecting these unit thyristors in parallel.

FIG. 3 is a top view of this type of GTO thyristor according to the prior art, and FIG. 4 is a sectional view taken along the line I--I in FIG. Third
In FIGS. 4 and 1, 1 is a pellet, 2 is a unit GTO thyristor, 4 is an anode electrode, 5 is a cathode electrode, 6 is a gate electrode, 7 is a gate-cathode insulating film, 11 is a first emitter layer, and 12 is The first base layer, 13 is the second base layer, 14 is the second emitter layer, 15 is the buffer layer, 16 is the emitter short-circuit region, and 16 'is the element isolation emitter short-circuit region.

A large-capacity GTO thyristor according to the prior art shown in FIGS. 3 and 4 is a multiple ring in which so-called unit GTO thyristors 2 are radially arranged in parallel in a pellet 1 which is a disk-shaped semiconductor substrate having a large diameter. It has a structure. Each unit thyristor 2 has a basic structure including a p-type first emitter layer 11, an n-type first base layer 12, a p-type second base layer 13 and an n-type second emitter layer 14. In order to increase the breakdown voltage of the semiconductor substrate, the first base layer 12
And a first emitter layer 11 are provided with a high impurity concentration buffer layer 15 made of the same conductive semiconductor as the first base layer 12, that is, an n-type semiconductor in this case.
It has a so-called pnipn junction structure with a reduced thickness of 12.

Further, in the GTO thyristor according to the illustrated prior art, the first base layer 12 and the buffer layer 15 adjacent to the first base layer 12 are connected to the anode electrode similarly to the emitter layer 11 via a high-concentration impurity layer made of the same conductor. 4 is provided with an emitter short-circuit region 16 for making a low resistance contact with the cathode 4 in the projected portion of the cathode electrode 5, and further, an emitter short-circuit region 16 'for element isolation is provided in the central portion and the peripheral portion of the pellet 1.

Note that, as a conventional technique related to the GTO thyristor having the above-described structure, for example, the Institute of Electrical Communication Material EDD-8
7-65 / SPC-87-49 (1987) PP27-35, EDD-88-57 / SPC
The techniques described in -88-55 (1988) PP77-84 and JP-A-55-39619 are known.

[Problems to be Solved by the Invention] A GTO thyristor in which an emitter short circuit region is formed in a pnipn junction structure according to the prior art described above is as shown in FIG.
At least one emitter short-circuit region 16 is formed in the projected portion of the second emitter layer 14 and configured. This structure is
This is suitable when the GTO thyristor is used separately as a single unit, and in the above-mentioned conventional technique, each unit GTO thyristor 2 is formed even if a large number of unit GTO thyristors 2 are formed in parallel in order to increase the capacity. They were formed to have the same structure.

However, in such a conventional technique, since the buffer layer 15 is formed of a high-concentration impurity layer and has low resistance, the short-circuit resistance R _SO in the buffer layer 15 becomes too small, and the element is reduced. The gate trigger current when turning on becomes large. For this reason, the GTO thyristor according to the related art cannot generate the potential drop due to the short-circuit resistance for turning on the element unless the gate trigger current is increased.
O It is impossible to turn on the thyristor, and some units G
There is a problem that only the TO thyristor is turned on and the unit GTO thyristor may be destroyed.

That is, the p-type second base layer 13 is formed via the gate electrode 6.
The gate trigger current input to the cathode current flows from the n-type second emitter layer 14 to the cathode electrode 5. At this time, the electron current injected from the n-type second emitter layer 14 is collected through the collector junction by the J ₂ junction between the n-type first base layer 12 and the p-type second base layer 13. The current flows into the emitter short-circuit region 16 through the n-type first base layer and the n-type buffer layer 15. Since this current flows in the emitter short-circuit region 16 and hardly flows in the p-type first emitter layer 11, the gate trigger current at the time of turning on the device becomes large, and when it is remarkable, the device cannot be fired. .

On the other hand, when the GTO thyristor is turned off, the residual carrier accumulated in the base layer must be promptly discharged to the outside by the input of the off-gate current, and the emitter short-circuit layer can be formed in advance. It is essential.

An object of the present invention is to improve the gate trigger characteristic of a large capacity GTO thyristor having a pnipn junction structure and unit GTO thyristors arranged in parallel in a multiple ring shape, and to make the device safe with a relatively small gate trigger current. Another object of the present invention is to provide a GTO thyristor having an emitter short circuit area that can be reliably turned on.

[Means for Solving the Problems] According to the present invention, the object is to provide a gate turn-off in which a plurality of unit gate turn-off thyristors having a pnipn structure and having an emitter short-circuit region are arranged in parallel in a semiconductor substrate. In the thyristor, the semiconductor substrate has a disk shape, and the plurality of unit gate turn-off thyristors are arranged concentrically around the center of the semiconductor substrate so as to have a plurality of ring shapes, and the emitter short circuit is performed. Regions are provided radially between the unit gate turn-off thyristors arranged in the ring shape and having a width narrower than the width between the unit gate turn-off thyristors and along the longitudinal direction of the cathode side emitter layer forming the unit gate turn-off thyristors. Between the rings where the unit gate turn-off thyristors are arranged and The projection of the emitter layer of the electrode side is achieved by not provided.

Further, the object is a gate turn-off thyristor having a pnipn structure and a plurality of unit gate turn-off thyristors having emitter short-circuit regions arranged in parallel in the semiconductor substrate, wherein the semiconductor substrate has a disk shape. , The plurality of unit gate turn-off thyristors,
Concentric circles centered on the center of the semiconductor substrate are arranged so as to form a plurality of rings, and the emitter short-circuit region is provided between unit gate turn-off thyristors between rings in which the plurality of unit gate turn-off thyristors are arranged. A cathode that is provided in a ring shape with a width narrower than the width between the rings and has a width narrower than the width between the unit gate turn-off thyristors between the unit gate turn-off thyristors arranged in a ring shape. This is achieved by being provided radially along the longitudinal direction of the side emitter layer and not provided in the projection portion of the emitter layer on the cathode electrode side of the unit gate turn-off thyristor.

[Operation] The invention according to claim 1 is a unit arranged in a ring shape.
Between the GTO, that is, between the cathode-side emitter layers forming the unit GTO, a short circuit layer is provided along the longitudinal direction of the cathode-side emitter layer with a width narrower than the width between the cathode-emitter layers, and It is configured without providing a short-circuit layer between adjacent rings.

According to the invention described in claim 1, the width of the short-circuit layer is narrower than the width between the adjacent cathode-side emitter layers, and the short-circuit layer is not provided between the adjacent rings. The area can be reduced. Therefore, the present invention can increase the short-circuit resistance and reduce the gate trigger current. Further, according to the present invention, since the short-circuit layer is provided along the longitudinal direction of the cathode side emitter layer, it is possible to uniformly discharge the carriers from the entire area of the unit GTO, which reduces turn-off performance. Thus, it is possible to obtain the effect that the operation is not nonuniform due to carrier interference between the rings of the cathode side emitter layer.

In addition to the configuration of the invention of claim 1, a ring-shaped short-circuit layer narrower than the width between the rings is provided between the rings of the unit GTOs arranged in a ring shape. It is configured. Therefore, the invention described in claim 2 does not increase the short-circuit resistance of the GTO so much and the gate trigger current is not increased as compared with the invention described in claim 1.

According to the invention described in claim 2, the ring-shaped short-circuit layer provided between the rings reduces the carrier inflow between the rings, reduces the interference between the rings, and operates each unit GTO. Can be improved, and as a result, large current switching can be performed.

[Embodiment] An embodiment of the GTO thyristor according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a top view of a four-divided portion showing a basic configuration example of the present invention, FIG. 2 is a cross-sectional view taken along the line II in FIG. 1, and reference numerals in FIGS. Is the same as the case of.

The GTO thyristor shown in FIG. 1 has a large number of unit GTO thyristors 2 in the pellet 1 centered around the gate electrode 6 for gate control current input (the example shown in FIG. In the double), they are arranged in parallel in a ring shape and a radial shape. Each of the unit GTO thyristors has a pnipn junction structure as shown in FIG. 2, in which the p-type first emitter layer 11 is formed on the anode electrode 4 exposed on the first main surface, and the n-type second thyristor is formed. The emitter layer 14 is the cathode electrode 5, the part of the p-type second base layer 13 exposed on the second main surface is the gate electrode 6 through the high-concentration region of the same conductivity type, and is low in Al or the like. Ohmic connection is made by resistance metal.

The GTO thyristor having the above-described structure has an n-type relatively low resistance between the p-type first emitter layer 11 and the high-resistance n-type (i layer) first base layer 12. Buffer layer
15 is formed, the short-circuit resistance R _SO is small when the emitter short-circuit region 16 is formed in the opposite projection regions of the n-type second emitter layer 14 as described in the section of the prior art. Too much, the gate trigger current becomes large,
The turn-on characteristics deteriorate.

Therefore, in order to improve the firing characteristic without impairing the gate turn-off characteristic, the basic configuration example of the present invention shown in FIG. 1 and FIG. 2 has the emitter short-circuit region 16 with the n-type second emitter. It is not provided in the projection area of the layer 14 but is formed in a ring shape in the projection area of the area where the gate electrode 6 of the p-type second base layer 13 is connected at the boundary of the unit GTO thyristors 2 arranged radially Configured. As a result, the current path in the buffer layer 15 in the projected portion of the n-type second emitter layer 14 extends laterally on the p-type first emitter layer 11 to reach the emitter short-circuit regions 16 and 16 '. Therefore, the short circuit resistance can be increased. Therefore, the collector current easily flows into the p-type first emitter layer 11, and according to the embodiment of the present invention, the GTO thyristor can be safely and surely turned on.

Particularly, in the large-capacity GTO thyristor as shown in the above-mentioned embodiment, the unit GTO thyristors 2 are concentrically arranged in parallel to form a multiple ring, so that an emitter short-circuit region is formed between the array rings of the unit GTO thyristor 2. When provided in a ring shape, the short-circuit resistance can be set to have an appropriate size, so that its turn-on characteristic can be greatly improved.

A large-capacity GTO thyristor with the structure described above
It has a high breakdown voltage of 000V or more, and can safely and reliably control a large current of 2000A or more without increasing conduction loss.

Further, such a GTO thyristor is suitable for use in a power conversion device through an inverter or a converter, and can form a large capacity power conversion device.

FIGS. 5 and 6 are top views of the four-divided portion showing the configurations of the first and second embodiments of the present invention, and the reference numerals in the figures are the same as those in FIG.

The first embodiment of the present invention shown in FIG. 5 is constituted by radially providing an emitter short-circuit region 16 in the projection portion of the gate electrode 6 between the unit GTO thyristors 2 arranged in a ring in the pellet 1. Even with such a structure, the same effect as in the case of the basic configuration example described with reference to FIGS. 1 and 2 can be obtained.

In addition, in the first embodiment of the present invention, as can be seen from FIG. 5, between the unit GTO2 arranged in a ring shape, that is, between the cathode side emitter layers forming the unit GTO,
The short-circuit layer 16 is provided along the longitudinal direction of the cathode-side emitter layer with a width narrower than the width between the cathode-emitter layers, and the short-circuit layer is not provided between the adjacent rings.

According to the first embodiment of the present invention as described above, the width of the short-circuit layer is narrower than the width between the adjacent cathode-side emitter layers, and the short-circuit layer is not provided between the adjacent rings. The area of the layers can be reduced. Therefore, this first embodiment can increase the short circuit resistance,
The gate trigger current can be reduced. Further, in this first embodiment, since the short-circuit layer is provided along the longitudinal direction of the cathode side emitter layer, the carriers can be uniformly discharged from the entire area of the unit GTO. It is possible to obtain an effect that the turn-off performance is not deteriorated and the operation is not nonuniform due to carrier interference between the rings of the cathode side emitter layer.

The second embodiment of the present invention shown in FIG. 6 is the basic configuration example of the present invention described with reference to FIGS. 1 and 2, and the first embodiment of the present invention described with reference to FIG. It has a combined structure. That is, the second embodiment of the present invention shown in FIG. 6 is a unit GT arranged radially in parallel.
O Emitter short circuit area formed in a ring shape with a width narrower than the width between the rings in the projection area of the boundary portion of the O thyristor 2, and radially formed in the projection area of the boundary portion of the unit GTO thyristor 2 arranged in a ring shape. And an emitter short circuit area.

Also in such a second embodiment of the present invention, as shown in FIG.
The same effects as the basic configuration example of the present invention described with reference to FIG. 2 can be obtained.

Furthermore, according to the second embodiment of the present invention, the width of the ring-shaped short-circuit layer provided between the rings is configured to be narrower than the width between the rings, so that the short-circuit resistance of the GTO is increased too much. Therefore, the gate trigger current is not increased as compared with the first embodiment. Further, according to the second embodiment of the present invention, the ring-shaped short-circuit layer provided between the rings reduces the carrier inflow between the rings and the interference between the rings to reduce the operation of each unit GTO. Uniformity can be improved. As a result, the second embodiment of the present invention can switch large current.

The pellet 1 which is the semiconductor substrate on which the large-capacity GTO thyristor according to the present invention is formed is usually silicon (Si).
However, gallium arsenide (GaAs) may be used.

[Advantages of the Invention] As described above, according to the present invention, a large capacity, a high breakdown voltage, a low loss, a gate trigger current, a holding current, and
It is possible to provide a high-performance GTO thyristor with a small latching current.

[Brief description of drawings]

FIG. 1 is a top view of a four-divided portion showing a basic configuration example of the present invention, FIG. 2 is a cross-sectional view taken along the line II in FIG. 1, and FIG. 3 is a top view showing the configuration of a conventional technique. Figure 4 shows I-
Sectional views I, FIGS. 5 and 6 are top views showing the configurations of the first and second embodiments of the present invention. 1 ... pellet, 2 ... unit GTO thyristor, 4 ... anode electrode, 5 ... cathode electrode, 6 ... gate electrode,
7 ... Gate-cathode insulating film, 11 ... first emitter layer, 12 ... first base layer, 13 ... second base layer, 14 ...
Second emitter layer, 15 ... Buffer layer, 16 ... Emitter short circuit area, 16 '... Element isolation emitter short circuit area.

Continuation of front page (56) Reference JP-A-1-171272 (JP, A) JP-A-56-10967 (JP, A) JP-A-51-86982 (JP, A) JP-A-57-153467 (JP , A)

Claims (2)

[Claims] 1. A plurality of unit gate turn-off thyristors having a pnipn structure and having an emitter short-circuit region,
In a gate turn-off thyristor arranged in parallel in a semiconductor substrate, the semiconductor substrate has a disk shape,
The plurality of unit gate turn-off thyristors are arranged concentrically around the center of the semiconductor body so as to form a plurality of rings, and the emitter short-circuit regions are arranged in the ring-shaped unit gate turn-off thyristors. A space narrower than the space between the unit gate turn-off thyristors and radially provided along the longitudinal direction of the cathode side emitter layer forming the unit gate turn-off thyristor, and between the rings and the cathodes in which the unit gate turn-off thyristors are arranged. A gate turn-off thyristor, which is not provided in the projection portion of the emitter layer on the electrode side. 2. A plurality of unit gate turn-off thyristors having a pnipn structure and having an emitter short-circuit region,
In a gate turn-off thyristor arranged in parallel in a semiconductor substrate, the semiconductor substrate has a disk shape,
The plurality of unit gate turn-off thyristors are arranged concentrically around the center of the semiconductor body so as to form a plurality of rings, and the emitter short-circuit region is arranged with the plurality of unit gate turn-off thyristors. Between the unit gate turn-off thyristors between the rings, it is provided in a ring shape with a width narrower than the width between the rings, and between the unit gate turn-off thyristors arranged in a ring shape, with a width narrower than the width between the unit gate turn-off thyristors, The gate turn-off thyristor is provided radially along the longitudinal direction of the cathode-side emitter layer forming the unit gate turn-off thyristor, and is not provided in the projection part of the emitter layer on the cathode electrode side of the unit gate turn-off thyristor. .