JP5446103B2 - Bidirectional thyristor - Google Patents

Bidirectional thyristor Download PDF

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JP5446103B2
JP5446103B2 JP2008058457A JP2008058457A JP5446103B2 JP 5446103 B2 JP5446103 B2 JP 5446103B2 JP 2008058457 A JP2008058457 A JP 2008058457A JP 2008058457 A JP2008058457 A JP 2008058457A JP 5446103 B2 JP5446103 B2 JP 5446103B2
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竜也 神村
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Sanken Electric Co Ltd
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Description

本発明は、双方向サイリスタに関し、特に電流上昇率並びに転流時臨界電圧上昇率を改善したトライアック（TRIAC；Triode AC Switch）と称される双方向サイリスタに関する。   The present invention relates to a bidirectional thyristor, and more particularly to a bidirectional thyristor called TRIAC (Triode AC Switch) having improved current rise rate and critical voltage rise rate during commutation.

下記特許文献１に開示されている双方向サイリスタは、ランプの点灯及び非点灯の動作制御、交流電流の導通及び非導通の動作制御等を行う制御素子として使用することができる。   The bidirectional thyristor disclosed in Patent Document 1 below can be used as a control element that performs operation control of lighting and non-lighting of a lamp, operation control of conduction and non-conduction of an alternating current, and the like.

例えば、コーナーゲート構造を有する双方向サイリスタは図１２乃至図１５に示すように構成されている。ここで、図１２は双方向サイリスタの第１の主電極及びゲート電極の平面形状を示す平面図、図１３は双方向サイリスタの表面側の半導体領域の平面形状を示す平面図、図１４は双方向サイリスタの断面構造図、図１５は双方向サイリスタの裏面側の半導体領域の平面形状を示す裏面図である。なお、図１４に示す断面図は、図１２、図１３、図１５の各図において切断線Ｆ１４−Ｆ１４における断面図である。   For example, a bidirectional thyristor having a corner gate structure is configured as shown in FIGS. Here, FIG. 12 is a plan view showing the planar shape of the first main electrode and the gate electrode of the bidirectional thyristor, FIG. 13 is a plan view showing the planar shape of the semiconductor region on the surface side of the bidirectional thyristor, and FIG. FIG. 15 is a back view showing the planar shape of the semiconductor region on the back side of the bidirectional thyristor. Note that the cross-sectional view shown in FIG. 14 is a cross-sectional view taken along the cutting line F14-F14 in each of FIGS.

コーナーゲート構造を有する双方向サイリスタは、図１２及び図１４に示すように、半導体基板１００の表面（図１４中、上側表面）１００Ａ上に第１の主電極１１１及びゲート電極１１２が配設され、半導体基板１００の裏面（図１４中、下側表面）１００Ｂ上に第２の主電極１１３が配設されている。半導体基板１００は、ｎ型半導体領域１０１と、ｎ型半導体領域１０１の表面１００Ａ側に隣接して配設されたｐ型ベース領域１０２と、ｎ型半導体領域１０１の裏面１００Ｂ側に隣接して配設されたｐ型ベース領域１０３と、ｐ型ベース領域１０２の表面１００Ａ側に配設されたｎ型エミッタ領域１０４と、ｐ型ベース領域１０３の裏面側１００Ｂ側に配設されたｎ型エミッタ領域１０５と、ｐ型ベース領域１０２の表面１００Ａ側であってｎ型エミッタ領域１０４に離間して配設されたｎ型ゲート領域１０６とを備えている。   In the bidirectional thyristor having the corner gate structure, as shown in FIGS. 12 and 14, the first main electrode 111 and the gate electrode 112 are disposed on the surface 100A of the semiconductor substrate 100 (the upper surface in FIG. 14). The second main electrode 113 is disposed on the back surface (lower surface in FIG. 14) 100B of the semiconductor substrate 100. The semiconductor substrate 100 is disposed adjacent to the n-type semiconductor region 101, the p-type base region 102 disposed adjacent to the front surface 100A side of the n-type semiconductor region 101, and the back surface 100B side of the n-type semiconductor region 101. The p-type base region 103 provided, the n-type emitter region 104 disposed on the surface 100A side of the p-type base region 102, and the n-type emitter region disposed on the back surface side 100B of the p-type base region 103 105, and an n-type gate region 106 disposed on the surface 100A side of the p-type base region 102 and spaced apart from the n-type emitter region 104.

第１の主電極１１１は、ｐ型ベース領域１０２上及びｎ型エミッタ領域１０４上に配設されており、双方に電気的に接続されている。ゲート電極１１２は、ｐ型半導体領域１０２上及びｎ型ゲート領域１０６上に配設され、双方に電気的に接続されている。第２の主電極１１３は、ｐ型ベース領域１０３及びｎ型エミッタ領域１０４上に配設されており、双方に電気的に接続されている。   The first main electrode 111 is disposed on the p-type base region 102 and the n-type emitter region 104 and is electrically connected to both. The gate electrode 112 is disposed on the p-type semiconductor region 102 and the n-type gate region 106 and is electrically connected to both. The second main electrode 113 is disposed on the p-type base region 103 and the n-type emitter region 104, and is electrically connected to both.

ゲート領域１０６及びゲート電極１１２は、図１３中、半導体基板１００の表面１００Ａの左下コーナーに配設されている。ｎ型エミッタ領域１０４は、半導体基板１００Ａの左辺及び左上コーナーから右上コーナーに渡って配設されている。また、ｎ型エミッタ領域１０５は、半導体基板１００の裏面１００Ｂの左下コーナー及び下辺から右上コーナーに渡って配設されている。   The gate region 106 and the gate electrode 112 are disposed in the lower left corner of the surface 100A of the semiconductor substrate 100 in FIG. The n-type emitter region 104 is disposed from the left side and upper left corner of the semiconductor substrate 100A to the upper right corner. Further, the n-type emitter region 105 is disposed from the lower left corner and the lower side of the back surface 100B of the semiconductor substrate 100 to the upper right corner.

この種の双方向サイリスタは、ｎ型エミッタ領域１０４、ｐ型ベース領域１０２、ｎ型半導体領域１０１及びｐ型ベース領域１０３の４つの半導体領域により構成される第１の主サイリスタと、ｐ型ベース領域１０２、ｎ型半導体領域１０１、ｐ型ベース領域１０３及びｎ型エミッタ領域１０５の４つの半導体領域により構成される第２の主サイリスタと、ｎ型ゲート領域１０６、ｐ型ベース領域１０２、ｎ型半導体領域１０１、ｐ型ベース領域１０３及びｎエミッタ領域１０５により構成されるゲート機構部（補助サイリスタ）とを有する。そして、双方向サイリスタは以下の４つのモードにおいてターンオン動作を行う。   This type of bidirectional thyristor includes a first main thyristor composed of four semiconductor regions, an n-type emitter region 104, a p-type base region 102, an n-type semiconductor region 101, and a p-type base region 103, and a p-type base. A second main thyristor composed of four semiconductor regions: a region 102, an n-type semiconductor region 101, a p-type base region 103, and an n-type emitter region 105; an n-type gate region 106; a p-type base region 102; A gate mechanism portion (auxiliary thyristor) including a semiconductor region 101, a p-type base region 103, and an n-emitter region 105; The bidirectional thyristor performs a turn-on operation in the following four modes.

（１）第１のモード
第１のモードは、第１の主電極１１１を基準にして第２の主電極１１３が正電位のときに、ゲート電極１１２を正電位にし、ターンオンを実行する。この第１のモードにおいては、第２の主電極１１３からｐ型ベース領域１０３、ｎ型半導体領域１０１、ｐ型ベース領域１０２、ｎ型エミッタ領域１０４のそれぞれを通して第１の主電極１１１に主電流が流れる。 (1) First Mode In the first mode, when the second main electrode 113 is at a positive potential with respect to the first main electrode 111, the gate electrode 112 is set at a positive potential and turn-on is executed. In this first mode, the main current flows from the second main electrode 113 to the first main electrode 111 through the p-type base region 103, the n-type semiconductor region 101, the p-type base region 102, and the n-type emitter region 104. Flows.

（２）第２のモード
第２のモードは、第１の主電極１１１を基準にして第２の主電極１１３が正電位のときに、ゲート電極１１２を負電位にし、ターンオンを実行する。第２のモードにおいては、第１のモードと同様に、第２の主電極１１３からｐ型ベース領域１０３、ｎ型半導体領域１０１、ｐ型ベース領域１０２、ｎ型エミッタ領域１０４のそれぞれを通して第１の主電極１１１に主電流が流れる。 (2) Second Mode In the second mode, when the second main electrode 113 is at a positive potential with respect to the first main electrode 111, the gate electrode 112 is set at a negative potential and turn-on is executed. In the second mode, as in the first mode, the first main electrode 113 passes through the p-type base region 103, the n-type semiconductor region 101, the p-type base region 102, and the n-type emitter region 104. A main current flows through the main electrode 111.

（３）第３のモード
第３のモードは、第１の主電極１１１を基準にして第２の主電極１１３が負電位のときに、ゲート電極１１２を負電位にし、ターンオンを実行する。第３のモードにおいては、第１の主電極１１１からｐ型ベース領域１０２、ｎ型半導体領域１０１、ｐ型ベース領域１０３、ｎ型エミッタ領域１０５のそれぞれを通して第２の主電極１１３に主電流が流れる。 (3) Third Mode In the third mode, when the second main electrode 113 has a negative potential with respect to the first main electrode 111, the gate electrode 112 is set to a negative potential and turn-on is executed. In the third mode, a main current flows from the first main electrode 111 to the second main electrode 113 through the p-type base region 102, the n-type semiconductor region 101, the p-type base region 103, and the n-type emitter region 105. Flowing.

（４）第４のモード
第４のモードは、第１の主電極１１１を基準にして第２の主電極１１３が負電位のときに、ゲート電極１１２を正電位にし、ターンオンを実行する。第４のモードにおいては、第３のモードと同様に、第１の主電極１１１からｐ型ベース領域１０２、ｎ型半導体領域１０１、ｐ型ベース領域１０３、ｎ型エミッタ領域１０５のそれぞれを通して第２の主電極１１３に主電流が流れる。
特公昭５０−８３１４号公報 (4) Fourth Mode In the fourth mode, when the second main electrode 113 is at a negative potential with respect to the first main electrode 111, the gate electrode 112 is set at a positive potential and turn-on is executed. In the fourth mode, as in the third mode, the second main mode 111 passes through the p-type base region 102, the n-type semiconductor region 101, the p-type base region 103, and the n-type emitter region 105, respectively. The main current flows through the main electrode 113.
Japanese Patent Publication No. 50-8314

しかしながら、前述の双方向サイリスタにおいては、以下の点について配慮がなされていなかった。   However, in the above-described bidirectional thyristor, the following points have not been considered.

（１）第１の主サイリスタ及び第２の主サイリスタの相互の構造や形状には対称性がないので、第１の主電極１１１とゲート電極１１２との間の電位分布や素子トリガー時の電流分布が不均一になる。このため、第１及び第２の主サイリスタの通電初期に流れる電流密度が大きいと、電流集中により双方向サイリスタに破壊が生じる。 (1) Since there is no symmetry in the structure and shape of the first main thyristor and the second main thyristor, the potential distribution between the first main electrode 111 and the gate electrode 112 and the current when the element is triggered Distribution becomes uneven. For this reason, when the current density flowing in the initial energization of the first and second main thyristors is large, the bidirectional thyristor is destroyed due to current concentration.

（２）第１及び第２の主サイリスタの通電初期に流れる電流密度を低減するためには、双方の主サイリスタの通電初期に動作する領域を広げ、かつ双方の主サイリスタをより均一に動作させる必要がある。しかしながら、前述のように、第１及び第２の主サイリスタの相互の構造や形状には対称性がないので、双方の主サイリスタにおいて均一な動作をすることが難しく、電流集中が発生しやすい。 (2) In order to reduce the current density that flows in the initial energization of the first and second main thyristors, the area that operates in the initial energization of both main thyristors is expanded, and both main thyristors are operated more uniformly. There is a need. However, as described above, since the mutual structure and shape of the first and second main thyristors are not symmetrical, it is difficult to perform a uniform operation in both the main thyristors, and current concentration tends to occur.

（３）前述の双方向サイリスタが例えば交流電流の制御素子として使用される場合において、第１の主サイリスタ、第２の主サイリスタのそれぞれは交互に動作する。このとき、一方の主サイリスタが非導通（オフ）状態にあっても半導体基板１００内にはキャリアが残存し、この残存するキャリアが逆方向電圧印加時にトリガー電流となり、導通（オン）状態となる誤動作が生じる。この誤動作は逆方向電圧の立ち上がりが速いほど発生しやすい。ここで、誤動作に対する耐量は転流時臨界電圧上昇率（ｄｖ／ｄｔ）ｃによって定義されている。この転流時臨界電圧上昇率（ｄｖ／ｄｔ）ｃを大きくすれば、誤動作を防止することができる。 (3) When the above-described bidirectional thyristor is used as, for example, an alternating current control element, each of the first main thyristor and the second main thyristor operates alternately. At this time, even if one of the main thyristors is in a non-conduction (off) state, carriers remain in the semiconductor substrate 100, and the remaining carriers become a trigger current when a reverse voltage is applied, and are in a conduction (on) state. A malfunction occurs. This malfunction is more likely to occur as the reverse voltage rises faster. Here, the tolerance for malfunction is defined by the rate of increase in critical voltage at the time of commutation (dv / dt) c. If this critical voltage rise rate (dv / dt) c during commutation is increased, malfunction can be prevented.

（４）転流時臨界電圧上昇率（ｄｖ／ｄｔ）ｃを改善するためには、双方の主サイリスタ内に残存するキャリアが相互に影響を及ぼさない構造を採用することが重要である。第１の主サイリスタと第２の主サイリスタとの間の離間距離を大きくすれば、残存するキャリアの相互の影響は小さくなる。しかしながら、半導体チップサイズが増大し、双方向サイリスタの小型化を実現することが難しい。 (4) In order to improve the critical voltage increase rate (dv / dt) c during commutation, it is important to adopt a structure in which carriers remaining in both main thyristors do not affect each other. If the separation distance between the first main thyristor and the second main thyristor is increased, the mutual influence of the remaining carriers is reduced. However, the semiconductor chip size increases, and it is difficult to reduce the size of the bidirectional thyristor.

（５）また、主サイリスタ内にキャリアを捕獲する重金属を拡散し、キャリアのライフタイムを短縮することにより、残存するキャリアを消滅させる技術を採用することが可能である。この技術を採用すれば、転流時臨界電圧上昇率（ｄｖ／ｄｔ）ｃを改善することができる。しかしながら、重金属は双方向サイリスタの電気的特性や物理的特性に悪影響を及ぼす。例えば、重金属は、ゲートトリガー電流ＩGTの増加を招き、又素子抵抗の増加に伴う発熱量の増加によって電流上昇率（ｄｉ／ｄｔ）耐量の低下を誘発する。 (5) It is also possible to employ a technique for erasing remaining carriers by diffusing heavy metals that capture carriers into the main thyristor and shortening the lifetime of the carriers. If this technique is adopted, the critical voltage increase rate (dv / dt) c during commutation can be improved. However, heavy metals adversely affect the electrical and physical characteristics of bidirectional thyristors. For example, heavy metals, causes an increase of the gate trigger current I GT, also induces a decrease in the rate of current rise (di / dt) capability by increasing the heating value with an increase in device resistance.

本発明は上記課題を解決するためになされたものである。従って、本発明は、双方の主サイリスタの通電初期に流れる電流密度を低減するとともに、転流時臨界電圧上昇率（ｄｖ／ｄｔ）ｃを改善することができる双方向サイリスタを提供することである。更に、本発明は、小型化を実現しつつ、電気的特性や物理的特性を向上することができる双方向サイリスタを提供することである。   The present invention has been made to solve the above problems. Accordingly, the present invention is to provide a bidirectional thyristor capable of reducing the current density flowing in the initial energization of both main thyristors and improving the critical voltage increase rate (dv / dt) c during commutation. . Furthermore, this invention is providing the bidirectional thyristor which can improve an electrical property and a physical characteristic, implement | achieving size reduction.

上記課題を解決するために、本発明の実施の形態に係る双方向サイリスタは、半導体基板と、半導体基板の一方の表面に配設された第１の主電極及びゲート電極と、半導体基板の一方の表面と反対の他方の表面上に配設された第２の主電極と、を備え、半導体基板が、第１の導電型の第１の半導体領域と、第１の半導体領域の一方の表面側に隣接して配設された前記第１の導電型とは逆の第２の導電型の第２の半導体領域と、第１の半導体領域の他方の表面側に隣接して配設された第２の導電型の第３の半導体領域と、第２の半導体領域の一方の表面側に配設された第１の導電型の第４の半導体領域と、第３の半導体領域の他方の表面側に配設された第１の導電型の第５の半導体領域と、第２の半導体領域の一方の表面側に第４の半導体領域と離間して配設された第１の導電型の第６の半導体領域と、を備え、第１の主電極が第２の半導体領域及び第４の半導体領域に電気的に接続され、第２の主電極が第３の半導体領域及び第５の半導体領域に電気的に接続され、ゲート電極が第２の半導体領域及び第６の半導体領域に電気的に接続された双方向サイリスタであって、
長手方向に終端がない閉じた平面形状を有する第６の半導体領域と、第６の半導体領域の幅方向の一方の側に隣り合ってゲート電極と第２の半導体領域とを電気的に接続する第１の接続部と、第６の半導体領域の幅方向の前記一方の側において、第１の接続部から第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有する第４の半導体領域と、この第４の半導体領域の幅方向の第１の接続部とは反対側の一方の側に隣り合って第１の主電極と第２の半導体領域とを電気的に接続する第２の接続部と、第６の半導体領域の幅方向の一方の側と反対側の他方の側において、第６の半導体領域から第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有し、第１の主電極と第２の半導体領域とを電気的に接続する第３の接続部とを備え、第５の半導体領域の平面形状は、長手方向に終端がない閉じた平面形状を有し、半導体基板の一方の表面の法線方向から見て第５の半導体領域と第６の半導体領域との重複部が均一幅を有し、同心のリング形状である。 In order to solve the above problems, a bidirectional thyristor according to an embodiment of the present invention includes a semiconductor substrate, a first main electrode and a gate electrode disposed on one surface of the semiconductor substrate, and one of the semiconductor substrates. A second main electrode disposed on the other surface opposite to the first surface, wherein the semiconductor substrate has a first semiconductor region of the first conductivity type and one surface of the first semiconductor region. A second semiconductor region of a second conductivity type opposite to the first conductivity type disposed adjacent to the first semiconductor region, and disposed adjacent to the other surface side of the first semiconductor region A third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type disposed on one surface side of the second semiconductor region, and the other surface of the third semiconductor region A fifth semiconductor region of the first conductivity type disposed on the side, and a fourth semiconductor region on one surface side of the second semiconductor region A sixth semiconductor region of the first conductivity type that is spaced apart, and the first main electrode is electrically connected to the second semiconductor region and the fourth semiconductor region, A bidirectional thyristor having a main electrode electrically connected to the third semiconductor region and the fifth semiconductor region, and a gate electrode electrically connected to the second semiconductor region and the sixth semiconductor region;
A sixth semiconductor region having a closed planar shape having no end in the longitudinal direction is electrically connected to the gate electrode and the second semiconductor region adjacent to one side in the width direction of the sixth semiconductor region. On the one side in the width direction of the first connection portion and the sixth semiconductor region, the first connection portion is closed without any end in the longitudinal direction from the first connection portion to the entire circumference in the longitudinal direction of the sixth semiconductor region. A fourth semiconductor region having a planar shape, and a first main electrode and a second semiconductor region adjacent to one side opposite to the first connection portion in the width direction of the fourth semiconductor region; A second connection portion that electrically connects the sixth semiconductor region and the other side opposite to one side in the width direction of the sixth semiconductor region. It has a closed planar shape with no end in the longitudinal direction over the circumference, and the first main electrode and the second semiconductor A third connecting portion that electrically connects the region, and the planar shape of the fifth semiconductor region has a closed planar shape that does not end in the longitudinal direction, and is normal to one surface of the semiconductor substrate When viewed from the direction, the overlapping portion of the fifth semiconductor region and the sixth semiconductor region has a uniform width and has a concentric ring shape.

本発明に係る双方向サイリスタにおいて、半導体基板と、半導体基板の一方の表面に配設された第１の主電極及びゲート電極と、半導体基板の一方の表面と反対の他方の表面上に配設された第２の主電極と、を備え、半導体基板が、第１の導電型の第１の半導体領域と、第１の半導体領域の一方の表面側に隣接して配設された第１の導電型とは逆の第２の導電型の第２の半導体領域と、第１の半導体領域の他方の表面側に隣接して配設された第２の導電型の第３の半導体領域と、第２の半導体領域の一方の表面側に配設された第１の導電型の第４の半導体領域と、第３の半導体領域の他方の表面側に配設された第１の導電型の第５の半導体領域と、第２の半導体領域の一方の表面側に第４の半導体領域と離間して配設された第１の導電型の第６の半導体領域と、を備え、第１の主電極が第２の半導体領域及び第４の半導体領域に電気的に接続され、第２の主電極が第３の半導体領域及び第５の半導体領域に電気的に接続され、ゲート電極が第２の半導体領域及び第６の半導体領域に電気的に接続された双方向サイリスタであって、長手方向に終端がない閉じた平面形状を有する第６の半導体領域と、第６の半導体領域の幅方向の一方の側に隣り合ってゲート電極と第２の半導体領域とを電気的に接続する第１の接続部と、第６の半導体領域の幅方向の一方の側において、第１の接続部から第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有する第４の半導体領域と、第４の半導体領域の幅方向の第１の接続部とは反対側の一方の側に隣り合って第１の主電極と第２の半導体領域とを電気的に接続する第２の接続部と、第６の半導体領域の幅方向の一方の側と反対側の他方の側において、第６の半導体領域から第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有し、第１の主電極と第２の半導体領域とを電気的に接続する第３の接続部とを備え、第６の半導体領域の平面形状がリング形状により構成され、第４の半導体領域の平面形状が第６の半導体領域の外側に形成され、第５の半導体領域の平面形状が第６の半導体領域の内側に形成されている。 In the bidirectional thyristor according to the present invention, the semiconductor substrate, the first main electrode and the gate electrode disposed on one surface of the semiconductor substrate, and the other surface opposite to the one surface of the semiconductor substrate are disposed. A first semiconductor region having a first conductivity type, and a first semiconductor region disposed adjacent to one surface side of the first semiconductor region. A second semiconductor region of a second conductivity type opposite to the conductivity type; a third semiconductor region of a second conductivity type disposed adjacent to the other surface side of the first semiconductor region; A fourth semiconductor region of the first conductivity type disposed on one surface side of the second semiconductor region and a first conductivity type of first semiconductor layer disposed on the other surface side of the third semiconductor region. 5 of the first conductivity type disposed on one surface side of the fifth semiconductor region and the second semiconductor region and spaced apart from the fourth semiconductor region. The first main electrode is electrically connected to the second semiconductor region and the fourth semiconductor region, and the second main electrode is connected to the third semiconductor region and the fifth semiconductor region. A sixth semiconductor having a closed planar shape that is electrically connected and has a gate electrode electrically connected to the second semiconductor region and the sixth semiconductor region, and has no longitudinal termination. A first connection part that electrically connects the gate electrode and the second semiconductor region adjacent to one side in the width direction of the sixth semiconductor region, and a width direction of the sixth semiconductor region On one side, a fourth semiconductor region having a closed planar shape with no end in the longitudinal direction from the first connection portion to the entire circumference in the longitudinal direction of the sixth semiconductor region; and Adjacent to one side opposite to the first connecting portion in the width direction A second connecting portion that electrically connects the main electrode of the second semiconductor region to the second semiconductor region, and the other side opposite to one side in the width direction of the sixth semiconductor region from the sixth semiconductor region A third connection having a closed planar shape that does not end in the longitudinal direction over the entire circumference of the sixth semiconductor region and electrically connecting the first main electrode and the second semiconductor region. A planar shape of the sixth semiconductor region is formed by a ring shape, a planar shape of the fourth semiconductor region is formed outside the sixth semiconductor region, and a planar shape of the fifth semiconductor region is the first shape 6 is formed inside the semiconductor region.

また、本発明に係る双方向サイリスタにおいて、半導体基板と、半導体基板の一方の表面に配設された第１の主電極及びゲート電極と、半導体基板の一方の表面と反対の他方の表面上に配設された第２の主電極と、を備え、半導体基板が、第１の導電型の第１の半導体領域と、第１の半導体領域の一方の表面側に隣接して配設された第１の導電型とは逆の第２の導電型の第２の半導体領域と、第１の半導体領域の他方の表面側に隣接して配設された第２の導電型の第３の半導体領域と、第２の半導体領域の一方の表面側に配設された第１の導電型の第４の半導体領域と、第３の半導体領域の他方の表面側に配設された第１の導電型の第５の半導体領域と、第２の半導体領域の一方の表面側に第４の半導体領域と離間して配設された第１の導電型の第６の半導体領域と、を備え、第１の主電極が第２の半導体領域及び第４の半導体領域に電気的に接続され、第２の主電極が第３の半導体領域及び第５の半導体領域に電気的に接続され、ゲート電極が第２の半導体領域及び第６の半導体領域に電気的に接続された双方向サイリスタであって、長手方向に終端がない閉じた平面形状を有する第６の半導体領域と、第６の半導体領域の幅方向の一方の側に隣り合ってゲート電極と第２の半導体領域とを電気的に接続する第１の接続部と、第６の半導体領域の幅方向の一方の側において、第１の接続部から第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有する第４の半導体領域と、第４の半導体領域の幅方向の第１の接続部とは反対側の一方の側に隣り合って第１の主電極と第２の半導体領域とを電気的に接続する第２の接続部と、第６の半導体領域の幅方向の一方の側と反対側の他方の側において、第６の半導体領域から第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有し、第１の主電極と第２の半導体領域とを電気的に接続する第３の接続部とを備え、前記第６の半導体領域の平面形状がリング形状により構成され、前記第４の半導体領域の平面形状が前記第６の半導体領域の内側に形成され、前記第５の半導体領域の平面形状が前記第６の半導体領域の外側に形成されている。 Further, in the bidirectional thyristor according to the present invention, the semiconductor substrate, the first main electrode and the gate electrode disposed on one surface of the semiconductor substrate, and the other surface opposite to the one surface of the semiconductor substrate. A first main region of the first conductivity type, and a first semiconductor region disposed adjacent to one surface side of the first semiconductor region. A second semiconductor region of the second conductivity type opposite to the first conductivity type, and a third semiconductor region of the second conductivity type disposed adjacent to the other surface side of the first semiconductor region A fourth semiconductor region of the first conductivity type disposed on one surface side of the second semiconductor region, and a first conductivity type disposed on the other surface side of the third semiconductor region First conductive layer disposed on one surface side of the fifth semiconductor region and the second semiconductor region and spaced apart from the fourth semiconductor region. The first main electrode is electrically connected to the second semiconductor region and the fourth semiconductor region, and the second main electrode is electrically connected to the third semiconductor region and the fifth semiconductor region. A bidirectional thyristor electrically connected to a semiconductor region and having a gate electrode electrically connected to the second semiconductor region and the sixth semiconductor region, and having a closed planar shape having no end in the longitudinal direction. 6 semiconductor region, a first connection part that is adjacent to one side in the width direction of the sixth semiconductor region and electrically connects the gate electrode and the second semiconductor region, and A fourth semiconductor region having a closed planar shape with no end in the longitudinal direction from the first connection portion to the entire circumference in the longitudinal direction of the sixth semiconductor region on one side in the width direction; Adjacent to one side opposite to the first connecting portion in the width direction of the semiconductor region A second connecting portion for electrically connecting the first main electrode and the second semiconductor region, and a second side opposite to one side in the width direction of the sixth semiconductor region. A first planar electrode having a closed planar shape with no end in the longitudinal direction over the entire circumference in the longitudinal direction of the sixth semiconductor region from the semiconductor region, and electrically connecting the first main electrode and the second semiconductor region. 3, the planar shape of the sixth semiconductor region is formed by a ring shape, the planar shape of the fourth semiconductor region is formed inside the sixth semiconductor region, and the fifth semiconductor region A planar shape of the semiconductor region is formed outside the sixth semiconductor region.

本発明によれば、第１及び第２の主サイリスタの通電初期に流れる電流密度を低減するとともに、転流時臨界電圧上昇率（ｄｖ／ｄｔ）ｃを改善することができる双方向サイリスタを提供することができる。   According to the present invention, there is provided a bidirectional thyristor capable of reducing the current density flowing in the initial energization of the first and second main thyristors and improving the commutation critical voltage increase rate (dv / dt) c. can do.

更に、本発明によれば、小型化を実現しつつ、電気的特性や物理的特性を向上することができる双方向サイリスタを提供することができる。   Furthermore, according to the present invention, it is possible to provide a bidirectional thyristor that can improve electrical characteristics and physical characteristics while realizing miniaturization.

次に、図面を参照して、本発明の実施の形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、現実のものとは異なる。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれている場合がある。   Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. In addition, there may be a case where the dimensional relationships and ratios are different between the drawings.

また、以下に示す実施の形態はこの発明の技術的思想を具体化するための装置や方法を例示するものであって、この発明の技術的思想は各構成部品の配置等を下記のものに特定するものでない。この発明の技術的思想は、特許請求の範囲において、種々の変更を加えることができる。   Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is to arrange the components and the like as follows. Not specific. The technical idea of the present invention can be variously modified within the scope of the claims.

（第１の実施の形態）
本発明の第１の実施の形態は、この発明の基本的な構造を有する双方向サイリスタを説明するものである。 (First embodiment)
The first embodiment of the present invention describes a bidirectional thyristor having the basic structure of the present invention.

［双方向サイリスタのデバイス構造］
図１乃至図４に示すように、第１の実施の形態に係る双方向サイリスタ（トライアック）１は、半導体基板１０と、半導体基板１０の一方の表面１０Ａ（図１中、上側表面）上に配設された第１の主電極２１（Ｔ１）及びゲート電極２３（Ｇ）と、半導体基板１０の一方の表面１０Ａと反対の他方の表面１０Ｂ（図１中、下側裏面）上に配設された第２の主電極２２（Ｔ２）とを備えている。 [Device structure of bidirectional thyristor]
As shown in FIGS. 1 to 4, the bidirectional thyristor (triac) 1 according to the first embodiment is formed on a semiconductor substrate 10 and one surface 10A of the semiconductor substrate 10 (upper surface in FIG. 1). Arranged on the first main electrode 21 (T1) and the gate electrode 23 (G) disposed on the other surface 10B (the lower back surface in FIG. 1) opposite to the one surface 10A of the semiconductor substrate 10. Second main electrode 22 (T2).

半導体基板１０は、第１の導電型の第１の半導体領域１１と、第１の半導体領域１１の一方の表面１０Ａ側に隣接して配設された第１の導電型とは逆の第２の導電型の第２の半導体領域１２と、第１の半導体領域１１の他方の表面１０Ｂ側に隣接して配設された第２の導電型の第３の半導体領域１３と、第２の半導体領域１２の一方の表面１０Ａ側に配設された第１の導電型の第４の半導体領域１４と、第３の半導体領域１３の他方の表面１０Ｂ側に配設された第１の導電型の第５の半導体領域１５と、第２の半導体領域１２の一方の表面１０Ａ側に第４の半導体領域１４と離間して配設された第１の導電型の第６の半導体領域１６とを備えている。ここで、第１の実施の形態において、第１の導電型はｎ型であり、第２の導電型はｐ型である。従って、第１の半導体領域１１、第４の半導体領域１４、第５の半導体領域１５及び第６の半導体領域はｎ型半導体領域であり、第２の半導体領域及び第３の半導体領域はｐ型半導体領域である。   The semiconductor substrate 10 includes a first conductivity type first semiconductor region 11 and a second conductivity type opposite to the first conductivity type disposed adjacent to one surface 10A side of the first semiconductor region 11. A second semiconductor region 12 of the second conductivity type, a third semiconductor region 13 of the second conductivity type disposed adjacent to the other surface 10B side of the first semiconductor region 11, and a second semiconductor The first conductivity type fourth semiconductor region 14 disposed on one surface 10A side of the region 12 and the first conductivity type disposed on the other surface 10B side of the third semiconductor region 13. A fifth semiconductor region 15 and a sixth semiconductor region 16 of the first conductivity type disposed on the one surface 10A side of the second semiconductor region 12 and spaced apart from the fourth semiconductor region 14 are provided. ing. Here, in the first embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. Therefore, the first semiconductor region 11, the fourth semiconductor region 14, the fifth semiconductor region 15, and the sixth semiconductor region are n-type semiconductor regions, and the second semiconductor region and the third semiconductor region are p-type. It is a semiconductor region.

この双方向サイリスタ１は、第１の主サイリスタ、第２の主サイリスタ及びゲート機構部（補助サイリスタ）を備えている。第１の主サイリスタは、第４の半導体領域１４、第２の半導体領域１２、第１の半導体領域１１及び第３の半導体領域１３の４つの半導体領域により構成される。第２の主サイリスタは、第２の半導体領域１２、第１の半導体領域１１、第３の半導体領域１３及び第５の半導体領域１５の４つの半導体領域により構成される。ゲート機構部は、第６の半導体領域１６、第２の半導体領域１２、第１の半導体領域１１、第３の半導体領域１３及び第５の半導体領域１５の５つの半導体領域により構成される。   The bidirectional thyristor 1 includes a first main thyristor, a second main thyristor, and a gate mechanism (auxiliary thyristor). The first main thyristor is configured by four semiconductor regions of a fourth semiconductor region 14, a second semiconductor region 12, a first semiconductor region 11, and a third semiconductor region 13. The second main thyristor is composed of four semiconductor regions: a second semiconductor region 12, a first semiconductor region 11, a third semiconductor region 13, and a fifth semiconductor region 15. The gate mechanism section includes five semiconductor regions, that is, a sixth semiconductor region 16, a second semiconductor region 12, a first semiconductor region 11, a third semiconductor region 13, and a fifth semiconductor region 15.

第１の実施の形態において、第１の半導体領域１１は、ｎ型コレクタ領域であり、ｎ型シリコン単結晶基板の不純物密度をそのまま利用して形成される。この第１の半導体領域１１は、例えば７．２×１０13atoms／cm3−１．４×１０13atoms／cm3の不純物密度に設定され、１００μm−１９０μmの厚さを有する。 In the first embodiment, the first semiconductor region 11 is an n-type collector region and is formed using the impurity density of the n-type silicon single crystal substrate as it is. The first semiconductor region 11 is set to an impurity density of, for example, 7.2 × 10 13 atoms / cm 3 −1.4 × 10 13 atoms / cm 3 and has a thickness of 100 μm to 190 μm.

第２の半導体領域１２は、表面ｐ型ベース領域であり、第１の半導体領域１１の一方の表面１０Ａからｐ型不純物をイオン注入法又は拡散法により導入し活性化することにより形成される。この第２の半導体領域１２は例えば５．０×１０16atoms／cm3−３．０×１０18atoms／cm3の不純物密度に設定される。第２の半導体領域１２の一方の表面１０Ａから第１の半導体領域１１までの接合深さは３５μm−６５μmに設定される。 The second semiconductor region 12 is a surface p-type base region, and is formed by introducing a p-type impurity from one surface 10A of the first semiconductor region 11 by an ion implantation method or a diffusion method and activating it. The second semiconductor region 12 is set to an impurity density of, for example, 5.0 × 10 16 atoms / cm 3 −3.0 × 10 18 atoms / cm 3 . The junction depth from one surface 10A of the second semiconductor region 12 to the first semiconductor region 11 is set to 35 μm-65 μm.

第３の半導体領域１３は、裏面ｐ型ベース領域であり、第１の半導体領域１１の他方の表面１０Ｂからｐ型不純物をイオン注入法又は拡散法により導入し活性化することにより形成される。この第３の半導体領域１３は例えば５．０×１０16atoms／cm3−３．０×１０18atoms／cm3の不純物密度に設定される。第３の半導体領域１３の他方の表面１０Ｂから第１の半導体領域１１までの接合深さは３５μm−６５μmに設定される。 The third semiconductor region 13 is a back surface p-type base region, and is formed by introducing and activating a p-type impurity from the other surface 10B of the first semiconductor region 11 by an ion implantation method or a diffusion method. The third semiconductor region 13 is set to an impurity density of, for example, 5.0 × 10 16 atoms / cm 3 −3.0 × 10 18 atoms / cm 3 . The junction depth from the other surface 10B of the third semiconductor region 13 to the first semiconductor region 11 is set to 35 μm-65 μm.

第４の半導体領域１４は、表面ｎ型エミッタ領域であり、第１の半導体領域１１の一方の表面１０Ａ（実際には第２の半導体領域１２の表面）からｎ型不純物をイオン注入法又は拡散法により導入し活性化することにより形成される。この第４の半導体領域１４は例えば１．０×１０19atoms／cm3−５．０×１０20atoms／cm3の不純物密度に設定される。第４の半導体領域１４の一方の表面１０Ａから第２の半導体領域１２までの接合深さは１５μm−３５μmに設定される。 The fourth semiconductor region 14 is a surface n-type emitter region, and an n-type impurity is ion-implanted or diffused from one surface 10A of the first semiconductor region 11 (actually the surface of the second semiconductor region 12). It is formed by introducing and activating by the method. The fourth semiconductor region 14 is set to an impurity density of, for example, 1.0 × 10 19 atoms / cm 3 -5.0 × 10 20 atoms / cm 3 . The junction depth from one surface 10A of the fourth semiconductor region 14 to the second semiconductor region 12 is set to 15 μm-35 μm.

第５の半導体領域１５は、裏面ｎ型エミッタ領域であり、第１の半導体領域１１の他方の表面１０Ｂ（実際には第３の半導体領域１３の表面）からｎ型不純物をイオン注入法又は拡散法により導入し活性化することにより形成される。この第５の半導体領域１５は例えば１．０×１０19atoms／cm3−５．０×１０20atoms／cm3の不純物密度に設定される。第５の半導体領域１５の他方の表面１０Ｂから第３の半導体領域１３までの接合深さは１５μm−４５μmに設定される。 The fifth semiconductor region 15 is a back surface n-type emitter region, and an n-type impurity is ion-implanted or diffused from the other surface 10B of the first semiconductor region 11 (actually the surface of the third semiconductor region 13). It is formed by introducing and activating by the method. The fifth semiconductor region 15 is set to an impurity density of, for example, 1.0 × 10 19 atoms / cm 3 −5.0 × 10 20 atoms / cm 3 . The junction depth from the other surface 10B of the fifth semiconductor region 15 to the third semiconductor region 13 is set to 15 μm-45 μm.

第６の半導体領域１６は、ｎ型ゲート領域であり、第１の半導体領域１１の一方の表面１０Ａ（実際には第２の半導体領域１２の表面）からｎ型不純物をイオン注入法又は拡散法により導入し活性化することにより形成される。この第６の半導体領域１６は例えば１．０×１０19atoms／cm3−５．０×１０20atoms／cm3の不純物密度に設定される。第６の半導体領域１６の一方の表面１０Ａから第２の半導体領域１２までの接合深さは１５μm−３５μmに設定される。第１の実施の形態においては、第４の半導体領域１４、第６の半導体領域１６のそれぞれは、同一の製造条件に設定されているので、同一製造工程により製造されている。 The sixth semiconductor region 16 is an n-type gate region, and an n-type impurity is ion-implanted or diffused from one surface 10A of the first semiconductor region 11 (actually the surface of the second semiconductor region 12). It is formed by introducing and activating. The sixth semiconductor region 16 is set to an impurity density of, for example, 1.0 × 10 19 atoms / cm 3 -5.0 × 10 20 atoms / cm 3 . The junction depth from one surface 10A of the sixth semiconductor region 16 to the second semiconductor region 12 is set to 15 μm-35 μm. In the first embodiment, each of the fourth semiconductor region 14 and the sixth semiconductor region 16 is set under the same manufacturing conditions, and is manufactured by the same manufacturing process.

第１の主電極２１は、半導体基板１０の一方の表面１０Ａ上に配設され、第２の半導体領域１２及び第４の半導体領域１４に電気的に接続される。この第１の主電極２１は例えばスパッタリング法又は蒸着法により成膜されたアルミニウムにより構成されている。また、第１の主電極２１には銅、ニッケル等の金属膜を使用することができる。   The first main electrode 21 is disposed on one surface 10 </ b> A of the semiconductor substrate 10 and is electrically connected to the second semiconductor region 12 and the fourth semiconductor region 14. The first main electrode 21 is made of, for example, aluminum formed by sputtering or vapor deposition. Further, a metal film such as copper or nickel can be used for the first main electrode 21.

ゲート電極２３は、半導体基板１０の一方の表面１０Ａ上に配設され、第２の半導体領域１２及び第６の半導体領域１６に電気的に接続される。第１の実施の形態において、ゲート電極２３は第１の主電極２１と同一導電性材料により形成されかつ同一導電層により構成されている。また、図１乃至図４においては図示していないが、実際にはゲート電極２３と第１の主電極２１との間には絶縁膜（パッシベーション膜）が配設されており、ゲート電極２３と第１の主電極２１との間は電気的に絶縁されている。   The gate electrode 23 is disposed on one surface 10 </ b> A of the semiconductor substrate 10 and is electrically connected to the second semiconductor region 12 and the sixth semiconductor region 16. In the first embodiment, the gate electrode 23 is formed of the same conductive material as that of the first main electrode 21 and is formed of the same conductive layer. Although not shown in FIGS. 1 to 4, an insulating film (passivation film) is actually provided between the gate electrode 23 and the first main electrode 21. The first main electrode 21 is electrically insulated.

第２の主電極２２は、半導体基板１０の他方の表面１０Ｂ上に配設され、第３の半導体領域１３及び第５の半導体領域１５に電気的に接続される。第２の主電極２２は前述の第１の主電極２１と同一導電性材料により構成されている。   The second main electrode 22 is disposed on the other surface 10B of the semiconductor substrate 10 and is electrically connected to the third semiconductor region 13 and the fifth semiconductor region 15. The second main electrode 22 is made of the same conductive material as the first main electrode 21 described above.

このような基本的構成を有する第１の実施の形態に係る双方向サイリスタ１は、均一幅（一定の幅寸法Ｗｇ）を有しかつ長手方向に終端がない閉じた平面形状を有する第６の半導体領域１６と、この第６の半導体領域１６の幅方向の一方の側（第６の半導体領域１６の外輪）に隣り合ってゲート電極２３と第２の半導体領域１２とを電気的に接続する第１の接続部３１と、第６の半導体領域１６の幅方向の一方の側において、第１の接続部３１から第６の半導体領域１６の長手方向の全周に渡って均一距離で離間して配設され、均一幅（一定の幅寸法Ｗｅ）を有しかつ長手方向に終端がない閉じた平面形状を有する第４の半導体領域１４と、この第４の半導体領域１４の幅方向の第１の接続部３１とは反対側の一方の側（第４の半導体領域の外輪）に隣り合って第１の主電極２１と第２の半導体領域１２とを電気的に接続する第２の接続部３２と、第６の半導体領域１６の幅方向の一方の側と反対側の他方の側（第６の半導体領域１６の内輪）において、第６の半導体領域１６からこの第６の半導体領域１６の長手方向の全周に渡って均一距離で離間して配設され、均一幅（一定の幅寸法Ｗｂ）を有しかつ長手方向に終端がない閉じた平面形状を有し、第１の主電極２１と第２の半導体領域１２とを電気的に接続する第３の接続部３３と備えている。ここで、第１の接続部３１と第２の接続部３２との間の離間距離Ａと、第１の接続部３１と第３の接続部３３との間の離間距離Ｂとは等しい事が好ましい。   The bi-directional thyristor 1 according to the first embodiment having such a basic configuration has a uniform planar shape (a constant width dimension Wg) and a closed planar shape having no end in the longitudinal direction. The gate electrode 23 and the second semiconductor region 12 are electrically connected adjacent to the semiconductor region 16 and one side in the width direction of the sixth semiconductor region 16 (outer ring of the sixth semiconductor region 16). On the one side in the width direction of the first connection portion 31 and the sixth semiconductor region 16, the first connection portion 31 is separated from the first connection portion 31 by a uniform distance over the entire circumference in the longitudinal direction of the sixth semiconductor region 16. A fourth semiconductor region 14 having a uniform planar shape (constant width dimension We) and having a closed planar shape with no end in the longitudinal direction; and a fourth semiconductor region 14 in the width direction of the fourth semiconductor region 14 1 side opposite to the connection portion 31 of the first semiconductor region (the fourth semiconductor region A second connection portion 32 that is adjacent to the ring and electrically connects the first main electrode 21 and the second semiconductor region 12, and is opposite to one side in the width direction of the sixth semiconductor region 16. On the other side (inner ring of the sixth semiconductor region 16), the sixth semiconductor region 16 is disposed at a uniform distance from the sixth semiconductor region 16 over the entire circumference in the longitudinal direction of the sixth semiconductor region 16. A third connection having a width (a constant width dimension Wb) and a closed planar shape having no end in the longitudinal direction, and electrically connecting the first main electrode 21 and the second semiconductor region 12 And 33. Here, the separation distance A between the first connection part 31 and the second connection part 32 and the separation distance B between the first connection part 31 and the third connection part 33 may be equal. preferable.

第１の実施の形態に係る双方向サイリスタ１においては、半導体基板１０の一方の表面１０Ａの面法線の方向から見て（平面的に見て）、第３の接続部３３の平面形状は一方の表面１０Ａの中心点Ｐを中心とする真円形状により構成されている。そして、第６の半導体領域１６、第１の接続部３１、第４の半導体領域１４及び第２の接続部３２の各々の平面形状は、第３の接続部３３（中心点Ｐ）を中心とし、順次半径が大きくなる同心のリング形状により構成されている。換言すれば、第１の主サイリスタは、第６の半導体領域１６のリング形状の外側に配設されている。   In the bidirectional thyristor 1 according to the first embodiment, when viewed from the direction of the surface normal of the one surface 10A of the semiconductor substrate 10 (as viewed in plan), the planar shape of the third connection portion 33 is It is constituted by a perfect circle shape centering on the center point P of one surface 10A. The planar shape of each of the sixth semiconductor region 16, the first connection portion 31, the fourth semiconductor region 14, and the second connection portion 32 is centered on the third connection portion 33 (center point P). These are configured by concentric ring shapes in which the radius increases sequentially. In other words, the first main thyristor is disposed outside the ring shape of the sixth semiconductor region 16.

また、第１の実施の形態の特徴に係る双方向サイリスタ１においては、第４の半導体領域１４及び第５の半導体領域１５のそれぞれの平面形状は、第６の半導体領域１６の平面形状の中心点Ｐと同心となるリング形状により構成されている。換言すれば、第４の半導体領域１４の一方の側（外輪）及び他方の側（内輪）並びに第５の半導体領域１５の一方の側（外輪）及び他方の側（内輪）の平面形状はいずれも第６の半導体領域１６の平面形状と同心となるリング形状により構成されている。   Further, in the bidirectional thyristor 1 according to the feature of the first embodiment, the planar shape of each of the fourth semiconductor region 14 and the fifth semiconductor region 15 is the center of the planar shape of the sixth semiconductor region 16. The ring is concentric with the point P. In other words, what is the planar shape of one side (outer ring) and the other side (inner ring) of the fourth semiconductor region 14 and one side (outer ring) and the other side (inner ring) of the fifth semiconductor region 15? Is also formed of a ring shape that is concentric with the planar shape of the sixth semiconductor region 16.

第５の半導体領域１５の一方の側は、半導体基板１０の一方の表面１０Ａの面法線方向から見て第６の半導体領域１６と重複する領域内（第６の半導体領域１６の内輪と外輪との間）に配設されている。第６の半導体領域１６の他方の側（内輪）と第５の半導体領域１５の一方の側（外輪）との間は重複部４０の幅Ｃに設定されている。すなわち、第２の半導体領域１２、第１の半導体領域１１、第３の半導体領域１３及び第５の半導体領域１５を有する第２の主サイリスタは第６の半導体領域１６から第３の接続部３３側に配設されている。換言すれば、第２の主サイリスタは、第６の半導体領域１６のリング形状の内側に配設されている。   One side of the fifth semiconductor region 15 is located in a region overlapping with the sixth semiconductor region 16 when viewed from the surface normal direction of the one surface 10A of the semiconductor substrate 10 (inner and outer rings of the sixth semiconductor region 16). Between the two). A width C of the overlapping portion 40 is set between the other side (inner ring) of the sixth semiconductor region 16 and one side (outer ring) of the fifth semiconductor region 15. That is, the second main thyristor having the second semiconductor region 12, the first semiconductor region 11, the third semiconductor region 13, and the fifth semiconductor region 15 is connected from the sixth semiconductor region 16 to the third connection portion 33. It is arranged on the side. In other words, the second main thyristor is disposed inside the ring shape of the sixth semiconductor region 16.

［双方向サイリスタの動作及び作用効果］
次に、前述の第１の実施の形態に係る双方向サイリスタ１の動作及び作用効果について図５乃至図８を用いて説明する。 [Operation and effects of bidirectional thyristor]
Next, operations and effects of the bidirectional thyristor 1 according to the first embodiment will be described with reference to FIGS.

（１）第１のモード
図５に示すように、第１のモード（モード１）は、第１の主電極（Ｔ１）２１を基準にして、第２の主電極（Ｔ２）２２に正電位を印加し、ゲート電極（Ｇ）２３に正電位を印加し、ターンオン動作を実行する。ここで、電子Ｅの流れは細い線幅の破線により示し、正孔Ｈ及びゲートトリガ電流ＩGTの流れは細い線幅の実線により示す。また、半導体基板１０の他方の表面１０Ｂから一方の表面１０Ａに向かう第１の主電流Ｉ1及び逆に一方の表面１０Ａから他方の表面１０Ｂに向かう第２の主電流Ｉ2の流れは太い線幅の実線により示す。この表記方法は第１のモードに限らず第２のモード乃至第４のモードにおいても同様である。 (1) First Mode As shown in FIG. 5, in the first mode (mode 1), a positive potential is applied to the second main electrode (T2) 22 with respect to the first main electrode (T1) 21. Is applied, a positive potential is applied to the gate electrode (G) 23, and a turn-on operation is performed. Here, the flow of the electrons E is indicated by a thin broken line, and the flow of the holes H and the gate trigger current I GT is indicated by a thin solid line. The flow of the first main current I 1 from the other surface 10B of the semiconductor substrate 10 toward the one surface 10A and conversely the flow of the second main current I 2 from the one surface 10A toward the other surface 10B is a thick line. Indicated by the solid line of width. This notation is the same not only in the first mode but also in the second to fourth modes.

第１のモードにおいては、次の動作によって第１の主サイリスタがオン状態になる。まず、ゲート電極２３から第１の接続部３１、第２の半導体領域１２、第２の接続部３２のそれぞれを通して第１の主電極２１にゲートトリガ電流ＩGTが流れる。これにより、第２の半導体領域１２に電圧降下が生じ、第２の半導体領域１２と第４の半導体領域１４との間のｐｎ接合が順バイアス状態となり、第４の半導体領域１４から第２の半導体領域１２に電子Ｅが注入される。第２の半導体領域１２に注入された電子Ｅの一部は第１の半導体領域１１に注入され、この第１の半導体領域１１に電子Ｅが蓄積される。この結果、第３の半導体領域１３から第１の半導体領域１１に正孔Ｈの注入が生じる。第１の半導体領域１１に注入された正孔Ｈの一部は第２の半導体領域１２に注入され、第４の半導体領域１４から第２の半導体領域１２への電子Ｅの注入が増幅される。そして、最終的に、第２の主電極２２、第３の半導体領域１３、第１の半導体領域１１、第２の半導体領域１２、第４の半導体領域１４及び第１の主電極２１の電流経路、つまり第１の主サイリスタにおいて、第１の方向の主電流Ｉ1が流れる。 In the first mode, the first main thyristor is turned on by the following operation. First, the gate trigger current I GT flows from the gate electrode 23 to the first main electrode 21 through each of the first connection portion 31, the second semiconductor region 12, and the second connection portion 32. As a result, a voltage drop occurs in the second semiconductor region 12, the pn junction between the second semiconductor region 12 and the fourth semiconductor region 14 becomes a forward bias state, and the second semiconductor region 14 Electrons E are injected into the semiconductor region 12. A part of the electrons E injected into the second semiconductor region 12 is injected into the first semiconductor region 11, and the electrons E are accumulated in the first semiconductor region 11. As a result, holes H are injected from the third semiconductor region 13 into the first semiconductor region 11. A part of the holes H injected into the first semiconductor region 11 is injected into the second semiconductor region 12, and the injection of electrons E from the fourth semiconductor region 14 into the second semiconductor region 12 is amplified. . Finally, current paths of the second main electrode 22, the third semiconductor region 13, the first semiconductor region 11, the second semiconductor region 12, the fourth semiconductor region 14, and the first main electrode 21. That is, the main current I 1 in the first direction flows in the first main thyristor.

この一連の第１の主サイリスタのトリガ機構において、第１の接続部３１、第４の半導体領域１４及び第３の接続部３２のそれぞれが同一の中心点Ｐに対するリング形状により構成されているので、第１の接続部３１と第３の接続部３３との間の電位分布及びゲートトリガ電流ＩGTの分布はリング形状の円周上において均一になる。従って、このゲートトリガ電流ＩGTにより第４の半導体領域１４から第２の半導体領域１２への電子Ｅの注入量、第３の半導体領域１３から第１の半導体領域１１への正孔Ｈの注入量は均一化され、中心点Ｐを中心として同心円状に均一なトリガ動作が行われる。 In the trigger mechanism of the series of first main thyristors, each of the first connection portion 31, the fourth semiconductor region 14, and the third connection portion 32 is configured by a ring shape with respect to the same center point P. The potential distribution between the first connection portion 31 and the third connection portion 33 and the distribution of the gate trigger current I GT are uniform on the circumference of the ring shape. Therefore, the injection amount of electrons E from the fourth semiconductor region 14 to the second semiconductor region 12 and the injection of holes H from the third semiconductor region 13 to the first semiconductor region 11 by this gate trigger current I GT . The amount is made uniform, and a uniform trigger operation is performed concentrically around the center point P.

また、第１のモードにおいては、第１の接続部３１から第２の接続部３２に、内側の小さなリングから外側の大きなリングに向かってゲートトリガ電流ＩGTが流れるので、ターンオン動作の初期の動作領域つまり第４の半導体領域１４の周辺長（エミッタ領域の周辺長）を長くし、第１の主サイリスタの初期通電領域を広げることで、第１の主サイリスタの通電初期に流れる電流密度を低減する事ができる。 In the first mode, the gate trigger current I GT flows from the first small connection ring to the second large connection ring 32 from the first connection portion 31 to the second connection portion 32. By increasing the operating region, that is, the peripheral length of the fourth semiconductor region 14 (peripheral length of the emitter region) and widening the initial energization region of the first main thyristor, the current density flowing in the initial energization of the first main thyristor can be reduced. Can be reduced.

（２）第２のモード
図６に示すように、第２のモード（モード２）は、第１の主電極（Ｔ１）２１を基準にして、第２の主電極（Ｔ２）２２に正電位を印加し、ゲート電極（Ｇ）２３に負電位を印加し、ターンオンを実行する。第２のモードにおいては、次の動作によって第１の主サイリスタがオン状態になる。 (2) Second Mode As shown in FIG. 6, in the second mode (mode 2), a positive potential is applied to the second main electrode (T2) 22 with respect to the first main electrode (T1) 21. Is applied, a negative potential is applied to the gate electrode (G) 23, and turn-on is executed. In the second mode, the first main thyristor is turned on by the following operation.

まず、第１の主電極２１から第３の接続部３３、第２の半導体領域１２、第１の接続部３１のそれぞれを通してゲート電極２３にゲートトリガ電流ＩGTが流れる。これにより、第２の半導体領域１２に電圧降下が生じ、第２の半導体領域１２と第６の半導体領域１６との間のｐｎ接合が順バイアス状態となり、第６の半導体領域１６から第２の半導体領域１２に電子Ｅが注入される。第２の半導体領域１２に注入された電子Ｅの一部は第１の半導体領域１１に注入され、この第１の半導体領域１１に電子Ｅが蓄積される。この結果、第３の半導体領域１３から第１の半導体領域１１に正孔Ｈの注入が生じる。第１の半導体領域１１に注入された正孔Ｈの一部は第２の半導体領域１２に注入され、第６の半導体領域１６から第２の半導体領域１２への電子Ｅの注入が増幅される。そして、最終的に、第６の半導体領域１６、第２の半導体領域１２、第１の半導体領域１１及び第３の半導体領域１３の電流経路、つまりゲート機構部分（補助サイリスタ）が導通状態になる。 First, the gate trigger current I GT flows from the first main electrode 21 to the gate electrode 23 through the third connection portion 33, the second semiconductor region 12, and the first connection portion 31. As a result, a voltage drop occurs in the second semiconductor region 12, the pn junction between the second semiconductor region 12 and the sixth semiconductor region 16 is in a forward bias state, and the second semiconductor region 12 has a second bias state. Electrons E are injected into the semiconductor region 12. A part of the electrons E injected into the second semiconductor region 12 is injected into the first semiconductor region 11, and the electrons E are accumulated in the first semiconductor region 11. As a result, holes H are injected from the third semiconductor region 13 into the first semiconductor region 11. A part of the holes H injected into the first semiconductor region 11 is injected into the second semiconductor region 12, and the injection of electrons E from the sixth semiconductor region 16 into the second semiconductor region 12 is amplified. . Finally, the current paths of the sixth semiconductor region 16, the second semiconductor region 12, the first semiconductor region 11, and the third semiconductor region 13, that is, the gate mechanism portion (auxiliary thyristor) are in a conductive state. .

このゲート機構部分が導通状態になると、このゲート機構部分の電子Ｅ及び正孔Ｈの注入動作がゲート機構部分に近接している第１の主サイリスタに転移し若しくは波及し、この第１の主サイリスタのターンオン動作が開始される。第１のモードと同様に、第１の主サイリスタにおいては、第２の主電極２２から第１の主電極２１に、第３の半導体領域１３、第１の半導体領域１１、第２の半導体領域１２、第４の半導体領域１４のそれぞれを通して第１の方向の主電流Ｉ1が流れる。 When the gate mechanism portion becomes conductive, the injection operation of electrons E and holes H in the gate mechanism portion is transferred to or spreads to the first main thyristor adjacent to the gate mechanism portion. The thyristor turn-on operation is started. Similar to the first mode, in the first main thyristor, the third semiconductor region 13, the first semiconductor region 11, and the second semiconductor region are transferred from the second main electrode 22 to the first main electrode 21. 12, the main current I 1 in the first direction flows through each of the fourth semiconductor regions 14.

この一連のゲート機構部分並びに第１の主サイリスタのトリガ機構において、第６の半導体領域１６、第１の接続部３１、及び第3の接続部３３のそれぞれが同一の中心点Ｐに対するリング形状により構成されているので、第１の接続部３１と第３の接続部３３との間の電位分布及びゲートトリガ電流ＩGTの電流分布はリング形状の円周上において均一になる。従って、このゲートトリガ電流ＩGTにより第６の半導体領域１６から第２の半導体領域１２への電子Ｅの注入量、第３の半導体領域１３から第１の半導体領域１１への正孔Ｈの注入量は均一化され、中心点Ｐを中心として同心円状に均一なトリガ動作が行われる。 In this series of gate mechanism portions and the trigger mechanism of the first main thyristor, each of the sixth semiconductor region 16, the first connection portion 31, and the third connection portion 33 has a ring shape with respect to the same center point P. Since it is configured, the potential distribution between the first connection portion 31 and the third connection portion 33 and the current distribution of the gate trigger current I GT are uniform on the ring-shaped circumference. Therefore, the injection amount of electrons E from the sixth semiconductor region 16 to the second semiconductor region 12 and the injection of holes H from the third semiconductor region 13 to the first semiconductor region 11 by this gate trigger current I GT . The amount is made uniform, and a uniform trigger operation is performed concentrically around the center point P.

また、第２のモードにおいては、第３の接続部３３から第１の接続部３１に、内側の小さなリングから外側の大きなリングに向かってゲートトリガ電流ＩGTが流れるので、ターンオン動作の初期の動作領域つまり第６の半導体領域１６の周辺長（エミッタ領域の周辺長）を長くし、第１の主サイリスタの初期通電領域を広げることで、第１の主サイリスタの通電初期に流れる電流密度を低減する事ができる。 Further, in the second mode, the gate trigger current I GT flows from the third connection portion 33 to the first connection portion 31 from the inner small ring to the outer large ring, so that the initial turn-on operation is performed. By increasing the peripheral length of the operating region, that is, the sixth semiconductor region 16 (peripheral length of the emitter region) and widening the initial energization region of the first main thyristor, the current density flowing in the initial energization of the first main thyristor can be reduced. Can be reduced.

（３）第３のモード
図７に示すように、第３のモード（モード３）は、第１の主電極（Ｔ１）２１を基準にして第２の主電極（Ｔ２）２２が負電位のときに、ゲート電極（Ｇ）２３を負電位にし、ターンオンを実行する。第３のモードにおいては、次の動作によって第２の主サイリスタがオン状態になる。 (3) Third Mode As shown in FIG. 7, in the third mode (mode 3), the second main electrode (T2) 22 is negative with respect to the first main electrode (T1) 21. Sometimes, the gate electrode (G) 23 is set to a negative potential and turn-on is performed. In the third mode, the second main thyristor is turned on by the following operation.

まず、第１の主電極２１から第３の接続部３３、第２の半導体領域１２、第１の接続部３１のそれぞれを通してゲート電極２３にゲートトリガ電流ＩGTが流れる。これにより、第２の半導体領域１２に電圧降下が生じ、第２の半導体領域１２と第６の半導体領域１６との間のｐｎ接合が順バイアス状態となり、第６の半導体領域１６から第２の半導体領域１２に電子Ｅが注入される。第２の半導体領域１２に注入された電子Ｅの一部は第１の半導体領域１１に注入され、この第１の半導体領域１１に電子Ｅが蓄積される。この結果、第１の半導体領域１１と第２の半導体領域１２との間のｐｎ接合の順バイアス状態が強められ、第２の半導体領域１２から第１の半導体領域１１に正孔Ｈの注入が生じる。この正孔Ｈは、第１の半導体領域１１、第３の半導体領域１３のそれぞれを経て第２の主電極２２に流れる。この正孔Ｈの流れにより第３の半導体領域１３に電圧降下が生じ、第３の半導体領域１３と第５の半導体領域１５との間のｐｎ接合が順バイアス状態になり、第５の半導体領域１５から第３の半導体領域１３に電子Ｅが注入される。この電子Ｅの一部は第１の半導体領域１１に注入される。これにより、ゲート機構部分（補助サイリスタ）が導通状態になる。 First, the gate trigger current I GT flows from the first main electrode 21 to the gate electrode 23 through the third connection portion 33, the second semiconductor region 12, and the first connection portion 31. As a result, a voltage drop occurs in the second semiconductor region 12, the pn junction between the second semiconductor region 12 and the sixth semiconductor region 16 is in a forward bias state, and the second semiconductor region 12 has a second bias state. Electrons E are injected into the semiconductor region 12. A part of the electrons E injected into the second semiconductor region 12 is injected into the first semiconductor region 11, and the electrons E are accumulated in the first semiconductor region 11. As a result, the forward bias state of the pn junction between the first semiconductor region 11 and the second semiconductor region 12 is strengthened, and holes H are injected from the second semiconductor region 12 into the first semiconductor region 11. Arise. The holes H flow to the second main electrode 22 through each of the first semiconductor region 11 and the third semiconductor region 13. The flow of the holes H causes a voltage drop in the third semiconductor region 13, and the pn junction between the third semiconductor region 13 and the fifth semiconductor region 15 becomes a forward bias state, and the fifth semiconductor region Electrons E are injected from 15 into the third semiconductor region 13. A part of the electrons E is injected into the first semiconductor region 11. As a result, the gate mechanism portion (auxiliary thyristor) becomes conductive.

このゲート機構部分が導通状態になると、このゲート機構部分の電子Ｅ及び正孔Ｈの注入動作がゲート機構部分に近接している第２の主サイリスタに転移し若しくは波及し、この第２の主サイリスタのターンオン動作が開始される。すなわち、第２の主サイリスタにおいては、第１の主電極２１から第２の主電極２２に、第２の半導体領域１２、第１の半導体領域１１、第３の半導体領域１３、第５の半導体領域１５のそれぞれを通して第２の方向の主電流Ｉ2が流れる。 When the gate mechanism portion becomes conductive, the injection operation of electrons E and holes H in the gate mechanism portion is transferred to or spreads to the second main thyristor adjacent to the gate mechanism portion. The thyristor turn-on operation is started. That is, in the second main thyristor, the second semiconductor region 12, the first semiconductor region 11, the third semiconductor region 13, and the fifth semiconductor are transferred from the first main electrode 21 to the second main electrode 22. A main current I 2 in the second direction flows through each of the regions 15.

この一連のゲート機構部分並びに第２の主サイリスタのトリガ機構において、第６の半導体領域１６、第１の接続部３１、第３の接続部３３、第５の半導体領域１５と第６の半導体領域１６との重複部４０のそれぞれが同一の中心点Ｐに対するリング形状により構成されているので、第１の接続部３１と第３の接続部３３との間の電位分布及びゲートトリガ電流ＩGTの分布はリング形状の円周上において均一になる。従って、このゲートトリガ電流ＩGTにより第６の半導体領域１６から第２の半導体領域１２への電子Ｅの注入量、第５の半導体領域１５から第１の半導体領域１１への電子Ｅの注入量は均一化され、中心点Ｐを中心として同心円状に均一なトリガ動作が行われる。 In this series of gate mechanism portion and trigger mechanism of the second main thyristor, the sixth semiconductor region 16, the first connection portion 31, the third connection portion 33, the fifth semiconductor region 15 and the sixth semiconductor region Since each of the overlapping portions 40 with 16 is formed in a ring shape with respect to the same center point P, the potential distribution between the first connecting portion 31 and the third connecting portion 33 and the gate trigger current I GT The distribution is uniform on the circumference of the ring shape. Therefore, the injection amount of electrons E from the sixth semiconductor region 16 to the second semiconductor region 12 and the injection amount of electrons E from the fifth semiconductor region 15 to the first semiconductor region 11 by the gate trigger current I GT . Are uniformed, and a uniform trigger operation is performed concentrically around the center point P.

また、第３のモードにおいては、第３の接続部３３から第１の接続部３１に、内側の小さなリングから外側の大きなリングに向かってゲートトリガ電流ＩGTが流れるので、ターンオン動作の初期の動作領域つまり第６の半導体領域１６の周辺長（エミッタ領域の周辺長）を長くし、第２の主サイリスタの初期通電領域を広げることで、第２の主サイリスタの通電初期に流れる電流密度を低減する事ができる。 In the third mode, the gate trigger current I GT flows from the third connection portion 33 to the first connection portion 31 from the inner small ring to the outer large ring. By increasing the peripheral length of the operating region, that is, the sixth semiconductor region 16 (peripheral length of the emitter region) and widening the initial energization region of the second main thyristor, the current density flowing in the initial energization of the second main thyristor can be reduced. Can be reduced.

また、従来の双方向サイリスタの場合、第3のモードは第1のモードよりも低感度となってしまうが、第３の接続部３３が第６の半導体領域１６よりも内側に形成されるため、ゲートトリガ電流ＩGTの電流密度を高める事ができる。従って、第３のモードの感度を高める事ができるとともに、第１のモードと第３のモードとの感度の差を改善する事ができる。 Further, in the case of the conventional bidirectional thyristor, the third mode is less sensitive than the first mode, but the third connection portion 33 is formed inside the sixth semiconductor region 16. The current density of the gate trigger current I GT can be increased. Therefore, the sensitivity of the third mode can be increased, and the difference in sensitivity between the first mode and the third mode can be improved.

（４）第４のモード
図８に示すように、第４のモード（モード４）は、第１の主電極（Ｔ１）２１を基準にして、第２の主電極（Ｔ２）２２に負電位を印加し、ゲート電極（Ｇ）２３に正電位を印加し、ターンオン動作を実行する。第４のモードにおいては、次の動作によって第２の主サイリスタがオン状態になる。 (4) Fourth Mode As shown in FIG. 8, in the fourth mode (mode 4), the second main electrode (T2) 22 has a negative potential based on the first main electrode (T1) 21. Is applied, a positive potential is applied to the gate electrode (G) 23, and a turn-on operation is performed. In the fourth mode, the second main thyristor is turned on by the following operation.

まず、ゲート電極２３から第１の接続部３１、第２の半導体領域１２、第２の接続部３２のそれぞれを通して第１の主電極２１にゲートトリガ電流ＩGTが流れる。これにより、第２の半導体領域１２に電圧降下が生じ、第２の半導体領域１２と第４の半導体領域１４との間のｐｎ接合が順バイアス状態となり、第４の半導体領域１４から第２の半導体領域１２に電子Ｅが注入される。第２の半導体領域１２に注入された電子Ｅの一部は第１の半導体領域１１に注入され、この第１の半導体領域１１に電子Ｅが蓄積される。この結果、第１の半導体領域１１と第２の半導体領域１２との間のｐｎ接合の順バイアスが強められ、第２の半導体領域１２から第１の半導体領域１１に正孔Ｈの注入が生じる。この正孔Ｈは、第１の半導体領域１１、第３の半導体領域１３のそれぞれを経て第２の主電極２２に流れる。これにより、第３の半導体領域１３に電圧降下が生じ、第３の半導体領域１３と第５の半導体領域１５との間のｐｎ接合が順バイアス状態になり、第５の半導体領域１５から第３の半導体領域１３に電子Ｅが注入される。この電子Ｅは第１の半導体領域１１に注入される。 First, the gate trigger current I GT flows from the gate electrode 23 to the first main electrode 21 through each of the first connection portion 31, the second semiconductor region 12, and the second connection portion 32. As a result, a voltage drop occurs in the second semiconductor region 12, the pn junction between the second semiconductor region 12 and the fourth semiconductor region 14 becomes a forward bias state, and the second semiconductor region 14 Electrons E are injected into the semiconductor region 12. A part of the electrons E injected into the second semiconductor region 12 is injected into the first semiconductor region 11, and the electrons E are accumulated in the first semiconductor region 11. As a result, the forward bias of the pn junction between the first semiconductor region 11 and the second semiconductor region 12 is strengthened, and holes H are injected from the second semiconductor region 12 into the first semiconductor region 11. . The holes H flow to the second main electrode 22 through each of the first semiconductor region 11 and the third semiconductor region 13. As a result, a voltage drop occurs in the third semiconductor region 13, the pn junction between the third semiconductor region 13 and the fifth semiconductor region 15 is in a forward bias state, and the third semiconductor region 15 to the third semiconductor region 13 Electrons E are injected into the semiconductor region 13. The electrons E are injected into the first semiconductor region 11.

この結果、第３のモードと同様に、第２の主サイリスタのターンオン動作が開始される。すなわち、第２の主サイリスタにおいては、第１の主電極２１から第２の主電極２２に、第２の半導体領域１２、第１の半導体領域１１、第３の半導体領域１３、第５の半導体領域１５のそれぞれを通して第２の方向の主電流Ｉ2が流れる。 As a result, similarly to the third mode, the turn-on operation of the second main thyristor is started. That is, in the second main thyristor, the second semiconductor region 12, the first semiconductor region 11, the third semiconductor region 13, and the fifth semiconductor are transferred from the first main electrode 21 to the second main electrode 22. A main current I 2 in the second direction flows through each of the regions 15.

この一連のゲート機構部分並びに第２の主サイリスタのトリガ機構において、第１の接続部３１、第２の接続部３２、第４の半導体領域１４、第5の半導体領域１５と第６の半導体領域１６との重複部４０のそれぞれが同一の中心点Ｐに対するリング形状により構成されているので、第１の接続部３１と第２の接続部３２との間の電位分布及びゲートトリガ電流ＩGTの電流分布はリング形状の円周上において均一になる。従って、このゲートトリガ電流ＩGTにより第４の半導体領域１４から第２の半導体領域１２への電子Ｅの注入量、第５の半導体領域１５から第１の半導体領域１１への電子Ｅの注入量は均一化され、中心点Ｐを中心として同心円状に均一なトリガ動作が行われる。 In this series of gate mechanism portions and the trigger mechanism of the second main thyristor, the first connection portion 31, the second connection portion 32, the fourth semiconductor region 14, the fifth semiconductor region 15, and the sixth semiconductor region. Since each of the overlapping portions 40 with 16 is formed in a ring shape with respect to the same center point P, the potential distribution between the first connection portion 31 and the second connection portion 32 and the gate trigger current I GT The current distribution is uniform on the circumference of the ring shape. Therefore, the injection amount of electrons E from the fourth semiconductor region 14 to the second semiconductor region 12 and the injection amount of electrons E from the fifth semiconductor region 15 to the first semiconductor region 11 by the gate trigger current I GT . Are uniformed, and a uniform trigger operation is performed concentrically around the center point P.

また、第４のモードにおいては、第１の接続部３１から第２の接続部３２に、内側の小さなリングから外側の大きなリングに向かってゲートトリガ電流ＩGTが流れるので、ターンオン動作の初期の動作領域つまり第４の半導体領域１４の周辺長（エミッタ領域の周辺長）を長くし、第２の主サイリスタの通電初期に流れる電流密度を低減することができる。 In the fourth mode, since the gate trigger current I GT flows from the first small connecting ring 31 to the second connecting ring 32 from the small inner ring to the large outer ring, the initial turn-on operation is performed. The operating region, that is, the peripheral length of the fourth semiconductor region 14 (peripheral length of the emitter region) can be increased, and the current density flowing in the initial energization of the second main thyristor can be reduced.

第１の実施の形態に係る双方向サイリスタ１においては、ゲート電極２３の一方の側に第１の主サイリスタ、ゲート電極２３の他方の側に第２の主サイリスタが配設されている。特に、第１の実施形態に係る双方向サイリスタ１において、第５の半導体領域５と第６の半導体領域６の重複部４０がゲート電極２３の一方の側にあり、第４の半導体領域が他方の側にある。このような構成により、２つの第１の主サイリスタと第２の主サイリスタとの間が空間的に分離されるので、第１の主サイリスタと第２の主サイリスタとの間の相互の影響による誤動作を防止することができ、転流時臨界電圧上昇率（ｄｖ／ｄｔ）ｃ耐量を向上することができる。   In the bidirectional thyristor 1 according to the first embodiment, a first main thyristor is disposed on one side of the gate electrode 23, and a second main thyristor is disposed on the other side of the gate electrode 23. In particular, in the bidirectional thyristor 1 according to the first embodiment, the overlapping portion 40 of the fifth semiconductor region 5 and the sixth semiconductor region 6 is on one side of the gate electrode 23, and the fourth semiconductor region is on the other side. On the side. With such a configuration, since the two first main thyristors and the second main thyristor are spatially separated, the mutual influence between the first main thyristor and the second main thyristor is caused. Malfunctions can be prevented, and the critical voltage increase rate (dv / dt) c tolerance during commutation can be improved.

このように第１の実施の形態に係る双方向サイリスタ１においては、第１及び第２の主サイリスタの初期通電領域を広げて第１及び第２の主サイリスタの通電初期に流れる電流密度を低減するとともに、転流時臨界電圧上昇率（ｄｖ／ｄｔ）ｃを改善することができる。   As described above, in the bidirectional thyristor 1 according to the first embodiment, the initial energization regions of the first and second main thyristors are expanded to reduce the current density flowing in the initial energization of the first and second main thyristors. In addition, the critical voltage increase rate (dv / dt) c during commutation can be improved.

（第２の実施の形態）
本発明の第２の実施の形態は、前述の第１の実施の形態に係る双方向サイリスタ１において、ゲート電極２３特に第１の接続部３１を中心として、第４の半導体領域１４及び第２の接続部３２と第３の接続部３３との配置位置を反転させた例を説明するものである。 (Second Embodiment)
The second embodiment of the present invention is the bidirectional thyristor 1 according to the first embodiment described above, in which the fourth semiconductor region 14 and the second semiconductor region 14 are arranged around the gate electrode 23, particularly the first connection portion 31. The example which reversed the arrangement position of the connection part 32 of this and the 3rd connection part 33 is demonstrated.

［双方向サイリスタのデバイス構造］
第２の実施の形態に係る双方向サイリスタ１の各部の符号は前述の第１の実施の形態に係る双方向サイリスタ１の基本構造と同じとする。すなわち、双方向サイリスタ１は、図９に示すように、半導体基板１０と、半導体基板１０の一方の表面１０Ａ（図９中、上側表面）上に配設された第１の主電極２１（Ｔ１）及びゲート電極２３（Ｇ）と、半導体基板１０の一方の表面１０Ａと反対の他方の表面１０Ｂ（図９中、下側裏面）上に配設された第２の主電極２２（Ｔ２）とを備えている。 [Device structure of bidirectional thyristor]
The reference numerals of the respective parts of the bidirectional thyristor 1 according to the second embodiment are the same as the basic structure of the bidirectional thyristor 1 according to the first embodiment. That is, as shown in FIG. 9, the bidirectional thyristor 1 includes a semiconductor substrate 10 and a first main electrode 21 (T1) disposed on one surface 10A (the upper surface in FIG. 9) of the semiconductor substrate 10. ) And the gate electrode 23 (G), and the second main electrode 22 (T2) disposed on the other surface 10B (the lower back surface in FIG. 9) opposite to the one surface 10A of the semiconductor substrate 10. It has.

半導体基板１０は、第１の導電型の第１の半導体領域１１と、第１の半導体領域１１の一方の表面１０Ａ側に隣接して配設された第１の導電型とは逆の第２の導電型の第２の半導体領域１２と、第１の半導体領域１１の他方の表面１０Ｂ側に隣接して配設された第２の導電型の第３の半導体領域１３と、第２の半導体領域１２の一方の表面１０Ａ側に配設された第１の導電型の第４の半導体領域１４と、第３の半導体領域１３の他方の表面１０Ｂ側に配設された第１の導電型の第５の半導体領域１５と、第２の半導体領域１２の一方の表面１０Ａ側に第４の半導体領域１４と離間して配設された第１の導電型の第６の半導体領域１６とを備えている。ここで、第１の実施の形態と同様に、第２の実施の形態において、第１の導電型はｎ型であり、第２の導電型はｐ型である。   The semiconductor substrate 10 includes a first conductivity type first semiconductor region 11 and a second conductivity type opposite to the first conductivity type disposed adjacent to one surface 10A side of the first semiconductor region 11. A second semiconductor region 12 of the second conductivity type, a third semiconductor region 13 of the second conductivity type disposed adjacent to the other surface 10B side of the first semiconductor region 11, and a second semiconductor The first conductivity type fourth semiconductor region 14 disposed on one surface 10A side of the region 12 and the first conductivity type disposed on the other surface 10B side of the third semiconductor region 13. A fifth semiconductor region 15 and a sixth semiconductor region 16 of the first conductivity type disposed on the one surface 10A side of the second semiconductor region 12 and spaced apart from the fourth semiconductor region 14 are provided. ing. Here, as in the first embodiment, in the second embodiment, the first conductivity type is n-type, and the second conductivity type is p-type.

このような基本的構成を有する第２の実施の形態に係る双方向サイリスタ１は、均一幅（一定の幅寸法Ｗｇ）を有しかつ長手方向に終端がない閉じた平面形状を有する第６の半導体領域１６と、この第６の半導体領域１６の幅方向の他方の側（第６の半導体領域１６の内輪）に隣り合ってゲート電極２３と第２の半導体領域１２とを電気的に接続する第１の接続部３１と、第６の半導体領域１６の幅方向の他方の側において、第１の接続部３１から第６の半導体領域１６の長手方向の全周に渡って均一距離で離間して配設され、均一幅（一定の幅寸法Ｗｅ）を有しかつ長手方向に終端がない閉じた平面形状を有する第４の半導体領域１４と、この第４の半導体領域１４の幅方向の第１の接続部３１とは反対側の他方の側（第４の半導体領域の内輪）に隣り合って第１の主電極２１と第２の半導体領域１２とを電気的に接続する第２の接続部３２と、第６の半導体領域１６の幅方向の他方の側と反対側の一方の側（第６の半導体領域１６の外輪）において、第６の半導体領域１６からこの第６の半導体領域１６の長手方向の全周に渡って均一距離で離間して配設され、均一幅（一定の幅寸法Ｗｂ）を有しかつ長手方向に終端がない閉じた平面形状を有し、第１の主電極２１と第２の半導体領域１２とを電気的に接続する第３の接続部３３と備えている。第１の接続部３１と第２の接続部３２との間の離間距離Ａと、第１の接続部３１と第３の接続部３３との間の離間距離Ｂとは等しい事が好ましい。   The bi-directional thyristor 1 according to the second embodiment having such a basic configuration has a uniform planar shape (constant width dimension Wg) and a closed planar shape having no end in the longitudinal direction. The gate electrode 23 and the second semiconductor region 12 are electrically connected adjacent to the semiconductor region 16 and the other side in the width direction of the sixth semiconductor region 16 (inner ring of the sixth semiconductor region 16). On the other side in the width direction of the first connection portion 31 and the sixth semiconductor region 16, the first connection portion 31 is separated from the first connection portion 31 by a uniform distance over the entire circumference in the longitudinal direction of the sixth semiconductor region 16. A fourth semiconductor region 14 having a uniform planar shape (constant width dimension We) and having a closed planar shape with no end in the longitudinal direction; and a fourth semiconductor region 14 in the width direction of the fourth semiconductor region 14 1 on the other side opposite to the connection portion 31 (the fourth semiconductor region). A second connection portion 32 that is adjacent to the ring) and electrically connects the first main electrode 21 and the second semiconductor region 12, and the other side in the width direction of the sixth semiconductor region 16. Is disposed at a uniform distance from the sixth semiconductor region 16 over the entire circumference in the longitudinal direction of the sixth semiconductor region 16 on one side (outer ring of the sixth semiconductor region 16). A third connection having a width (a constant width dimension Wb) and a closed planar shape having no end in the longitudinal direction, and electrically connecting the first main electrode 21 and the second semiconductor region 12 And 33. The separation distance A between the first connection portion 31 and the second connection portion 32 and the separation distance B between the first connection portion 31 and the third connection portion 33 are preferably equal.

すなわち、双方向サイリスタ１は、第２の接続部３２、第４の半導体領域１４、第１の接続部３１、第６の半導体領域１６及び第３の接続部３３のそれぞれの平面形状が、第２の接続部３２を中心とする（中心点Ｐを中心とする）同心のリング形状により構成されている。第１の実施の実施の形態に係る双方向サイリスタ１は、中心点Ｐからその周囲に向かって、第３の接続部３３、第６の半導体領域１６、第１の接続部３１、第４の半導体領域１４、第２の接続部３２のそれぞれをレイアウトしていることに対して、第２の実施の形態に係る双方向サイリスタ１は反転されたレイアウトを有する。それ以外の基本構造は、第１の実施の形態に係る双方向サイリスタ１と第２の実施の形態に係る双方向サイリスタ１との間では同一である。また、双方向サイリスタ１のターンオン動作は前述の第１のモード乃至第４のモードにおいて同一であるので、ここでの説明は省略する。   That is, the bidirectional thyristor 1 has the planar shapes of the second connection part 32, the fourth semiconductor region 14, the first connection part 31, the sixth semiconductor region 16, and the third connection part 33, It is comprised by the concentric ring shape centering on the connection part 32 of 2 (centering on the center point P). The bidirectional thyristor 1 according to the first embodiment includes a third connecting portion 33, a sixth semiconductor region 16, a first connecting portion 31, and a fourth connecting portion from the center point P toward the periphery thereof. Whereas each of the semiconductor region 14 and the second connection portion 32 is laid out, the bidirectional thyristor 1 according to the second embodiment has an inverted layout. Other basic structures are the same between the bidirectional thyristor 1 according to the first embodiment and the bidirectional thyristor 1 according to the second embodiment. Further, since the turn-on operation of the bidirectional thyristor 1 is the same in the first to fourth modes, the description thereof is omitted here.

［双方向サイリスタの作用効果］
以上説明したように、第２の形態に係る双方向サイリスタ１においては、前述の第１の実施の形態に係る双方向サイリスタ１により得られる作用効果と同様の作用効果を奏することができる。 [Effects of bidirectional thyristor]
As described above, the bidirectional thyristor 1 according to the second embodiment can achieve the same operational effects as the operational effects obtained by the bidirectional thyristor 1 according to the first embodiment described above.

（第３の実施の形態）
本発明の第３の実施の形態は、前述の第１の実施の形態並びに第２の実施の形態に係る双方向サイリスタ１において、各々の半導体領域や各々の電極の平面形状を変えた例を説明するものである。 (Third embodiment)
The third embodiment of the present invention is an example in which the planar shape of each semiconductor region and each electrode is changed in the bidirectional thyristor 1 according to the first embodiment and the second embodiment described above. Explain.

［第１の変形例］
図１０（Ａ）及び図１０（Ｂ）に示す第３の実施の形態の第１の変形例に係る双方向サイリスタ１は、前述の第１の実施の形態に係る双方向サイリスタ１の第４の半導体領域１４，第５の半導体領域１５、第６の半導体領域１６、第１の接続部３１、第２の接続部３２、第３の接続部３３、第４の接続部３４のそれぞれの平面形状を楕円リング形状により構成している。これらの平面形状以外の双方向サイリスタ１の基本構造は、第１の実施の形態に係る双方向サイリスタ１と同一である。楕円リング形状は長手方向に終端がない閉じた形状である。 [First Modification]
The bidirectional thyristor 1 according to the first modification of the third embodiment shown in FIGS. 10A and 10B is the fourth of the bidirectional thyristor 1 according to the first embodiment described above. The respective planes of the semiconductor region 14, the fifth semiconductor region 15, the sixth semiconductor region 16, the first connection part 31, the second connection part 32, the third connection part 33, and the fourth connection part 34. The shape is an elliptical ring shape. The basic structure of the bidirectional thyristor 1 other than these planar shapes is the same as that of the bidirectional thyristor 1 according to the first embodiment. The elliptical ring shape is a closed shape with no end in the longitudinal direction.

また、第１の変形例に係る双方向サイリスタ１は、前述の第２の実施の形態に係る双方向サイリスタ１においてこのような平面形状により構成してもよい。   Further, the bidirectional thyristor 1 according to the first modification may be configured by such a planar shape in the bidirectional thyristor 1 according to the second embodiment described above.

［第２の変形例］
図１１（Ａ）及び図１１（Ｂ）に示す第３の実施の形態の第２の変形例に係る双方向サイリスタ１は、前述の第１の実施の形態に係る双方向サイリスタ１の第１の主電極（Ｔ１）２１、第２の主電極（Ｔ２）２２、ゲート電極（Ｇ）２３、第４の半導体領域１４，第５の半導体領域１５、第６の半導体領域１６，第１の接続部３１，第２の接続部３２、第３の接続部３３のそれぞれの平面形状を多角形のリング形状により構成している。多角形のリング形状は、ここでは方形のリング形状であるが、三角形のリング形状や五角形以上の多角形のリング形状であってもよい。この多角形のリング形状は長手方向に終端がない閉じた形状である。また、多角形のリング形状においては、角部分の電流密度が高くなり、電界集中が発生し易くなるので、適度な曲率半径の円弧を持たせることが好ましい。これらの平面形状以外の双方向サイリスタ１の基本構造は、第１の実施の形態に係る双方向サイリスタ１と同一である。 [Second Modification]
The bidirectional thyristor 1 according to the second modification of the third embodiment shown in FIGS. 11A and 11B is the first of the bidirectional thyristor 1 according to the first embodiment described above. Main electrode (T1) 21, second main electrode (T2) 22, gate electrode (G) 23, fourth semiconductor region 14, fifth semiconductor region 15, sixth semiconductor region 16, first connection Each planar shape of the part 31, the 2nd connection part 32, and the 3rd connection part 33 is comprised by the polygonal ring shape. Here, the polygonal ring shape is a square ring shape, but may be a triangular ring shape or a polygonal ring shape of pentagon or more. This polygonal ring shape is a closed shape with no end in the longitudinal direction. Further, in the polygonal ring shape, the current density at the corner portion becomes high and electric field concentration is likely to occur. Therefore, it is preferable to have an arc with an appropriate radius of curvature. The basic structure of the bidirectional thyristor 1 other than these planar shapes is the same as that of the bidirectional thyristor 1 according to the first embodiment.

また、第２の変形例に係る双方向サイリスタ１は、前述の第２の実施の形態に係る双方向サイリスタ１においてこのような平面形状により構成してもよい。   Further, the bidirectional thyristor 1 according to the second modification may be configured by such a planar shape in the bidirectional thyristor 1 according to the second embodiment described above.

（その他の実施の形態）
上記のように、本発明を第１の実施の形態乃至第３の実施の形態によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものでない。本発明は様々な代替実施の形態、実施例及び運用技術に適用することができる。例えば、本発明は、前述の双方向サイリスタ１の第１の半導体領域１１〜第６の半導体領域１６の導電型を反転させてもよい。 (Other embodiments)
As described above, the present invention has been described with reference to the first to third embodiments. However, the description and the drawings which constitute a part of this disclosure do not limit the present invention. The present invention can be applied to various alternative embodiments, examples, and operational technologies. For example, in the present invention, the conductivity types of the first semiconductor region 11 to the sixth semiconductor region 16 of the bidirectional thyristor 1 described above may be reversed.

本発明の第１の実施の形態に係る双方向サイリスタの断面図である。1 is a cross-sectional view of a bidirectional thyristor according to a first embodiment of the present invention. 図１に示す双方向サイリスタの電極を除いた各半導体領域並びに接続部のレイアウトを示す平面図である。FIG. 2 is a plan view showing a layout of each semiconductor region and connection portions excluding electrodes of the bidirectional thyristor shown in FIG. 1. 図１に示す双方向サイリスタの電極のレイアウトを示す平面図である。It is a top view which shows the layout of the electrode of the bidirectional thyristor shown in FIG. 図１に示す双方向サイリスタの電極を除いた各半導体領域のレイアウトを示す低面図である。FIG. 2 is a bottom view showing a layout of each semiconductor region excluding electrodes of the bidirectional thyristor shown in FIG. 1. 図１に示す双方向サイリスタの第１のモードの動作状態を示す断面図である。It is sectional drawing which shows the operation state of the 1st mode of the bidirectional thyristor shown in FIG. 第２のモードの動作状態を示す断面図である。It is sectional drawing which shows the operation state of a 2nd mode. 第３のモードの動作状態を示す断面図である。It is sectional drawing which shows the operation state of a 3rd mode. 第４のモードの動作状態を示す断面図である。It is sectional drawing which shows the operation state of a 4th mode. 本発明の第２の実施の形態に係る双方向サイリスタの断面図である。It is sectional drawing of the bidirectional thyristor which concerns on the 2nd Embodiment of this invention. （Ａ）は本発明の第３の実施の形態の第１の変形例に係る双方向サイリスタの平面図、（Ｂ）は（Ａ）に示す双方向サイリスタの底面図である。(A) is a top view of the bidirectional thyristor which concerns on the 1st modification of the 3rd Embodiment of this invention, (B) is a bottom view of the bidirectional thyristor shown to (A). （Ａ）は本発明の第３の実施の形態の第２の変形例に係る双方向サイリスタの平面図、（Ｂ）は（Ａ）に示す双方向サイリスタの底面図である。(A) is a top view of the bidirectional thyristor which concerns on the 2nd modification of the 3rd Embodiment of this invention, (B) is a bottom view of the bidirectional thyristor shown to (A). 本発明の背景技術に係る双方向サイリスタの電極のレイアウトを示す平面図である。It is a top view which shows the layout of the electrode of the bidirectional thyristor which concerns on the background art of this invention. 背景技術に係る双方向サイリスタの電極を除いた各半導体領域のレイアウトを示す平面図である。It is a top view which shows the layout of each semiconductor area | region except the electrode of the bidirectional thyristor which concerns on background art. 背景技術に係る双方向サイリスタの断面図である。It is sectional drawing of the bidirectional thyristor which concerns on background art. 背景技術に係る双方向サイリスタの低面図である。It is a bottom view of the bidirectional thyristor according to the background art.

符号の説明Explanation of symbols

１…双方向サイリスタ
１０…半導体基板
１１…第１の半導体領域
１２…第２の半導体領域
１３…第３の半導体領域
１４…第４の半導体領域
１５…第５の半導体領域
１６…第６の半導体領域
２１、Ｔ１…第１の主電極
２２、Ｔ２…第２の主電極
２３、Ｇ…ゲート電極
３１…第１の接続部
３２…第２の接続部
３３…第３の接続部 DESCRIPTION OF SYMBOLS 1 ... Bidirectional thyristor 10 ... Semiconductor substrate 11 ... 1st semiconductor region 12 ... 2nd semiconductor region 13 ... 3rd semiconductor region 14 ... 4th semiconductor region 15 ... 5th semiconductor region 16 ... 6th semiconductor Region 21, T1 ... first main electrode 22, T2 ... second main electrode 23, G ... gate electrode 31 ... first connection portion 32 ... second connection portion 33 ... third connection portion

Claims (3)

半導体基板と、
前記半導体基板の一方の表面に配設された第１の主電極及びゲート電極と、
前記半導体基板の前記一方の表面と反対の他方の表面上に配設された第２の主電極と、を備え、
前記半導体基板が、第１の導電型の第１の半導体領域と、前記第１の半導体領域の前記一方の表面側に隣接して配設された前記第１の導電型とは逆の第２の導電型の第２の半導体領域と、前記第１の半導体領域の前記他方の表面側に隣接して配設された前記第２の導電型の第３の半導体領域と、前記第２の半導体領域の前記一方の表面側に配設された前記第１の導電型の第４の半導体領域と、前記第３の半導体領域の前記他方の表面側に配設された前記第１の導電型の第５の半導体領域と、前記第２の半導体領域の前記一方の表面側に前記第４の半導体領域と離間して配設された前記第１の導電型の第６の半導体領域と、を備え、
前記第１の主電極が前記第２の半導体領域及び前記第４の半導体領域に電気的に接続され、前記第２の主電極が前記第３の半導体領域及び前記第５の半導体領域に電気的に接続され、前記ゲート電極が前記第２の半導体領域及び前記第６の半導体領域に電気的に接続された双方向サイリスタであって、
長手方向に終端がない閉じた平面形状を有する前記第６の半導体領域と、
この第６の半導体領域の幅方向の一方の側に隣り合って前記ゲート電極と前記第２の半導体領域とを電気的に接続する第１の接続部と、
前記第６の半導体領域の前記幅方向の前記一方の側において、前記第１の接続部から前記第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有する前記第４の半導体領域と、
この第４の半導体領域の幅方向の前記第１の接続部とは反対側の前記一方の側に隣り合って前記第１の主電極と前記第２の半導体領域とを電気的に接続する第２の接続部と、
前記第６の半導体領域の前記幅方向の前記一方の側と反対側の他方の側において、前記第６の半導体領域からこの第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有し、前記第１の主電極と前記第２の半導体領域とを電気的に接続する第３の接続部と、
を備え、
前記第５の半導体領域の平面形状は、長手方向に終端がない閉じた平面形状を有し、
前記半導体基板の前記一方の表面の法線方向から見て前記第５の半導体領域と前記第６の半導体領域との重複部が均一幅を有し、同心のリング形状であることを特徴とする双方向サイリスタ。 A semiconductor substrate;
A first main electrode and a gate electrode disposed on one surface of the semiconductor substrate;
A second main electrode disposed on the other surface opposite to the one surface of the semiconductor substrate,
The semiconductor substrate is a first semiconductor region of a first conductivity type, and a second opposite to the first conductivity type disposed adjacent to the one surface side of the first semiconductor region. A second semiconductor region of the second conductivity type, a third semiconductor region of the second conductivity type disposed adjacent to the other surface side of the first semiconductor region, and the second semiconductor A fourth semiconductor region of the first conductivity type disposed on the one surface side of the region and the first conductivity type disposed on the other surface side of the third semiconductor region. A fifth semiconductor region; and a sixth semiconductor region of the first conductivity type disposed on the one surface side of the second semiconductor region and spaced apart from the fourth semiconductor region. ,
The first main electrode is electrically connected to the second semiconductor region and the fourth semiconductor region, and the second main electrode is electrically connected to the third semiconductor region and the fifth semiconductor region. A bidirectional thyristor, wherein the gate electrode is electrically connected to the second semiconductor region and the sixth semiconductor region,
The sixth semiconductor region having a closed planar shape with no end in the longitudinal direction;
A first connection portion that is adjacent to one side in the width direction of the sixth semiconductor region and electrically connects the gate electrode and the second semiconductor region;
On the one side in the width direction of the sixth semiconductor region, a closed planar shape having no end in the longitudinal direction from the first connection portion to the entire circumference in the longitudinal direction of the sixth semiconductor region. The fourth semiconductor region comprising:
The first main electrode and the second semiconductor region are electrically connected adjacent to the one side opposite to the first connection portion in the width direction of the fourth semiconductor region. Two connections,
Terminate in the longitudinal direction from the sixth semiconductor region over the entire circumference in the longitudinal direction of the sixth semiconductor region on the other side opposite to the one side in the width direction of the sixth semiconductor region. A third connecting portion that has a closed planar shape without any electrical connection and electrically connects the first main electrode and the second semiconductor region;
With
The planar shape of the fifth semiconductor region has a closed planar shape with no end in the longitudinal direction;
The overlapping portion of the fifth semiconductor region and the sixth semiconductor region has a uniform width when viewed from the normal direction of the one surface of the semiconductor substrate, and has a concentric ring shape. Bidirectional thyristor. 半導体基板と、A semiconductor substrate;
前記半導体基板の一方の表面に配設された第１の主電極及びゲート電極と、  A first main electrode and a gate electrode disposed on one surface of the semiconductor substrate;
前記半導体基板の前記一方の表面と反対の他方の表面上に配設された第２の主電極と、を備え、  A second main electrode disposed on the other surface opposite to the one surface of the semiconductor substrate,
前記半導体基板が、第１の導電型の第１の半導体領域と、前記第１の半導体領域の前記一方の表面側に隣接して配設された前記第１の導電型とは逆の第２の導電型の第２の半導体領域と、前記第１の半導体領域の前記他方の表面側に隣接して配設された前記第２の導電型の第３の半導体領域と、前記第２の半導体領域の前記一方の表面側に配設された前記第１の導電型の第４の半導体領域と、前記第３の半導体領域の前記他方の表面側に配設された前記第１の導電型の第５の半導体領域と、前記第２の半導体領域の前記一方の表面側に前記第４の半導体領域と離間して配設された前記第１の導電型の第６の半導体領域と、を備え、  The semiconductor substrate is a first semiconductor region of a first conductivity type, and a second opposite to the first conductivity type disposed adjacent to the one surface side of the first semiconductor region. A second semiconductor region of the second conductivity type, a third semiconductor region of the second conductivity type disposed adjacent to the other surface side of the first semiconductor region, and the second semiconductor A fourth semiconductor region of the first conductivity type disposed on the one surface side of the region and the first conductivity type disposed on the other surface side of the third semiconductor region. A fifth semiconductor region; and a sixth semiconductor region of the first conductivity type disposed on the one surface side of the second semiconductor region and spaced apart from the fourth semiconductor region. ,
前記第１の主電極が前記第２の半導体領域及び前記第４の半導体領域に電気的に接続され、前記第２の主電極が前記第３の半導体領域及び前記第５の半導体領域に電気的に接続され、前記ゲート電極が前記第２の半導体領域及び前記第６の半導体領域に電気的に接続された双方向サイリスタであって、  The first main electrode is electrically connected to the second semiconductor region and the fourth semiconductor region, and the second main electrode is electrically connected to the third semiconductor region and the fifth semiconductor region. A bidirectional thyristor, wherein the gate electrode is electrically connected to the second semiconductor region and the sixth semiconductor region,
長手方向に終端がない閉じた平面形状を有する前記第６の半導体領域と、  The sixth semiconductor region having a closed planar shape with no end in the longitudinal direction;
この第６の半導体領域の幅方向の一方の側に隣り合って前記ゲート電極と前記第２の半導体領域とを電気的に接続する第１の接続部と、  A first connection portion that is adjacent to one side in the width direction of the sixth semiconductor region and electrically connects the gate electrode and the second semiconductor region;
前記第６の半導体領域の前記幅方向の前記一方の側において、前記第１の接続部から前記第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有する前記第４の半導体領域と、  On the one side in the width direction of the sixth semiconductor region, a closed planar shape having no end in the longitudinal direction from the first connection portion to the entire circumference in the longitudinal direction of the sixth semiconductor region. The fourth semiconductor region comprising:
この第４の半導体領域の幅方向の前記第１の接続部とは反対側の前記一方の側に隣り合って前記第１の主電極と前記第２の半導体領域とを電気的に接続する第２の接続部と、  The first main electrode and the second semiconductor region are electrically connected adjacent to the one side opposite to the first connection portion in the width direction of the fourth semiconductor region. Two connections,
前記第６の半導体領域の前記幅方向の前記一方の側と反対側の他方の側において、前記第６の半導体領域からこの第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有し、前記第１の主電極と前記第２の半導体領域とを電気的に接続する第３の接続部と、Terminate in the longitudinal direction from the sixth semiconductor region over the entire circumference in the longitudinal direction of the sixth semiconductor region on the other side opposite to the one side in the width direction of the sixth semiconductor region. A third connecting portion that has a closed planar shape without any electrical connection and electrically connects the first main electrode and the second semiconductor region;
を備え、With
前記第６の半導体領域の平面形状がリング形状により構成され、前記第４の半導体領域の平面形状が前記第６の半導体領域の外側に形成され、前記第５の半導体領域の平面形状が前記第６の半導体領域の内側に形成されていることを特徴とする双方向サイリスタ。The planar shape of the sixth semiconductor region is configured by a ring shape, the planar shape of the fourth semiconductor region is formed outside the sixth semiconductor region, and the planar shape of the fifth semiconductor region is the first shape. The bidirectional thyristor is formed inside the semiconductor region of 6. 半導体基板と、A semiconductor substrate;
前記半導体基板の一方の表面に配設された第１の主電極及びゲート電極と、  A first main electrode and a gate electrode disposed on one surface of the semiconductor substrate;
前記半導体基板の前記一方の表面と反対の他方の表面上に配設された第２の主電極と、を備え、  A second main electrode disposed on the other surface opposite to the one surface of the semiconductor substrate,
前記半導体基板が、第１の導電型の第１の半導体領域と、前記第１の半導体領域の前記一方の表面側に隣接して配設された前記第１の導電型とは逆の第２の導電型の第２の半導体領域と、前記第１の半導体領域の前記他方の表面側に隣接して配設された前記第２の導電型の第３の半導体領域と、前記第２の半導体領域の前記一方の表面側に配設された前記第１の導電型の第４の半導体領域と、前記第３の半導体領域の前記他方の表面側に配設された前記第１の導電型の第５の半導体領域と、前記第２の半導体領域の前記一方の表面側に前記第４の半導体領域と離間して配設された前記第１の導電型の第６の半導体領域と、を備え、  The semiconductor substrate is a first semiconductor region of a first conductivity type, and a second opposite to the first conductivity type disposed adjacent to the one surface side of the first semiconductor region. A second semiconductor region of the second conductivity type, a third semiconductor region of the second conductivity type disposed adjacent to the other surface side of the first semiconductor region, and the second semiconductor A fourth semiconductor region of the first conductivity type disposed on the one surface side of the region and the first conductivity type disposed on the other surface side of the third semiconductor region. A fifth semiconductor region; and a sixth semiconductor region of the first conductivity type disposed on the one surface side of the second semiconductor region and spaced apart from the fourth semiconductor region. ,
前記第１の主電極が前記第２の半導体領域及び前記第４の半導体領域に電気的に接続され、前記第２の主電極が前記第３の半導体領域及び前記第５の半導体領域に電気的に接続され、前記ゲート電極が前記第２の半導体領域及び前記第６の半導体領域に電気的に接続された双方向サイリスタであって、  The first main electrode is electrically connected to the second semiconductor region and the fourth semiconductor region, and the second main electrode is electrically connected to the third semiconductor region and the fifth semiconductor region. A bidirectional thyristor, wherein the gate electrode is electrically connected to the second semiconductor region and the sixth semiconductor region,
長手方向に終端がない閉じた平面形状を有する前記第６の半導体領域と、  The sixth semiconductor region having a closed planar shape with no end in the longitudinal direction;
この第６の半導体領域の幅方向の一方の側に隣り合って前記ゲート電極と前記第２の半導体領域とを電気的に接続する第１の接続部と、  A first connection portion that is adjacent to one side in the width direction of the sixth semiconductor region and electrically connects the gate electrode and the second semiconductor region;
前記第６の半導体領域の前記幅方向の前記一方の側において、前記第１の接続部から前記第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有する前記第４の半導体領域と、  On the one side in the width direction of the sixth semiconductor region, a closed planar shape having no end in the longitudinal direction from the first connection portion to the entire circumference in the longitudinal direction of the sixth semiconductor region. The fourth semiconductor region comprising:
この第４の半導体領域の幅方向の前記第１の接続部とは反対側の前記一方の側に隣り合って前記第１の主電極と前記第２の半導体領域とを電気的に接続する第２の接続部と、  The first main electrode and the second semiconductor region are electrically connected adjacent to the one side opposite to the first connection portion in the width direction of the fourth semiconductor region. Two connections,
前記第６の半導体領域の前記幅方向の前記一方の側と反対側の他方の側において、前記第６の半導体領域からこの第６の半導体領域の長手方向の全周に渡って長手方向に終端がない閉じた平面形状を有し、前記第１の主電極と前記第２の半導体領域とを電気的に接続する第３の接続部と、Terminate in the longitudinal direction from the sixth semiconductor region over the entire circumference in the longitudinal direction of the sixth semiconductor region on the other side opposite to the one side in the width direction of the sixth semiconductor region. A third connecting portion that has a closed planar shape without any electrical connection and electrically connects the first main electrode and the second semiconductor region;
を備え、With
前記第６の半導体領域の平面形状がリング形状により構成され、前記第４の半導体領域の平面形状が前記第６の半導体領域の内側に形成され、前記第５の半導体領域の平面形状が前記第６の半導体領域の外側に形成されていることを特徴とする双方向サイリスタ。The planar shape of the sixth semiconductor region is a ring shape, the planar shape of the fourth semiconductor region is formed inside the sixth semiconductor region, and the planar shape of the fifth semiconductor region is the first shape. The bidirectional thyristor is formed outside the semiconductor region.
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