JPS6399568A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices such as gate turn-off (GTO) thyristors and insulated space bipolar transistors;
In particular, it relates to improved gate and base structures that can reduce turn-off current density and turn-off time.

Gate turn-off silicon rectifiers are four-layer semiconductor devices similar to common silices in that they are triggered into conduction by passing a gate current pulse through the gate electrode. However, unlike ordinary thyristors, gate turn-off thyristors are turned off by passing a current pulse of opposite polarity through the gate electrode, thus requiring a special commutating circuit element that increases the space requirements, cost and complexity of ordinary thyristor circuits. There is no need to provide A gate turn-off switch, also called a GTO switch or GTO-8CR, turns off the anode current with a reverse gate pulse that draws current from the gate conductor. Because GTO devices have regenerative feedback characteristics, relatively large reverse gate pulses are required, especially in the high power devices currently being developed. Typically, to obtain reliable turn-off, at least 10 to 5
A reverse gate current with a magnitude of 0% is required. In fact, it has become common to preselect and apply a sufficiently large gate pulse to interrupt the maximum expected GTO anode current.

Typically, when applying a reverse gate current to turn off a GTO device, the current flowing between the anode and cathode is localized toward the central portion of the device. Specifically, when a turn-off signal is applied to the gate region, the region immediately adjacent to the gate region of the semiconductor device becomes non-conductive first, forcing or localizing the current toward the center of the device. As the turn-off widens, the current density increases at or near the center of the emitter (or cathode). Once the conduction area is localized to a sufficiently small dimension, the device turns off in one dimension since all regeneration processes are interrupted. If the magnitude of the turn-off current applied to the gate electrode is insufficient to cause turn-off, the conducting area of the device becomes extremely localized and destroyed either by excessive heat generation or by avalanche injection. This may cause

One conventional method to solve current crowding at the cathode during turn-off has been to provide a cathode-to-gate short. Such a cathode-to-gate short circuit reduces the cathode current density, increases the di/dt capability of the device, and shortens the turn-off time of the device. Unfortunately, a cathode-to-gate short circuit requires a constant current flowing from the cathode to the gate during the reverse bias period, ie, when the GTO device is turned off. This current is a significant fraction of the on-current in the cathode-gate shorted order tube, thus presenting power loss and undesirable heat generation in the device itself.

Configured in a complex interdigitated comb configuration for high current, low voltage applications or configured in a less comb configuration to obtain a large geometric emitter area for high current, high voltage applications Conventional bipolar transistors are also susceptible to the current localization phenomenon described above with respect to si-risk. This failure mechanism is also called secondary yielding,
Paper by S. Kr1shna and P. L. Hower “
5econd Breakdownof'Trans
istors During Inductive T
urnoff” (Proceedings orthe
1. E, E, E,, Vol, 61. Ma,rch19
63).

= 4 - It is therefore an object of the present invention to have an improved cathode or emitter structure that reduces the current crowding during turn-off, shortens the turn-off time, and increases the threshold against breakdown due to secondary breakdown due to avalanche injection or heat generation. , high power controlled turn-on/turn-off solid state switches, e.g. GTO
The present invention is to provide thyristors and bipolar transistors.

It is another object of the present invention to provide an improved GTO thyristor and bipolar transistor in which no significant cathode-to-gate or base-to-emitter drain current flows during reverse bias turn-off.

A particular object of the present application is to provide a bipolar transistor improved as described above.

The present invention achieves these and other objects by providing an improved cathode or emitter structure that significantly reduces current crowding during turn-off by increasing the area through which current flows during turn-off. According to one embodiment of the invention, in order to prevent significant current from flowing in the central region of the emitter (or cathode) of a semiconductor device, a region of increased resistivity is interposed in this central region; overlay an insulating layer of silicon dioxide. The high impedance central region significantly reduces current crowding and increases the threshold for destruction due to secondary breakdown. In particular, the present application improves the turn-off characteristics of a bipolar transistor by substantially eliminating emitter-base leakage current during turn-off of the bipolar transistor. Moreover, the current gain characteristics of the bipolar transistor are unaffected by this improved emitter structure.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIGS. 1 and 2 show schematic cross-sectional views of a GTO cyrisk with a conventional configuration. A power GTO thyristor 11 is illustrated in FIG. 1 as a four-layer silicon pnpn switch in an interdigitated comb structure, for example of the type described in US Pat. No. 3,609,476. In the illustrated device, the outer semiconductor layers with deposited cathode contact strips or electrodes 12 and anode contacts or electrodes 13, respectively, are known as the N2 emitter layer and the P1 emitter layer, respectively, and the inner semiconductor layers are the P2 base layer and the P1 emitter layer. This is known as the 01 base layer. Gate contact strip or electrode 1
4 are attached on both sides of the emitter strip on the p22 base,
It is arranged to interpenetrate with the cathode contact strip or electrode 12.

Briefly, a feature of the turn-off mechanism of the GTO device is that by applying a reverse gate pulse to the gate terminal G, the anode current flowing from the anode terminal A to the cathode terminal C can be interrupted.

As mentioned above, the main effect here is that by flowing the reverse gate current -ic from the gate terminal, a lateral voltage drop is created at the p2 base, which causes localization or concentration of the current near the center of the n2 emitter. That's true.

The immediate area of the gate electrode 14 is the first area to become non-conducting, and as the current is localized towards the center of the emitter, turn-off begins at the end of the emitter and progresses inward, turning off as the current becomes localized towards the center of the emitter. As the current density increases at or near the center of the emitter. Once the conduction area is localized to a sufficiently small dimension, the device turns off in one dimension since the regeneration process is interrupted. As described above, if the current density at turn-off increases rapidly, the device may undergo secondary breakdown, and the device may be destroyed due to excessive heat generation or electron avalanche injection.

To reduce the magnitude of the current density at the center of the emitter, another GTO structure 20 of the conventional configuration shown in FIG.
In this case, a cathode-gate short circuit is used. Specifically, the second
In the figure, the area 16 is placed at the center of the 02 emitter area,
In this region, the cathode electrode 12 is brought into direct contact with the p2 base layer of the device.

p located at the center of the cathode electrode 12 and the emitter region
2 Direct electrical connection (short circuit or shunt) with base region 16
By doing so, the current concentration at the center of the cathode during the turn-off time is significantly reduced. By reducing the current concentration, not only the turn-off time but also the di/d
The ability will also be improved.

In addition, as the dv/dt capability of the device increases,
The threshold for destruction of the device due to current crowding in the center of the emitter is increased. Unfortunately, the resistance rb of the shorted emitter region is less than the lateral resistance r1 under the cathode electrode, so that a steady current flows from the cathode to the gate during the reverse bias "off" period. This current is a significant proportion of the on-current and represents power loss and undesirable heat generation in the device.

FIG. 3 shows a sectional view of an embodiment according to the invention.

In the present invention, the electrical short between the cathode and gate of the device shown in FIG. 2 is replaced by an electrically insulating layer of, for example, silicon dioxide, which constitutes a high impedance to current flow. Specifically, in the insulated gate turn-off thyristor 22 shown in FIG. 3, an insulating layer 17 is overlaid on the central portion 16 of the p2 base region extending to the surface of the semiconductor device. This causes the upper cathode electrode 12 to
2 to prevent electrical contact with the base region, eliminating cathode-to-gate shorts. The thickness of insulating layer 17 is not critical and can be about 500 to 10,000.

In terms of operation, in the isolated GTO thyrisk device of FIG. 3, by forming a high impedance to current flow in the central portion 16 of the emitter
This reduces current concentration in the central portion 16 of the emitter region during turn-off. As a result, the turn-off time is correspondingly shortened and reliability is significantly improved as device destruction resulting from secondary breakdown effects is reduced. A particularly important feature of a GTO structure constructed in accordance with the present invention is that no current flows from the cathode to the gate during the reverse bias "off" period of the device. This is because, as will be readily understood by those skilled in the art, the insulating layer 17, in combination with the increased resistivity central region 16, prevents any substantial current flow between the cathode and the gate, except for current flowing as leakage current. This is because it prevents water from flowing between the areas. Therefore, the third
The illustrated embodiment of the invention provides all of the desirable characteristics of the prior art device shown in FIG. 2, with the added benefit of eliminating cathode-to-gate drain current during reverse bias "off" periods.

Although the single emitter region is shown in FIG. 3 as intersecting with respect to the adjacent gate region, the large current
It will be obvious to those skilled in the art that it is desirable to have multiple gate and emitter regions in an interdigitated comb configuration to conduct currents (from tens to hundreds of amperes). However, in doing so, it is necessary that the current flow between the anode and cathode be uniformly distributed over the surface of the device. In another embodiment of the present invention shown in FIG. 4, the cell shown in FIG. 3 is used as one cell (device region), and a plurality of cells are arranged adjacent to each other to have uniform turn-on and turn-off characteristics. It has a multi-cell structure. In particular, in Figure 4, the number of square n
2 emitter regions are formed within the p2 base region, for example by well-known diffusion methods. The interconnect grid electrode 12 shown in FIG. 4 is a mesh structure that covers a significant portion of the total surface area of the device. As a result, the cathode displacement current is extremely small and can be carried by the gate electrode, thereby increasing the d v / d capability of the device.

Also, as clearly shown in FIG. 4, no current can flow in the internal region 16 of the n2 emitter region due to the presence of the insulating region 17 and the increased resistivity of the region 16 itself. Therefore, as mentioned above, current crowding is significantly reduced, which reduces the turn-off time and also reduces destruction due to secondary breakdown effects.

As will be understood by those skilled in the art, in the embodiment of the invention shown in FIGS. 3 and 4, the N2 emitter region is square in shape, with the P2 base region extending to the surface of the semiconductor wafer at its center. However, both regions may take other configurations without departing from the spirit of the invention. For example, the emitter and gate regions can be circularly and spirally interdigitated as desired to provide the emitter region with a region of increased resistivity or of the same conductivity type as the base region.

In addition, in FIG. 4, a common cathode metallization layer 19 is formed as a metal interconnect between a plurality of 02 metallization regions on the semiconductor surface. Of course, an insulating layer 18 is interposed between the grid electrode 12 and the common cathode metallization layer 19 to prevent electrical short circuits. As will be readily understood by those skilled in the art, by placing multiple conductors one on top of the other insulated from each other, it is possible to improve the conductivity from the top and bottom surfaces of the semiconductor wafer, an essential requirement for high power semiconductor switches. Uniform heat removal can be achieved.

Although embodiments according to the invention have been described with respect to insulated gate turn-off thyristors, the present application provides bipolar transistors applying the above-described novel features of the invention. For this reason, for example, by replacing the p1 emitter layer functioning as an anode of the thyristor shown in FIGS. 3 and 4 with an n+ layer, a bipolar npn) transistor can be obtained.

In this structure, the n1 base layer becomes the collector region of the bipolar transistor, the p2 base layer becomes the base region, and the n2 emitter layer becomes the emitter region.

A bipolar transistor constructed in a manner similar to the thyristor shown in FIG. 4 exhibits the same desirable characteristics as an insulated gate turn-off thyristor. Emitter current crowding during turn-off is reduced, the threshold for breakdown due to avalanche injection or secondary breakdown due to heat generation is increased, current gain is not sacrificed, and current consumption of the base drive circuit is not increased.

Figures 5a and 5b are circuit diagrams illustrating an example of application of GTO thyrisk and bipolar transistors. Fifth
In Figure a, a pnpn insulated gate turn-off circuit is connected to the circuit 24 that controls the current flowing through the load 25. One solution, shown in Figure 5b, is to connect an npn transistor to the circuit 26 that controls the current flowing through the load 27. It will be apparent to those skilled in the art that the illustrated example of FIGS. 5a and 5b is only an example of the use of insulated gate turn-off transistors and insulated space bipolar transistors, and that various other uses are possible. Furthermore, although the illustrated embodiment relates to a pnpn semiconductor structure, npnp structures are also possible. In addition to silicon, other semiconductor materials such as germanium or 1-2 group semiconductor compounds can also be used as desired.

Complementary structures to npn insulated space bipolar transistors can also be considered.

In summary, the insulated gate turn-off thyristors and insulated space bipolar transistors of the present invention exhibit superior performance characteristics over known conventional thyristors and bipolar transistors. In particular, current crowding and turn-off times are significantly reduced, which leads to undesirable reverse bias 7
1i flow is eliminated, the di/dt and dv/dt capabilities are greatly increased, and the threshold for failure due to secondary breakdown is increased.

Although the present invention has been described with reference to several embodiments, many modifications and changes can be made without departing from the spirit of the invention.

[Brief explanation of the drawing]

1 and 2 are schematic sectional views of a GTO thyristor having a conventional structure, FIG. 3 is a schematic sectional view of a GTO thyristor constructed according to the present invention, and FIG. 4 is a broken perspective view of another embodiment according to the present invention. 5a and 5b are electrical circuit diagrams showing examples of the use of a GTO thyristor and a bipolar transistor, respectively. 12... Cathode electrode, 13... Anode electrode, 14... Gate electrode, 16... Center portion,
17... Insulating layer, 18... Insulating layer, 19
...Cathode metallization layer, 22...Insulated GTO thyristor, pl...Emitter layer, p2...Base layer, n
l...base layer, n2...emitter layer.

Claims (1)

[Claims] 1. Three regions with sequentially overlapping conductivity types alternate,
It includes a semiconductor wafer whose inner region constitutes a base region and whose outer region constitutes an emitter and collector region, and further controls the emitter terminal, the collector terminal, and the current flowing between the collector terminal and the emitter terminal. a bipolar transistor semiconductor device having a base terminal for a semiconductor device having a predetermined resistivity region extending from the base region substantially centrally into the emitter region; extending from the common surface into the base region so as to completely surround the predetermined resistivity region, the region of predetermined resistivity having a higher resistivity than the emitter region; a base electrode disposed on the base region; and a region of the predetermined resistivity to prevent current from substantially flowing from the base region to the emitter region during a non-conducting state of the semiconductor device. A bipolar transistor semiconductor device having an overlying insulating layer. 2. The bipolar transistor semiconductor device according to claim 1, further comprising electrode means for interconnecting the emitter, collector and base regions to the emitter, collector and base terminals, respectively. 3. A plurality of regions having the predetermined resistivity are provided so as to be adjacent to each other at a distance from each other, an insulating layer is overlaid on each of these regions, and further a plurality of regions adjacent to each other at a distance from each other are provided. A bipolar transistor semiconductor device according to claim 1, wherein the bipolar transistor semiconductor devices are electrically interconnected by interconnection means.