JPS62541B2 - - Google Patents

Info

Publication number
JPS62541B2
JPS62541B2 JP1348682A JP1348682A JPS62541B2 JP S62541 B2 JPS62541 B2 JP S62541B2 JP 1348682 A JP1348682 A JP 1348682A JP 1348682 A JP1348682 A JP 1348682A JP S62541 B2 JPS62541 B2 JP S62541B2
Authority
JP
Japan
Prior art keywords
input
output
queue
channel
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1348682A
Other languages
English (en)
Japanese (ja)
Other versions
JPS58129627A (ja
Inventor
Yoshihisa Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1348682A priority Critical patent/JPS58129627A/ja
Publication of JPS58129627A publication Critical patent/JPS58129627A/ja
Publication of JPS62541B2 publication Critical patent/JPS62541B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP1348682A 1982-01-29 1982-01-29 入出力制御装置 Granted JPS58129627A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1348682A JPS58129627A (ja) 1982-01-29 1982-01-29 入出力制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1348682A JPS58129627A (ja) 1982-01-29 1982-01-29 入出力制御装置

Publications (2)

Publication Number Publication Date
JPS58129627A JPS58129627A (ja) 1983-08-02
JPS62541B2 true JPS62541B2 (US07709020-20100504-C00041.png) 1987-01-08

Family

ID=11834441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1348682A Granted JPS58129627A (ja) 1982-01-29 1982-01-29 入出力制御装置

Country Status (1)

Country Link
JP (1) JPS58129627A (US07709020-20100504-C00041.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02144509U (US07709020-20100504-C00041.png) * 1989-05-08 1990-12-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02144509U (US07709020-20100504-C00041.png) * 1989-05-08 1990-12-07

Also Published As

Publication number Publication date
JPS58129627A (ja) 1983-08-02

Similar Documents

Publication Publication Date Title
US5031091A (en) Channel control system having device control block and corresponding device control word with channel command part and I/O command part
US4939644A (en) Input/output controller for controlling the sequencing of the execution of input/output commands in a data processing system
US5170472A (en) Dynamically changing a system i/o configuration definition
US5765200A (en) Logical positioning within a storage device by a storage controller
US4272819A (en) Inter-subsystem direct transfer system
JPH0750456B2 (ja) 入出力制御システム
JP2557199B2 (ja) インターフェース・システムおよび方法
JPH05257866A (ja) 入出力装置に対して実行すべき直接メモリアクセス動作を動的に連鎖する装置及び方法
JPS62541B2 (US07709020-20100504-C00041.png)
JPS62542B2 (US07709020-20100504-C00041.png)
JPS62543B2 (US07709020-20100504-C00041.png)
JPS603229B2 (ja) 情報処理方式
JP2823624B2 (ja) I/oインタフェース制御方法
JPS6127791B2 (US07709020-20100504-C00041.png)
EP0290533B1 (en) I/o system for off-loading operating system functions
JPS6229831B2 (US07709020-20100504-C00041.png)
JPS638506B2 (US07709020-20100504-C00041.png)
JPH0766357B2 (ja) 入出力制御方式
JPH0424733B2 (US07709020-20100504-C00041.png)
JPH01237745A (ja) チャネルパス選択方式
JPH0376505B2 (US07709020-20100504-C00041.png)
JPS61240355A (ja) 入出力デ−タ処理方式
JPS61170855A (ja) 入出力デ−タ処理方式
JPH05151137A (ja) 電子計算機装置
JPS61166659A (ja) チヤネル制御方式