JPS62541B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output control device. When the information processing apparatus inputs and outputs data to peripheral input/output devices such as magnetic desks, teletypes, line printers, etc., these data inputs and outputs are performed via an input/output control device.

Generally, an input/output control device has a plurality of channels, and each of these channels is assigned a plurality of devices. Therefore the central processing unit
When the CPU inputs and outputs data to a specific device, the CPU specifies the channel number to which the device belongs and the device number of the device, and inputs and outputs the data.

Because there are multiple channels, each channel is commonly used by multiple devices, and the operating speed of each device is generally much slower than that of the CPU, the CPU When inputting/outputting data to/from, these points are generally taken into consideration as follows.

CPU (CPU operation program)
First, a channel program is created that specifies the details of the input/output operations to be followed by this input/output device, and is stored at a specific memory address in the main memory. Next, an input/output command is issued to the input/output control device. This I/O instruction has an opcode that specifies that this is an I/O instruction, and
It includes the channel number to which the device to perform input/output belongs, the device number of this device, and information indicating the storage start address of the above-mentioned channel program in the main storage device.

Upon receiving this input/output command, the input/output control device immediately checks the current status of the specified channel and device, and reports the check result to the CPU as a condition code.

This condition code CC distinguishes and displays, for example, four different states.

CC=0 indicates that the specified channel, subchannel, and device are currently ready to execute this I/O command, and therefore this I/O command will begin execution immediately.

CC=1 indicates that the device is currently pending an interrupt or is in use; CC=2 indicates that this channel or subchannel is currently in use (busy) or pending an interrupt.

CC=3 also indicates that the input/output operation cannot be performed because the specified channel, subchannel, or device is currently in a failed state or does not actually exist.

Now, when the report of CC=0 is generated, the input/output control device immediately reads the channel programs in order from the specified address in the main memory and executes the commanded input/output operation accordingly. Start.

On the other hand, the CPU that receives the CC = 0 report identifies that this I/O instruction has been successful, leaves the execution of the actual I/O operation to the I/O controller, and the CPU itself executes the next program. Proceed to. In this way, the execution of input/output instructions that require a relatively long time is transferred from the CPU program to the control of the input/output control device, thereby reducing the overhead of input/output instructions on the CPU program. .

On the other hand, if CC=3 is reported to the CPU, it is impossible to execute this input/output instruction in any case, so the CPU program does not repeat this input/output instruction any more and starts the next one. You can proceed to the program.

On the other hand, if CC = 1 or CC = 2 is reported, the CPU program identifies a temporary failure in execution of the I/O instruction and attempts the same I/O instruction again after an appropriate period of time. Command execution.

In this manner, when an input/output command temporarily fails to execute in a conventional device, the CPU program must perform appropriate processing and issue a command to execute the same input/output command again. This applies only to the execution of input/output instructions.
It has the disadvantage of increasing the overhead for the CPU program.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input/output control device that eliminates the above-mentioned conventional drawbacks.

The device of the present invention is an information processing device including a central processing unit, a main storage device, a channel control device, a plurality of channels, and a plurality of input/output devices. a plurality of input/output queue header tables including information regarding the device number of the device registered at the head of the queue; and information provided for each of the devices regarding whether or not the corresponding device is registered in the queue; Information regarding the storage start address of an input/output instruction for this device stored in the main memory, information regarding the presence or absence of a next device in the queue, and information regarding the device number of the device if there is one. a plurality of input/output queue concatenation tables including a plurality of input/output queue concatenation tables; and a plurality of flip-flops provided for each of the channels and controlled in response to generation/disappearance of each of the queues, and receiving input/output instructions from the central processing unit. The channel control device refers to the header table and the concatenation table corresponding to the channel number and device number specified by the input/output command, uses them to create the queue, sets the flip-flop, and executes any of the When a channel becomes empty, the channel refers to the corresponding flip-flop and generates an interrupt to the controller, and in response, the controller refers to the queue of the corresponding channel and interrupts the queue. Starts invoking input/output commands for devices registered in the device.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining one embodiment of the present invention.

This embodiment includes a central processing unit (hereinafter referred to as CPU) 1, a main memory unit (hereinafter referred to as MM) 2, a channel control unit (hereinafter referred to as CHC) 3, a plurality of channels CH4-1,
...4-K...4-N, and multiple input/output devices IOD5-1-1, 5-1- belonging to each channel
2,...5-1-M ₁ ,...5-K-1,...5-K-
R,...5-K-M _K ,...5-N-1,5-N-
2,...5-N-M _N.

The CHC3 and the channels 4-1 to 4
-N constitutes the input/output control device 6.

The CHC 3 also has an input/output queue header table 30 corresponding to each channel as shown in FIG.
-1,...30-K,...30-N, and an input/output queue concatenation table 31-1- for each input/output device.
1, 31-1-2,...31-1-M ₁ ,...31-
K-1, 31-K-2,...31-K-R,...31
-K-M _K ,...31-N-1,31-N-2,...
31-N-M _N , and a flip-flop FF32- for input/output command execution corresponding to each channel.
1, 32-K, ...32-N.

As shown in FIG. 3, each header table 30 consists of a register having a predetermined bit width, and stores 1-bit information indicating whether an input/output instruction queue exists in the corresponding channel. VLD field, and if this input/output command queue exists, an FST field for storing a pointer pointing to the concatenation table 31 corresponding to the input/output device registered at the head of this queue, and also an FST field of the queue. It also includes an LST field for storing a pointer pointing to the concatenation table 31 corresponding to the input/output device registered at the end.

Each of the concatenation tables 31, as shown in FIG. An NXT field that stores 1-bit information indicating whether or not an input/output device in the order exists, and if the content of this NXT field is "1", a concatenation table corresponding to the input/output device in the next order is specified. to store a pointer to
NXTDP field, ENQ field that stores 1-bit information indicating whether or not the input/output device corresponding to this concatenation table is currently added to the input/output command queue, and An IP field that stores 1-bit information indicating whether a new input/output command has occurred while the input/output device is being added to the input/output device, and a channel program (channel command word, CCW) for this input/output device stored in MM2. Store a pointer indicating the starting address
Contains the CCWAD field.

Now, the data input/output operation according to this embodiment is performed as follows.

Now, as an example, a data input/output operation for the Rth input/output device (that is, device 5-K-R) of the Kth channel (that is, channel 4-K) will be described. FIG. 5, FIG. 6, and FIG. 7 are flowcharts for explaining the operation of this embodiment.

The operation program OS of the CPU 1 is first a channel program (this is called a channel command word (CCW)) that specifies the details of the input/output operations to be performed by the input/output device 5-K-R.
and store it in a specific memory address of MM2.

Next, call CHC3, specify the DAW (device address word: this is the operation to be executed, in the current case, an input/output instruction),
and a word containing the channel number, K in the current example, and the device number, R in the current example, of the input/output device on which this operation is to be performed) and the CAW (command address word; this is the word that contains the A pointer indicating the storage start address in MM2 of the CCW is supplied (FIG. 5A), and waits for a report response using a condesion code from CHC3 (FIG. 5B).

On the other hand, the above call from CPU1 (Figure 5 A)
The received CHC3 is the supplied DAW and CAW.
(Fig. 5 d), and by decoding this, the specified operation is determined as an input/output command.
It is determined whether SIO is 0 for any other instruction (Fig. 5 O). If this is the input/output instruction SI0, as in the current case, check whether the channel K specified in the DAW is currently valid (actually exists and is not currently in a failure state). (Figure 5 F). If it is not valid, the condition code is set to 3 (CC=3) and a report is made to CPU1 (Figure 5, h). Also, if it is valid, set the condescension code to 0 (CC = 0),
Report to CPU1 (Figure 5 K).

When the CPU1 program receives one of these reports, it confirms the reception (Figure 5 B).
The process proceeds to the execution of the next instruction (Fig. 5 C), but in this embodiment, the report based on the condition code of CHC3 for the input/output instruction is CC=0 and CC=3.
CC = 1 and CC of the conventional device mentioned above
The feature is that it does not include a report for =2. For this reason, the above-mentioned drawbacks of the conventional device can be eliminated in the program on the CPU side.

In addition, the above-mentioned operation judgment (Fig. 5 O)
If the decoded instruction is an instruction other than an input/output instruction (for example, a test instruction, etc.), the specified instruction is processed (Fig. This occurs (see Figure 5) and is reported to the CPU, but this processing is the same as in conventional devices.

Now, when CC=0 is sent (Fig. 5 G), the processing of CHC3 proceeds further, and then the DAW
The contents of the concatenation table 31-K-R specified by the channel number K and device number R included in the file are read (see FIG. 5). First, it is checked whether the ENQ field is "1" (Figure 5).

First, the processing when this is "0" will be explained. The fact that the ENQ field is "0" (not "1") means that the input/output device 5-K-R that received this input/output command has not yet been added to the input/output command queue of this channel. (i.e. this input/output device 5-
This means that there are no I/O commands waiting for K-R). Therefore, as soon as an input/output command is issued to this input/output device 5-K-R, the concatenation table 3 for this device is immediately updated.
The ENQ field of 1-K-R is set to "1" to indicate that this has been added to the queue, and at the same time, the CAW (pointer indicating the storage start address in MM2 of the channel program of this input/output instruction) is set to this concatenation. Table 31-K-R
Write in the CCWAD field (Figure 5).

Next, the header table 30-K for this channel 4-K is read (FIG. 5C). Then, it is checked whether the VLD field of this header table 30-K is "0" (FIG. 5-S).
A value of “0” in the VLD field means that there is no I/O command queue for this channel yet (that is, some I/O devices belonging to this channel are currently receiving and executing I/O commands. (meaning there is nothing to wait for). Therefore, the input/output device 5-K-R that has received the current input/output command will form the queue first, so in order to display it, the VLD field of the header table 31-K-R is set to "1'', and a pointer indicating the concatenation table 31-K-R corresponding to this input/output device 5-K-R is stored in the FST field and the LST field (FIG. 5). In this way, the input/output device 31-K-R is registered at the head (and tail) of the input/output command queue of this channel 4-K.

Once this is done, CHC3 will be able to connect to this channel 4.
The flip-flop FF32-K corresponding to input/output instruction execution is set, and this channel 4-K is set.
It is displayed on K that there is an input/output device waiting for execution of an input/output command (FIG. 5, h).

Again, check the above VLD (Figure 5)
If VLD is "1" in this channel 4-K, it means that an input/output instruction queue already exists in this channel 4-K, and the pointer to the last input/output device is in this header table 30-K.
Stored in the LST field. Input/output device 5-K which recently received the input/output start command
-R needs to be registered as the latest input/output device next to the current last input/output device. Therefore, first of all, the header table 30-K
The concatenation table pointed to by the pointer stored in the LST field is selected (Fig. ) is set to "1", and the NXTDP field (this is the field that stores the pointer to the concatenation table corresponding to the next input/output device mentioned above) is set to "1". The last added input/output device 5-K-R compatible concatenation table 31-
A pointer pointing to K-R is stored (see Figure 5), and this same pointer is stored in header table 3.
Store it in the LST field of 0-K (Figure 5),
Indicates that the input/output device 5-K-R is at the end of the input/output command queue for this channel.

Once this is completed, the flip-flop FF32-K for this channel is ready for execution of input/output instructions, as described above.
(see Figure 5C) Normally in this case, the queue already exists, so
2-K should have been set, but as will be described later, this flip-flop 32-K may be reset even if there is a queue, so this is a countermeasure for this). Thus, if an I/O device that has received an I/O command has not previously been added to the queue, this device is newly added to the queue, and the I/O commands for this channel are executed accordingly. A waiting flip-flop will be set.

Now, next, in the process shown in Figure 5 above, ENQ
The processing when the field is "1" will be explained. The fact that the ENQ field is “1” means that the input/output device 5 that received the input/output command this time
-K-R indicates that the input/output command has already been received and is currently registered in a queue waiting for its execution. In this case, instead of registering the same input/output device 5-K-R twice in a new order, the corresponding connection table 31-K-
The IP field of R is set to "1" (FIG. 5 (n)) to indicate that there is a specific processing request for this input/output device 5-K-R. Moreover
Issues an interrupt request to CPU1 (Figure 5 D). In other words, CHC3 has already returned a report of CC=0 (successful reception of input/output command) to CPU1 in response to the commanded input/output command, but in reality, there is a special situation in which it is difficult to accept this as is. Therefore, this is notified to the CPU 1 using an interrupt. Processing for this will be described later.
However, the probability that processing that passes through this branch will occur is low.

Now, the input/output commands are accepted and registered in the queue, and the flip-flop 32-K is set to indicate the existence of this queue.The removal of each of these commands from the queue and their execution are as follows. It will be held in

That is, corresponding to each channel 4-1 to 4-N, each channel is currently in a busy state (that is, a state in which it is executing some process and cannot execute another process) or in an idle state (that is, it is currently in a state in which it cannot execute another process). A channel status monitoring program is running that monitors whether the channel is in an empty state where no processing is being performed and is ready for new processing at any time. This monitoring program for channel 4-K monitors whether channel 4-K is in an idle state (FIG. 6A).

When the execution of a certain input/output instruction on this channel 4-K is finished and this channel 4-K temporarily becomes idle, this program
It is checked whether the input/output instruction execution waiting flip-flop 32-K corresponding to -K is set (see Figure 6A), and if it is set, an interrupt is generated to CHC3 ( (c) in Fig. 6, starts the input/output command queue processing process of CHC3. (Figure 6 d).

When this process starts, it first reads the header table 30-K of the corresponding channel (Fig. 6 O), and registers the input/output device (that is, the head of the input/output command queue) specified by the FST field of this header table 30-K. Read the contents of the subchannel corresponding to the input/output device (input/output device) (Figure 5 F). This subchannel is a memory area provided for each channel corresponding to the input/output device managed by that channel, and the status of each input/output device managed by itself is stored in this subchannel.

In this way, it is checked whether the subchannel corresponding to the input/output device specified in the FST field is idle (Figure 6 G), and when it is confirmed that this input/output device can be started, the ENQ field of the corresponding concatenation table is checked. 6. Set "1" to "0" (Up until now, the ENQ field had "1" in it because it was in the queue, but now we will remove this device from the queue, so we will set the ENQ field to "0". Also, check whether the NXT field in the concatenation table is "1" (Figure 6). If it is "1", there is a device in the next order and it will be added to the queue from next time. Since it will be at the top, the contents of the NXTDP field of the concatenation table of this device to be removed are stored in the FST field of the header table (Figure 6). According to the instruction of the pointer stored in the CCWAD field of the concatenation table of the removed device, the first CCW is retrieved from the MM2 and the startup process for executing the input/output command is started (FIG. 6).

Furthermore, if the NXT field in the concatenation table is "0", the removed device is the last device in the queue, and the removal causes the queue of this channel to disappear. Therefore, after setting the VLD field of the header table of this channel to "0" (FIG. 6) and resetting the input/output instruction execution flip-flop of this channel to "0" (FIG. 6), the above-mentioned procedure is performed. In the same way, startup processing for executing input/output commands begins (see FIG. 6).

Also, in the process of Figure 6-g above, if the subchannel corresponding to the device at the head of this queue is displayed as not being idle, check whether the NXT field of the concatenation table of this device is 1 or not. Check (Figure 6). If the NXT field is "1", read the subchannel corresponding to the input/output device indicated by the NXTDP field (Fig. 6, So). Then, it is checked whether this subchannel is idle or not (Fig. 6). If it is not idle, it is further checked whether the NXT field of the concatenation table corresponding to this subchannel is "1" (FIG. 6, section). In this way, by repeating the loop of s, s, and t in Figure 6, when a device whose subchannel is idle is first found in this queue, that device is removed from the queue and the activation process is performed. I will do it. for that,
First, the concatenation table corresponding to the device found is
The ENQ field is reset from "1" to "0" (Figure 6, h), and depending on whether the NXT field of this concatenation table is "1" or not (Figure 6, T), it is set to "1".
If not, update the contents of the LST field in the header table to point to the previous device (see Figure 6), and update the contents of the concatenation table for the previous device accordingly. (Fig. 6) In this case, as a result of removal, the connection table of the previous device is
NXT field will be “0”).

Also, if the NXT field of the connection table of the device to be removed is 1, only the contents of the connection table of the device before removal are updated (see Figure 6).
Transfer the contents of this removed NXTDP field to the NXTDP field). In this way, the process of starting up the removed input/output device starts as described above (FIG. 6).

Also, if the idle subchannel is not found until the end of this queue (until the NXT field in Figure 6 becomes "0") in the loop of Figure 6, Se, So, Ta, then this In this state, in order to prevent similar interrupts to CHC3 from occurring one after another, the input/output instruction execution flip-flop of this channel is reset to "0" (FIG. 6, N). The flip-flop that has been reset in this way receives a new input/output instruction (the 5th instruction mentioned above).
It is set to "1" again when the above-mentioned situation changes after the input/output processing of a certain input/output device is completed (FIG. 7, h).

Finally, the process when an interrupt request is made to the CPU according to FIG. 5D described above is as follows.

When CHC3 issues an interrupt request, it holds the channel number and input/output device number corresponding to the interrupt request, and when CPU1 accepts the interrupt, it uses this channel number and device number. Access the necessary header and concatenation tables. When the CPU 1 accepts the above interrupt, the CHC 3 reads the concatenation table of the corresponding device using the channel number and device number held above (FIG. 7A). By checking the IP field of the concatenation table (FIG. 7(a)), if this IP field is "1", it is determined that an interrupt request for FIG. 5(d) has been received. Then, a predetermined channel status word CSW indicating that an input/output command has been received for the input/output device in the queue is stored in a predetermined area of MM2.
This is notified to the CPU 1 (FIG. 7C), and since this is the processing of the CHC 3, the IP field of this concatenation table is reset to "0" (FIG. 7D).

Furthermore, interrupts from CHC3 to CPU1 are as follows:
In addition to the above, it is also used when the execution of the input/output instruction started in the startup process in Figure 6 (a) is completed and the result is reported to CPU 1, but in this case, the connection in Figure 7 (a) is used. When the IP field of the table is checked, it is identified that there is no "1" in this field, and the CSW for the input/output instruction execution result is stored in the area of MM2 and reported to the CPU (Fig. 7 O). Read the header table of this channel (Figure 7) and check whether the VLD field is "1" (Figure 7 G). If this is "1", that is, if a queue exists, then The input/output instruction execution flip-flop, which was reset for the reason described in connection with FIG. 6, is reset (FIG. 7, h).
Of course, this is not necessary when the VLD field is "0" because there is no input/output command queue (see FIG. 7).

As mentioned above, using this example,
In response to a CPU input/output command, if the channel number is valid, the CHC always accepts it (reports it to the CPU with CC = 0) and registers it in the input/output command queue, thus creating a queue. When it is set, it sets a flip-flop waiting for an I/O command to be executed, while each channel checks this flip-flop when it becomes idle and ready to execute a new I/O command, and interrupts the CHC if it is set. Upon receiving this interrupt, the CHC removes from the queue the input/output devices registered in the queue that are currently capable of executing input/output commands, and sends them to this device. It is possible to provide an input/output control device that performs an operation such as executing an input/output command instructed by a user.

Therefore, once the CPU issues an input/output command, except in special cases, all subsequent processing can be entrusted to the input/output control device, thereby reducing overhead for input/output commands.

Note that the operations of the CHC and channel CH shown in the flowcharts of FIGS. 5, 6, and 7 of this embodiment can be easily realized using firmware. Of course, it is also possible to implement it using dedicated hardware.

Further, in this embodiment, the physical locations of the input/output command execution flip-flops 32-1 to 32-N are within the CHC 3, but they may of course be located within each channel.

In addition, the input/output queue header tables 30-1 to 30-N, the input/output queue concatenation tables 31-1-1 to 31-N-M _N , and the flip-flops 32-1 to 32-1 to 32-N used in this embodiment are used for input/output command execution. 32-
N can also be configured as the contents of each address in a predetermined area of the RAM.

As described above, when the present invention is used, input/output commands are accepted even when the input/output device is in a state other than idle, the commands are registered in the queue, and when the input/output device becomes idle, the commands are automatically executed one after another starting from the one that became idle. An input/output controller can be provided to handle this. This has the effect of reducing the overhead on the software of the central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining one embodiment of the present invention, and FIG. 2 is for explaining an input/output queue header table, an input/output queue concatenation table, and a flip-flop waiting for input/output command execution used in this embodiment. Figure 3 is a diagram for explaining the format of the input/output queue header table, Figure 4 is a diagram for explaining the format of the input/output queue header table.
This figure is a diagram for explaining the format of the input/output queue concatenation table, and FIGS. 5, 6, and 7 are flowcharts for explaining the operation of this embodiment. In the figure, 1... central processing unit CPU, 2...
...Main memory MM, 3...Channel control device
CHC, 4-1 to 4-N...Channel CH, 5-
1-1~5-N-M _N ...Input/output device IOD,
6... Input/output control device, 30-1 to 30-N...
I/O queue header table, 30-1-1 to 3
1-N-M _N ...I/O queue concatenation table, 3
2-1 to 32-N...Flip-flops waiting for input/output command execution.

Claims (1)

[Scope of Claims] 1. In an information processing device including a central processing unit, a main storage device, a channel control device, a plurality of channels, and a plurality of input/output devices, an input device provided for each channel and created for each channel. a plurality of input/output queue header tables containing information regarding the device number of the device registered at the head of the output command queue; and a plurality of input/output queue header tables provided for each of the devices and information regarding whether the corresponding device is registered in the queue. information, information regarding the storage start address of input/output instructions for this device stored in the main memory, information regarding the presence or absence of a next device in the queue, and information regarding the device number of the device if there is one. a plurality of input/output queue concatenation tables including a plurality of input/output queue concatenation tables, and a plurality of flip-flops provided corresponding to each of the channels and controlled in response to creation and disappearance of each of the queues, and receiving input/output commands from the central processing unit. The channel control device that receives the input/output command refers to the header table and the concatenation table corresponding to the channel number and device number specified by the input/output command, uses them to create the queue, sets the flip-flop, and performs any of the above operations. When a channel becomes empty, the channel refers to the corresponding flip-flop and generates an interrupt to the controller, and in response, the controller refers to the queue of the corresponding channel and stores the data in the queue. An input/output control device characterized in that it starts activating an input/output command to a registered device.