JPS62542B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output control device. When the information processing apparatus inputs and outputs data to peripheral input/output devices such as magnetic desks, teletypes, line printers, etc., these data inputs and outputs are performed via an input/output control device.

Generally, an input/output control device has a plurality of channels, and each of these channels is assigned a plurality of devices.

Therefore, when the central processing unit CPU inputs and outputs data to a specific device,
The CPU inputs and outputs data by specifying the channel number to which the device belongs and the device number of the device.

Because there are multiple channels, each channel is commonly used by multiple devices, and the operating speed of each device is generally much slower than that of the CPU, the CPU When inputting/outputting data to/from, these points are generally taken into consideration as follows.

CPU (CPU operation program)
First, a channel program is created that specifies the details of the input/output operations to be followed by this input/output device, and is stored at a specific memory address in the main memory. Next, an input/output command is issued to the input/output control device. This I/O instruction has an opcode that specifies that this is an I/O instruction, and
It includes the channel number to which the device to perform input/output belongs, the device number of this device, and information indicating the storage start address of the above-mentioned channel program in the main storage device.

Upon receiving this input/output command, the input/output control device immediately checks the current status of the specified channel and device, and reports the check result to the CPU as a condition code.

This condition code CC distinguishes and displays, for example, four different states.

CC=0 indicates that the specified channel, subchannel, and device are currently ready to execute this I/O command, and therefore this I/O command will begin execution immediately.

CC=1 indicates that the device is currently pending an interrupt or is in use; CC=2 indicates that this channel or subchannel is currently in use (busy) or pending an interrupt.

Also, CC=3 indicates that the input/output operation cannot be performed because the specified channel, subchannel, or device is currently in a failure state or does not actually exist.

Now, when the report of CC=0 is generated, the input/output control device immediately reads the channel programs in order from the specified address in the main memory and executes the commanded input/output operation accordingly. Start.

On the other hand, the CPU that receives the CC=0 report identifies that this input/output instruction has been successful, leaves the actual execution of the input/output operation to the input/output controller, and the CPU itself executes the next program. Proceed to. In this way, the execution of input/output instructions that require a relatively long time is transferred from the CPU program to the control of the input/output control device, thereby reducing the overhead of input/output instructions on the CPU program. .

On the other hand, if CC=3 is reported to the CPU, it is impossible to execute this input/output instruction in any case, so the CPU program does not repeat this input/output instruction any more and starts the next one. You can proceed to the program.

On the other hand, if CC=1 or CC=2 is reported, the CPU program uses this to identify a temporary execution failure of the I/O instruction, and waits an appropriate time before attempting the same I/O instruction again. Command execution.

In this manner, when an input/output command temporarily fails to execute in a conventional device, the CPU program must perform appropriate processing and issue a command to execute the same input/output command again. This applies only to the execution of input/output instructions.
It has the disadvantage of increasing the overhead for the CPU program.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input/output control device that eliminates the above-mentioned conventional drawbacks.

The device of the present invention is an information processing device including a central processing unit, a main storage device, a channel control device, a plurality of channels, and a plurality of input/output devices. a plurality of queue header table means including information regarding the device number of the device registered at the head of the queue; information provided for each of the devices regarding whether the corresponding device is registered in the queue; Contains information regarding the storage start address of input/output instructions for this device stored in the main memory, information regarding the presence or absence of a next device in the queue, and information regarding the device number of the device if there is one. a plurality of input/output queue concatenation table means; input/output command activation waiting display means provided for each of the channels and indicating the presence or absence of an input/output device waiting for activation of an input/output command in each of the queues; and an input/output command activation prohibition display means provided in the input/output command to indicate prohibition of activation of the input/output command, and the channel control device receiving the input/output command from the central processing unit displays the channel number and the channel number specified by the input/output command. The contents of the header table means and the concatenation table means corresponding to the device number are referred to and used to create the queue, and the activation waiting display means is set. When an arbitrary channel becomes idle, the channel is An interrupt is generated to the control device by referring to the corresponding display of the activation waiting display means and the activation prohibition display means, and in response, the control device refers to the queue of the corresponding channel and indicates that the channel is in the queue. Start invoking input/output commands for devices registered in .

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram for explaining one embodiment of the present invention.

This embodiment includes a central processing unit (hereinafter referred to as CPU) 1, a main memory unit (hereinafter referred to as MM) 2, a channel control unit (hereinafter referred to as CHC) 3, a plurality of channels CH4-1,
...4-K...4-N, and multiple input/output devices IOD5-1-1, 5- belonging to each channel
1-2,...5-1- _M1 ,...5-K-1...
5-K-R,...5-K-M _K ,...5-N-
1,5-M-2,...5-N-M _N.

The CHC3 and the channels 4-1 to 4
-N constitutes the input/output control device 6.

The CHC 3 also has an input/output queue header table 30 corresponding to each channel as shown in FIG.
-1,...30-K,...30-N, and an input/output queue concatenation table 31- for each input/output device.
1-1, 31-1-2...31-1-M ₁ ,...
31-K-1,...31-K-R,...31-K
-M _K ,...31-N-1,31-N-2...3
1-N-M _N , and a flip-flop FF32- for waiting input/output command activation for each channel.
1,...32-K,...32-N and input/output command activation inhibit flip-flop FF33-1,...
33-K, . . . 33-N.

As shown in FIG. 3, each header table 30 consists of a register having a predetermined bit width, and stores 1-bit information indicating whether an input/output instruction queue exists in the corresponding channel. VLD field, and if this input/output command queue exists, an FST field for storing a pointer pointing to the concatenation table 31 corresponding to the input/output device registered at the head of this queue, and also an FST field of the queue. It also includes an LST field for storing a pointer pointing to the concatenation table 31 corresponding to the input/output device registered at the end.

Each of the concatenation tables 31, as shown in FIG. An NXT field that stores 1-bit information indicating whether or not an input/output device in the order exists, and if the content of this NXT field is "1", a concatenation table corresponding to the input/output device in the next order is specified. to store a pointer to
NXTDP field, ENQ field that stores 1-bit information indicating whether or not the input/output device corresponding to this concatenation table is currently added to the input/output command queue, and An IP field that stores 1-bit information indicating whether a new input/output command has occurred while the input/output device is being added to the input/output device, and a channel program (channel command word, CCW) for this input/output device stored in MM2. Store a pointer indicating the starting address
Contains the CCWAD field.

Now, the data input/output operation according to this embodiment is performed as follows.

Now, as an example, a data input/output operation for the Rth input/output device (that is, device 5-K-R) of the Kth channel (that is, channel 4-K) will be described. FIG. 5, FIG. 6, and FIG. 7 are flowcharts for explaining the operation of this embodiment.

The operation program OS of the CPU 1 is first a channel program (this is called a channel command word (CCW)) that specifies the details of the input/output operations to be performed by the input/output device 5-K-R.
and store it in a specific memory address of MM2.

Next, call CHC3, specify the DAW (device address word: this is the operation to be performed, in the current case, an input/output instruction),
and the channel number of the input/output device on which this operation is to be performed, K in the current example, and the device number, R'' in the current example) and CAW (command address word; this is A pointer indicating the storage start address in MM2 of the CCW) is supplied (fifth
Figure A), waits for a report response from CHC3 using the condition code (Figure 5 B).

On the other hand, the above call from CPU1 (Figure 5 A)
The received CHC3 is the supplied DAW and CAW.
(Fig. 5 d), and by decoding this, the specified operation is determined as an input/output command.
Determine whether SIO is any other instruction (Fig. 5 O). If this is an input/output instruction SIO, as in the current case, check whether the channel K specified in the DAW is currently valid (actually exists and is not currently in a faulty state). (Figure 5 F).

If it is not valid, the condition code is set to 3 (CC=3) and a report is made to CPU1 (Figure 5, h).

If it is valid, the condition code is set to 0 (CC=0) and a report is made to the CPU 1 (FIG. 5G).

When the CPU1 program receives one of these reports, it confirms the reception (Figure 5 B).
The execution proceeds to the next instruction (FIG. 5C), but in this embodiment, the CHC3 condition code report for the input/output instruction is CC=0 and CC=
3, compared to CC=1 and CC of the conventional device mentioned above.
The feature is that it does not include a report for CC=2. For this reason, the above-mentioned drawbacks of the conventional device can be eliminated in the program on the CPU side.
In addition, in the operation judgment (Fig. 5, O), if the decoded instruction is an instruction other than an input/output instruction (for example, a test instruction, etc.), the processing for this specified instruction is performed (Fig. 5, C). , a condition code determined by the result is generated (FIG. 5) and reported to the CPU, but this processing is the same as in the conventional device.

Now, when CC=0 is sent (Fig. 5 G), the processing of CHC3 proceeds further, and then the DAW
The contents of the concatenation table 31-K-R specified by the channel number K and device number R included in the file are read (see FIG. 5). First, it is checked whether the ENQ field is "1" (see Figure 5).

First, the processing when this is "0" will be explained. The fact that the ENQ field is "0" (not "1") means that the input/output device 5-K-R that received this input/output command has not yet been added to the input/output command queue of this channel. (i.e. this input/output device 5
- means there are no I/O commands waiting for K-R). Therefore, as soon as an input/output command is issued to this input/output device 5-K-R, the concatenation table 3 for this device is immediately updated.
The ENQ field of 1-K-R is set to "1" to indicate that this has been added to the queue, and at the same time, the CAW (pointer indicating the storage start address in MM2 of the channel program of this input/output instruction) is set to this concatenation. Table 31-K-R
Write in the CCWAD field (Figure 5).

Next, the header table 30-K for this channel 4-K is read (FIG. 5C). Then, it is checked whether the VLD field of this header table 30-K is "0" (FIG. 5-S).
A value of 0 in the VLD field means that there is no queue for this channel yet (that is, some I/O devices belonging to this channel are currently receiving I/O commands and waiting to be activated). (meaning there is nothing).
Therefore, since the input/output device 5-K-R that currently receives the input/output command will form the queue first, in order to display it, the header table 3
Set the VLD field of 1-K-R to “1”, and set the FST field and LST field,
A pointer indicating the concatenation table 31-K-R corresponding to this input/output device 5-K-R is stored (FIG. 5). Thus, input/output device 31-K
-R is now registered at the head (and tail) of the queue for channel 4-K.

Once this is done, CHC3 will be able to connect to this channel 4.
A flip-flop FF32-K corresponding to input/output command activation is set, and this channel 4-K is set.
It is displayed on K that there is an input/output device waiting for activation of an input/output command (Fig. 5, h).

Again, check the above VLD (Figure 5)
If VLD is "1" in this channel 4-K, it means that a queue already exists in this channel 4-K, and the pointer to the last input/output device is stored in the LST field of this header table 30-K. ing. The input/output device 5-K-R, which newly received the input/output start command this time, needs to be registered as the latest last input/output device after the current last one. Therefore, first, select the concatenation table pointed to by the pointer stored in the LST field of the header table 30-K (Figure 5), and select the NXT of this concatenation table.
field (a bit in this field indicates that the next ranked input/output device in the queue exists in this queue) is set to “1”, and
The NXTDP field (this is a field that stores a pointer to the concatenation table corresponding to the next-ranked input/output device described above) contains the concatenation table corresponding to the input/output device 5-K-R that has been newly added to the end of the queue. 31-K-R is stored (Fig. 5 T), and this same pointer is stored in the LST field of the header table 30-K (Fig. 5 G), and the input/output device 5-K-R is stored.
indicates that is at the end of the queue for this channel.

When this is completed, reset the input/output command activation inhibit flip-flop FF33-K ((Fig. 5 N),
A new device waiting to be activated by an input/output command is added to the queue, indicating that the activation inhibited state has been removed.
(The timing and operation of setting the activation inhibit flip-flop 33-K will be described later). In this way, if an input/output device that has received an input/output command has not been added to the queue before, it is newly added to the queue, and the activation waiting flip-flop 32-K is set accordingly (queue queue). (if a new device is created) or the disabled flip-flop 33-K is reset (if a queue has already been created and this device is added to it).

Now, next, in the process shown in Figure 5 above, ENQ
The processing when the field is "1" will be explained. The fact that the ENQ field is “1” means that the input/output device 5 that received the input/output command this time
-KR indicates that the input/output command has already been received and is currently registered in the queue waiting for its execution. In this case, instead of registering the same input/output device 5-K-R twice in a new order, the corresponding connection table 31-K
-R's IP field is set to "1" (FIG. 5, N) to indicate that there is a specific processing request for this input/output device 5-K-R. Moreover
Issues an interrupt request to CPU1 (Figure 5 D). In other words, CHC3 has already returned a report of CC=0 (successful reception of input/output command) to CPU1 in response to the commanded input/output command, but in reality, there is a special situation in which it is difficult to accept this as is. Therefore, this is notified to the CPU 1 using an interrupt. Processing for this will be described later.
However, the probability that processing that passes through this branch will occur is low.

In this way, the input/output commands are accepted and registered in the queue, and the activation waiting flip-flop 32-K indicating the existence of this queue is set or the activation inhibiting flip-flop 33-K is reset. Dequeuing and activation are performed as follows.

That is, corresponding to each channel 4-1 to 4-N, each channel is currently in a busy state (that is, a state in which some processing is being executed and another processing cannot be executed) or in an idle state (that is, in an idle state). A channel status monitoring program is running that monitors whether the channel is in an empty state (currently not performing any processing and ready for new processing at any time). This monitoring program for channel 4-K monitors whether channel 4-K is in an idle state (FIG. 6A).

When the execution of a certain input/output instruction on this channel 4-K is finished and this channel 4-K temporarily becomes idle, this program executes the flip-flop FF32-K and the input/output instruction waiting flip-flop FF32-K for this channel 4-K. Refer to flip-flop FF33-K (sixth
Figure A), only when the former is set to “1” and the latter is reset to “0”
Generates an interrupt to CHC3 (Figure 6 c),
The input/output command queue processing process of CHC3 is activated (Fig. 6D).

When this process starts, it first reads the header table 30-K of the corresponding channel (Fig. 6, O), and the header specified by the FST field and LST field of this header table 30-K are interconnected as described above. It reads the subchannels corresponding to each concatenation table constituting the channel queue (FIG. 6(f)) and searches for one in an idle state (FIG. 6(g)). This subchannel stores, for each channel, the status of each input/output device managed by that channel.

Thus, when a device with an idle subchannel is found, this device is removed from the link in the queue (FIG. 6H). The process for removing this device is the reverse of the process for registering it in the queue as described above, so I will omit the details, but first, set the ENQ field of the concatenation table corresponding to the device to 0, and then Updates the NXTDP field in the concatenation table of the device at the position of sets the NXT field of the previous device to 0 and the header table.
(Also updates the contents of the LST field).

As a result of this removal, it is checked whether the queue has disappeared (Figure 6), and if the queue has disappeared, the VLD field of the header table is set to 0.
(Fig. 6), and also set the input/output command activation flip-flop FF32-K to 0 (Fig. 6).
From this point on, the startup process for this input/output command starts (see FIG. 6). The input/output command is activated by fetching the first CCW from the MM 2 and executing it in accordance with the pointer stored in the CCWAD field of the concatenation table corresponding to the removed device.

As a result of removal, if the queue still remains (branch of N in Figure 6), the VLD field and the flip-flop waiting for startup 32-K remain as they were and the startup process immediately begins (see Figure 6). shi).

Now, when reading each subchannel in the link mentioned above (Fig. 6 F) and searching for an idle subchannel (Fig. 6 G), if no idle subchannel is found in the queue, sets the input/output command activation inhibit flip-flop FF33-K to "1" (FIG. 6). By doing this, the judgment condition in Figure 6A above is reversed, and in this situation, no further interrupts from channel 4-K to CHC3 (Figure 6C) occur. It is for. As mentioned above, this activation-prohibited flip-flop 33-K is activated when a new input/output command is issued from the CPU 1 and registered in the queue (Fig. When the processing of the output command is completed (FIG. 7G), the status of the subchannel changes accordingly, so it is reset to "0", allowing interrupts from channel 4-K to CHC3 again.

Finally, the process when an interrupt request is made to the CPU according to FIG. 5D described above is as follows.

When CHC3 issues an interrupt request, it holds the channel number and input/output device number corresponding to the interrupt request, and when CPU1 accepts the interrupt, it uses this channel number and device number. Access the necessary header and concatenation tables. When the CPU 1 accepts the above interrupt, the CHC 3 reads the concatenation table of the corresponding device using the channel number and device number held above (FIG. 7A). By checking the IP field of the concatenation table (FIG. 7(a)), if this IP field is "1", it is determined that the interrupt request for FIG. 5(d) described above has been accepted. Then, a predetermined channel status word CSW indicating that an input/output start command has been issued for an input/output device in the queue is stored in a predetermined area of MM2, and this is notified to CPU1 ( FIG. 7C), and since the CHC3 process for this is now complete, the IP field of this concatenation table is reset to "0" (FIG. 7D).

Furthermore, interrupts from CHC3 to CPU1 are as follows:
In addition to the above, it is also used when the execution of the input/output command started in the startup process in Figure 6 B above is completed and the result is reported to CPU 1. In this case, the connection in Figure 7 B is used. When the IP field of the table is checked, it is identified that there is no "1" in this field, and the CSW for the input/output command execution result is stored in the area of MM2 and reported to the CPU (Fig. 7 O). As a result, the status of at least one subchannel changed and there was a possibility that a new input/output instruction could be activated, so flip-flop 3 for inhibiting input/output instruction activation of channel 4-K was created.
If 3-K is set, it is reset to "0" (FIG. 7F).

As mentioned above, using this example,
In response to a CPU input/output command, if the channel number is valid, the CHC always accepts it (reports it to the CPU with CC = 0) and registers it in the input/output command queue, thus creating a queue. When a channel is idle, it sets the flip-flop waiting for I/O command activation or resets the flip-flop inhibiting input/output command activation, while each channel becomes idle and changes the state of these two flip-flops when it becomes ready to execute a new I/O command. In response, the CHC generates an interrupt and requests the start of an I/O command, and the CHC that receives this interrupt waits in order from the devices registered in the queue that can currently execute the I/O command. An input/output control device can be provided that performs operations such as removing the device from the matrix and executing input/output instructions directed to the device.

Therefore, once the CPU issues an input/output command, except in special cases, all subsequent processing can be entrusted to the input/output control device, thereby reducing overhead for input/output commands.

Note that the operations of the CHC and channel CH shown in the flowcharts of FIGS. 5, 6, and 7 of this embodiment can be easily realized using firmware. Of course, it is also possible to implement it using dedicated hardware.

In addition, in this embodiment, input/output command activation waiting flip-flops 32-1 to 32-N and input/output command activation inhibiting flip-flops 33-1 to 33-N are provided.
Although the physical location of N is assumed to be within the CHC 3, it may of course be located within each channel.

In addition, the input/output queue header tables 30-1 to 30-N, the input/output queue concatenation tables 31-1-1 to 31-N-M _N , and the flip-flops waiting for input/output command activation 32-1 to 30-N used in this embodiment 32-N and input/output instruction activation inhibit flip-flop 33-
1 to 33-N can also be configured as the content of each address in a predetermined area of the RAM.

As described above, when the present invention is used, input/output commands are accepted even when the input/output device is in a state other than idle, the commands are registered in the queue, and when the input/output device becomes idle, the commands are automatically executed one after another starting from the one that became idle. An input/output controller can be provided to handle this. This has the effect of reducing the overhead on the software of the central processing unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining one embodiment of the present invention, and FIG. 2 shows an input/output queue header table, an input/output queue concatenation table, and an input/output queue concatenation table used in this embodiment.
FIG. 3 is a diagram for explaining the format of the input/output queue header table, and FIG. 4 is a diagram for explaining the input/output queue concatenation table. FIGS. 5, 6 and 7 are flowcharts for explaining the operation of this embodiment. In the figure, 1... central processing unit CPU, 2...
...Main memory MM, 3...Channel control device
CHC, 4-1 to 4-N...Channel CH, 5-
1-1~5-N-M _N ...Input/output device IOD,
6... Input/output control device, 30-1 to 30-N...
I/O queue header table, 31-1-1 to 3
1-N-M _N ...I/O queue concatenation table, 3
2-1 to 32-N...Flip-flops waiting for input/output command activation, 33-1 to 33-N...Flip-flops inhibiting input/output command activation.

Claims (1)

[Scope of Claims] 1. In an information processing device including a central processing unit, a main storage device, a channel control device, a plurality of channels, and a plurality of input/output devices, an input device provided for each channel and created for each channel. a plurality of queue header table means including information regarding the device number of the device registered at the head of the output command queue; information provided for each of the devices and regarding whether the corresponding device is registered in the queue; information regarding the storage start address of an input/output instruction for this device stored in the main memory; information regarding the presence or absence of a next device in the queue; and, if present, information regarding the device number of the device. a plurality of input/output queue concatenated table means including: input/output command activation waiting display means provided for each of the channels and indicating the presence or absence of an input/output device waiting for activation of an input/output command in each of the queues; an input/output command activation prohibition display means provided corresponding to a channel and indicating prohibition of activation of the input/output command, wherein the channel control device receives the input/output command from the central processing unit and controls the channel specified by the input/output command. The contents of the header table means and the concatenation table means corresponding to the header table means and the concatenation table means are referred to based on the number and device number, the queue is created using the contents, and the start waiting display means is set, so that when an arbitrary channel becomes idle, the corresponding contents are displayed. The channel refers to the display of the corresponding activation waiting display means and the activation prohibition display means and generates an interrupt to the control device, and in response, the control device refers to the queue of the corresponding channel and starts waiting. An input/output control device characterized in that it starts activating input/output commands for devices registered in a matrix.