JPS625352U - - Google Patents
Info
- Publication number
- JPS625352U JPS625352U JP9301985U JP9301985U JPS625352U JP S625352 U JPS625352 U JP S625352U JP 9301985 U JP9301985 U JP 9301985U JP 9301985 U JP9301985 U JP 9301985U JP S625352 U JPS625352 U JP S625352U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- exclusive
- address
- latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Detection And Correction Of Errors (AREA)
Description
第１図はこの考案の一実施例に従うデータ誤り
検知回路の回路構成図、第２図は従来のデータ誤
り検知回路の回路構成図である。
図において、５はＲＯＭ、１１は排他的論理和
回路、１２はラツチ／シフトレジスタ回路、１３
はアドレスカウンタ回路、１６はサムデータチエ
ツク回路である。なお、各図中、同一符号は同一
又は相当部分を示す。
FIG. 1 is a circuit diagram of a data error detection circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional data error detection circuit. In the figure, 5 is a ROM, 11 is an exclusive OR circuit, 12 is a latch/shift register circuit, and 13 is a latch/shift register circuit.
1 is an address counter circuit, and 16 is a sum data check circuit. In each figure, the same reference numerals indicate the same or equivalent parts.
Claims (1)
レスに夫々記憶されているデータの誤りの有無を
チエツクするための指標データを記憶している記
憶回路と、該記憶回路の各アドレスに記憶されて
いる前記データを所定のタイミングで逐次読出す
メモリアドレス信号を出力するアドレス計数回路
と、外部から与えられたデータを受けてこれを一
時的に記憶するとともに所定の信号が入力された
ときに該データをパラレル／シリアル変換して出
力するラツチ／シフトレジスタ回路と、前記記憶
回路から逐次出力されるデータと前記ラツチ／シ
フトレジスタ回路から帰還されたデータとの排他
的論理和をとつて前記ラツチ／シフトレジスタ回
路に出力する排他的論理和回路と、前記排他的論
理和回路において前記指標データと該指標データ
の直前の排他的論理和データとの排他的論理和を
とつた最終データが前記ラツチ／シフトレジスタ
回路から出力されたときに、該最終データを受け
て該データを構成している各々のビツト毎に予め
設定された基準値と比較することによつて誤りを
チエツクするデータチエツク回路とを有するデー
タ誤り検知回路。 A memory circuit that stores index data for checking the presence or absence of errors in the data stored at each address before the final address at the final address; and An address counting circuit that outputs a memory address signal that reads data sequentially at a predetermined timing, and an address counting circuit that receives externally applied data and temporarily stores it, and converts the data in parallel when a predetermined signal is input. / A latch/shift register circuit that serially converts and outputs data, and a latch/shift register circuit that performs an exclusive OR of data sequentially output from the storage circuit and data fed back from the latch/shift register circuit. and an exclusive OR circuit that outputs the final data obtained by exclusive ORing the index data and the exclusive OR data immediately before the index data in the exclusive OR circuit to the latch/shift register circuit. and a data check circuit that receives the final data and checks for errors by comparing each bit of the data with a preset reference value when the data is output from the data. Detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9301985U JPS625352U (en) | 1985-06-21 | 1985-06-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9301985U JPS625352U (en) | 1985-06-21 | 1985-06-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS625352U true JPS625352U (en) | 1987-01-13 |
Family
ID=30955238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9301985U Pending JPS625352U (en) | 1985-06-21 | 1985-06-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS625352U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5178938A (en) * | 1974-12-31 | 1976-07-09 | Sharp Kk | Kiokusochino tajushorisochi |
| JPS5337041A (en) * | 1976-09-17 | 1978-04-05 | Seiichi Komazaki | Sunbeam multistage condensing method and apparatus |
| JPS5373041A (en) * | 1976-12-13 | 1978-06-29 | Nec Corp | Detection device for fixed memory error |
-
1985
- 1985-06-21 JP JP9301985U patent/JPS625352U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5178938A (en) * | 1974-12-31 | 1976-07-09 | Sharp Kk | Kiokusochino tajushorisochi |
| JPS5337041A (en) * | 1976-09-17 | 1978-04-05 | Seiichi Komazaki | Sunbeam multistage condensing method and apparatus |
| JPS5373041A (en) * | 1976-12-13 | 1978-06-29 | Nec Corp | Detection device for fixed memory error |
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