JPS6085462U - PCM communication data detection circuit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram of a PCM commutation data detection circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of an input PC.
3 is a diagram showing the configuration of M parallel data, the contents of a down counter 9, and the output timing of each signal. FIG. l: ROM, 2. 3: Comparator, 4: Word specification means, 5: Frame specification means, 6: Register (commutation information), 7: OR gate circuit, 8: AND gate circuit, 9: Down counter, 10: Register (commutation data) , So: frame rate signal, S2
: Word match signal, S3: Frame match signal, S4 Two-rod signal, S: Latch signal, S8: Ripple carry signal. L? Nininini? "S・]r 7(θshiyW"'

Claims (1)

[Scope of utility model registration request] A storage circuit that stores commutation information indicating the detection cycle of commutation data in advance and outputs its contents sequentially in synchronization with word count data synchronized with PCM parallel data; in the case of super commutation, the initial stage of a word a word specifying means for specifying a value tone; a word comparator for inputting word count data and comparing it with the initial value of the word; and outputting a word match signal when they match; and in the case of super sub commutation, the word specifying means; , frame specifying means for specifying an initial value of a frame, and the word comparator, inputting frame count data synchronized with PCM parallel del data and comparing it with the initial value of the frame, and outputting a frame match signal when they match. a frame comparator that loads the contents of the storage circuit by means of a word match signal, a load signal by a word match signal in the case of supercommutation, and a word match signal and a frame match signal in the case of super subcommutation; and a control circuit that outputs a latch signal, and the content of the first storage means is loaded by a load signal, and in the case of supercommutation, the control circuit outputs a latch signal.
The loaded contents of the first storage means are sequentially subtracted by the word rate signal synchronized with the CM parallel signal, or in the case of super subcommutation, the frame rate signal synchronized with the PCM parallel signal, and when it becomes zero, a ripple carry occurs. A down counter that outputs a signal and outputs the load signal and the latch signal again by a control circuit, and a second storage means that captures predetermined commutation data of the PCM parallel data using the latch signal. PCM commutation data detection circuit.