JPH02216563A - Associative memory - Google Patents

Abstract

PURPOSE:To improve the reliability of a comparing operation by connecting an associative memory for an error detecting code through a MOS transistor (TR) to an associative memory for data registration and comparing operation, and comparing the input data error detecting code with the registered data error detecting code. CONSTITUTION:A coincidence signal 18 of an N-bit associative memory 12 is connected through a MOS TR 19 to an associative memory coincidence signal 17 for the error detecting code of an L-bit associative memory 15, and the TR 19 is turned on only during the comparison of the data. In addition, the data are inputted from N-bit data 11, registered into the memory 12, a data error detecting code 14 is generated by an arithmetic circuit 13, and registered to the memory 15. Further the memory 15 compares the code 14 by means of the circuit 13 with the registered data error detecting code, when they correspond, the signal 17 is outputted, and only when the data are correspond, the signal 18 is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device, and more particularly to an associative memory device.

[Conventional technology]

A conventional associative memory device has a data storage means, a comparator stage for input data and registered data, and means for outputting the comparison result as a coincidence signal, but it does not have a check function for data comparison operation. does not have.

[Problem to be solved by the invention]

Since the conventional associative memory device described above does not have a means for checking the data comparison operation, the reliability of the comparison operation depends on the reliability of the device, and therefore has the drawback that errors in the comparison operation cannot be detected.

[Means to solve the problem]

The present invention provides an associative memory cell having means for storing 1-bit data, means for comparing data input to a bit line with stored data, and means for outputting the comparison result as a coincidence signal. In an N bit x M word content addressable memory device in which N bits are connected in the word direction and M words are connected in the bit line direction, an error detection code calculation circuit that can generate an error detection code for input N bit data is connected to the bit line. , and can register the error detection code generated by the error detection code calculation circuit at the time of data registration, and compare the error detection code generated from the input data and the registered error detection code during the data comparison operation. A MOS transistor that is in an on state during a data comparison operation between a match signal of each word of the associative memory and its own match signal, in which M words of L-bit content addressable memory are connected in the bit line direction, and an error detection code is registered. In the data comparison operation, the input data and the error detection code generated by the error detection code calculation circuit are connected to the associative memory for data registration and the associative memory for registering the error detection code of the registered data, respectively. This configuration verifies the normality of the data comparison operation by outputting a match signal when the two match.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention for one word. The word line 16 of the N-bit associative memory 12 and the L-bit associative memory 15 is common, and the N-bit associative memory match signal 18
The error detection code associative memory match signal 17 of the L-bit associative memory 15 is ON only during the data comparison operation.
It is connected by an OS transistor 19, and the data input to the error detection code calculation circuit 1-3 is an N-bit content addressable memory 12.
This is done using the N bit data (bit line) 11, which is common to
The calculation result is transferred to the L-bit content addressable memory 15 using the error detection code 14.
In an associative memory device with an error detection function that can input data by controlling the word line 16, data is registered in the N-bit associative memory 12, and at the same time, the error detection code 14 of the input N-bit data 11 is The error detection code is generated by the error detection code calculation circuit 13 and is stored in the L bit associative memory 15.
Register to. In the data comparison operation, N and the data 11
By inputting data to the N-bit associative memory 12 and the error detection code calculation circuit 13, the N-bit associative memory
Then, the input data and the registered data are compared, and if they match, the N-bit content addressable memory match signal 18 (logical value "1") is output.
The L-bit content addressable memory 15 compares the error detection code 14 generated by the error detection code calculation circuit 13 with the error detection code of the registered data, and if they match,
Associative memory match signal 17 for error detection code (logical value ゛1°
°) is output. In the data comparison operation, the MoS transistor 19 is turned on, so only when the comparison operations in the L-bit associative memory and the N-bit associative memory match, the N
Bit associative memory match signal 18 is output (logical value "1"
) to be done. In other words, if either one does not match, N
The bit associative memory match signal 18 outputs the logical value "0°".By connecting the one word associative memory shown in FIG. 1 in the bit line direction, the error detection code calculation circuit can be shared and the associative memory It is easy to infer that only the capacity of can be increased.

〔Effect of the invention〕

As explained above, according to the present invention, an associative memory for error detection codes for checking data comparison operations is connected to an associative memory for data registration and comparison operations via MoS transistors, and input data is In addition to the data comparison operation for the data, the error detection code calculation circuit generates an error detection code for the input data and compares it with the error detection code for the registered data, thereby verifying the reliability of the associative memory comparison operation. This can be improved more than if you do this.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an associative memory device having a check function for a one-word data comparison operation according to an embodiment of the present invention. 11...N bit data (bit line), 12...N
Bit associative memory, 13... error detection code calculation circuit,
14... Error detection code, 15... L bit associative memory, 16... Word line, 17... Associative memory match signal for error detection code, 18... N bit associative memory match signal, 19. ...MOS transistor.

Claims (1)

[Claims] An association comprising means for storing 1-bit data, means for comparing data input to a bit line with stored data, and means for outputting the comparison result as a coincidence signal. An error detection code calculation circuit that can generate an error detection code for input N-bit data in an N-bit x M-word content addressable memory device in which memory cells are connected by N bits in the word direction and M words in the bit line direction. is connected to the bit line, and the error detection code generated by the error detection code calculation circuit can be registered at the time of data registration, and the error detection code generated from the input data and the registered error detection code can be registered at the time of data comparison operation. M is an L-bit associative memory that can be compared.
It is connected in the bit line direction for each word, and is connected through a MOS transistor that is turned on during a data comparison operation between the match signal of each word of the associative memory in which the error detection code is registered and its own match signal, and is connected to the data comparison operation. If the input data and the error detection code generated by the error detection code calculation circuit based on the input data are compared between the data registration associative memory and the error detection code registration associative memory of the registered data, and the two match. 1. An associative memory device that verifies the normality of a data comparison operation by outputting a match signal to a data addressable memory device.