JPS63177242A - Parity check method for associative memory - Google Patents

Abstract

PURPOSE:To detect a parity error at a high speed by using a 1st means which detects the coincidence between the parity information corresponding to the output of a parity generating circuit and the data to be retrieved and a 2nd means which detects the coincidence between the retrieving data and the data to be retrieved and then validating or invalidating the output of the 1st means with the output of the 2nd means. CONSTITUTION:The data stored in an array 2 of memory cells to be retrieved is selected by a lower rank bit (b) of an address and a signal of a low amplitude level is outputted via a data line (c). This signal is amplified by a sense circuit 3 and used as the read data (d) of the array 2. Then a comparator 4 retrieves the coincidence between a bit (a) serving as the retrieving data and the data (d) for output of a bit signal (g) to complete a retrieving action. While in a parity check mode the data contained in a parity memory cell array 2' by the bit (b) and a signal of a low amplitude level is outputted via a data line (c'). This signal is amplified by a sense circuit 3' to be used as the parity information (d'). Then a comparator 4' compares the information (d') with the parity (f) received from a parity generating circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an associative memory, and more particularly to a parity check method for an associative memory using a semiconductor integrated circuit.

[Conventional technology]

An associative memory is a memory whose internal contents are accessed depending on the content to be matched (searched for), and in computer systems, it has applications such as cache memory and TT-B for address translation. The content addressable memory has two memory cell arrays, and the first memory cell array stores data to be retrieved when comparing data (search data) with data to be searched (search data). and.

The search data is compared with the data stored in the first memory cell array A, and if they match, the data stored in the second memory cell array is output.

By the way, in a computer system, if an error occurs in data stored in a memory cell array, a parity check is generally performed to detect the error. Parity is from Me Gray-Hill.
Electronic Digital Technics, published in 1968 by Electronic Digital Technics Inc.
c Digital Technologies), p. 1
It is generated from arbitrary data as described in 14-p. and 116. Parity checking is an application of this to data error detection. When writing data to a memory cell array, the data is divided into several blocks, parity is generated for each block, and this parity information is also added to the data. and write it down, and
When reading data, by comparing the parity generated from the read data in the same way as when writing, and the parity information written in advance,
This is to determine whether an error has occurred in the stored data.

A conventional example of a parity check method in an associative memory will be explained with reference to FIG. 10.11. FIG. 10 is a diagram showing the configuration of the search section of the associative memory and its parity check method, and FIG. 11 is a diagram showing its time chart. The upper bit a of the address output from the address register 1 is search data, and the lower bit b is an address for selecting one of the memory cell arrays 2 for the data to be searched. The memory cell holding the searched data selected by b outputs a low amplitude level signal to the data line C,
The sense circuit 3 amplifies the read data d from the memory cell array 2 to a logic level signal. Comparison circuit 4 compares a and d, and if they match, outputs a hit signal g. The parity memory cell array 2' storing the parity corresponding to the data held in the parity information 2 is selected by b, the data line c/ is read out as parity information d' via the sense circuit 3', and the parity information is read from d. Parity e and d' generated by generation circuit 5 are compared by comparison circuit 4', and if they match, a parity check signal i is output, and the parity check is completed.

(Problems to be Solved by the Invention) In the above conventional technology, the parity check of the memory cell array for searched data is performed by reading out the memory cell array for searched data, generating the parity of the data, and holding it in advance. In other words, when performing a parity check,
A series of operations including accessing the memory cell array, generation of parity, and comparison are required, and there is a problem in that it takes too much time to complete the parity check.

An object of the present invention is to provide a parity check method that detects data errors at high speed.

The above purpose is to use a parity generation circuit that receives search data as input, and to connect the output of the parity generation circuit with parity information held in advance corresponding to the searched data. By comprising a first means for detecting a match, and a circuit for validating or disabling the output of the first means based on the output of the second means for detecting a match between the search data and the searched data, achieved.

(Operation) In the parity check of the memory cell array for searched data, the parity generation circuit generates the parity of the search data from the search data that is matched with the searched data, and the parity information stored in advance corresponding to the searched data is generated. Detects a match between the search data and the searched data, and validates the match between the search data and the searched data based on the match detection result.In other words, the parity of the data held in the memory cell array for the searched data is validated. Embodiment 2 Using parity generated from search data as Embodiment An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a diagram showing the configuration of a search section of an associative memory and its parity check method, and the same reference numerals as in FIG. 10 indicate the same parts. The difference in FIG. 1 from FIG. 10 is that the parity f generated by the parity generation circuit 5 from the search data a is used as the comparison circuit 4' to compare the parity information d' corresponding to the searched data. Furthermore, the output of the comparator circuit 4' is input to a signal validating circuit 6, and is controlled by a hit signal g to become a parity check signal i.

FIG. 2 is a time chart showing the operation of each point in FIG. When the lower bit b of the address is input to the search section, one piece of data in the memory cell array 2 to be searched is selected, and the selected memory cell outputs a low amplitude level signal to the data line C. The signal C is amplified to a logic level signal by the sense circuit 3 and outputted as read data d from the memory cell array 2. d is determined by the comparator circuit 4.

A match is detected with the upper bit a of the address which is the search data, a hit signal g is outputted, and the search operation is completed.

On the other hand, as a parity check.

A parity memory cell array 2 that stores parity information corresponding to data in the memory cell array 2 for searched data.
' is also selected by b, and the selected memory cell outputs a low amplitude level signal to the data line C'. The signal at c/ is amplified to a logic level signal by the sense circuit 3', and the parity information corresponding to d is output. Output d'. Parity f, which is detected to match d' by comparison circuit 4', is an output generated by parity generation circuit 5 from a, and is processed in parallel with the readout of d', and 4' outputs a match detection output. . b confirms the coincidence of a and d by g and outputs a parity check signal i via the signal validation circuit 5;
Parity check ends.

According to this embodiment, the parity generated once from the search data can be used in the parity check of the memory cell for the data to be searched, so that highly variable operation is possible.

FIG. 3 shows another embodiment of the invention. In Figure 3,
The same reference numerals as in FIGS. 1 and 10 indicate the same parts. Third
The difference between the figure and FIG. 1 is that a match between the data line C, which is a low amplitude level signal output by the memory cells in the memory cell array 2 for searched data, and the search data a is detected and output as a hit signal g. A coincidence detection circuit 7 is used, and other operations are the same as in the embodiment shown in FIG. FIG. 4 is a time chart showing the operation of each point in FIG. - By using the multiple output circuit 7, in order to detect coincidence without amplifying low amplitude level signals,
The hit signal g can be obtained at high speed.

5.6.7 is a diagram showing an example of a circuit configuration for realizing the coincidence detection circuit 7 of FIG. 3. In FIG. 0, 10 is N
Differential data line Dt with diode-connected MOS transistors, stone termination resistor.

11 is a logic circuit that crosses the input and output of the two CMOS inverters and performs an FORR between the bit line signal and the search data;
13 is a voltage-current conversion circuit using a differential pair of bipolar transistors, and 14 is an output circuit that converts current input into a logic level voltage output.

In this circuit, the data line data, which is a low-amplitude level signal that the memory cell directly drives to output data, and the search data are subjected to EOR logic, and the logic output is converted into a current.
By performing wired OR, a high-speed and compact coincidence detection circuit can be realized.

According to this embodiment, the same effects as the embodiment shown in FIG. 1 can be obtained. Furthermore, since there is no need to read data from the memory cell array for search target data, a sense circuit is not required and the circuit configuration is simplified. Further, by using a -number output circuit, a hit signal can be obtained at high speed.

FIG. 8 shows another embodiment of the present invention. In Figure 8,
The same reference numerals as in FIG. 1.3.10 indicate the same parts.

The difference between FIG. 8 and FIG. 3 is that a coincidence detection circuit 7' is used which detects point coincidence and outputs an output.

FIG. 9 is a time chart showing the operation of each point in FIG. - By using the multiple output circuit 7', it is possible to obtain the parity check signal i even faster in order to detect a coincidence without amplifying a low amplitude level signal.

In this embodiment, it is also possible to use circuits with the same configuration for the -number output circuits 7 and 7', making the overall circuit configuration extremely simple and the layout easy. Furthermore, since a match is detected using a low-amplitude level signal output from a memory cell, both the search operation and the parity check can be performed at high speed.

〔Effect of the invention〕

According to the present invention, in the parity check of the memory cell array section for searched data, parity is generated not from the data read from the memory cell array for searched data, but from the detected data that is matched with the read data. This has the effect of realizing high-speed parity check operation.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing one embodiment of the present invention, Fig. 2 is a time chart of the embodiment of Fig. 1, Fig. 3 is a diagram showing another embodiment of the invention, and Fig. 4 is a diagram showing the third embodiment. A time chart of the embodiment; FIGS. 5, 6, and 7 are diagrams showing an example of the components in the embodiment of FIG. 3; FIG. 8 is a diagram showing another embodiment of the present invention;
9 is a time chart of the embodiment shown in FIG. 8, FIG. 10 is a diagram showing a conventional example, and FIG. 11 is a time chart of the conventional example shown in FIG. 2...Memory cell array, 3...Sense circuit, 4.
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Claims (1)

[Claims] 1. In an associative memory having a first memory cell array and a first means for detecting coincidence between data stored in the first α memory cell and external data, the data stored in the first memory cell A second memory cell array that stores corresponding parity information, a parity generation circuit that receives external data as input and generates parity, and a match between the data stored in the second memory cell array and the output of the parity generation circuit. 1. A parity check method for an associative memory, comprising: second means for detecting; and a circuit for validating or invalidating the output of the second means based on the output of the first means.