JPS6252959B2 - - Google Patents
Info
- Publication number
- JPS6252959B2 JPS6252959B2 JP13112281A JP13112281A JPS6252959B2 JP S6252959 B2 JPS6252959 B2 JP S6252959B2 JP 13112281 A JP13112281 A JP 13112281A JP 13112281 A JP13112281 A JP 13112281A JP S6252959 B2 JPS6252959 B2 JP S6252959B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- lands
- land
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910000679 solder Inorganic materials 0.000 claims description 35
- 239000011888 foil Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000006096 absorbing agent Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明はチツプ状抵抗やフラツト状の集積回路
体等の電子部品の電極を印刷配線基板の導箔から
なるランドに載置して半田付けを行なう形式の印
刷配線基板装置に関し、予め接続用ランドに附着
する半田の量を均一化し、隣接ランド間の短絡を
防止するようにしたものである。Detailed Description of the Invention The present invention relates to a printed wiring board in which electrodes of electronic components such as chip resistors and flat integrated circuits are placed on lands made of conductive foil of the printed wiring board and soldered. Regarding the device, the amount of solder attached to the connecting lands is made uniform in advance to prevent short circuits between adjacent lands.
チツプ状抵抗やフラツトパツク状の集積回路体
等の電子部品を印刷配線基板上に載置し、その電
子部品の電極を接続用ランドに接合させて半田付
けを行なうようにした面実装形態の印刷配線基板
装置においては、従来第１図に示すように印刷配
線基板１の接続用ランド２に予めデツプ法によつ
て半田を附着し、この半田附着状態で電子部品３
を載置し、この電子部品３の電極４を第２図に示
すようにヒータブロツク５により加圧することに
よつて半田６を溶融させて電極４をランド２に半
田付けするようにしている。 Surface-mount printed wiring in which electronic components such as chip resistors and flat pack integrated circuits are mounted on a printed wiring board, and the electrodes of the electronic components are bonded to connection lands and soldered. Conventionally, in a board device, as shown in FIG. 1, solder is applied to the connection land 2 of a printed wiring board 1 in advance by the depth method, and the electronic component 3 is attached in this soldered state.
is placed on the electronic component 3, and the electrode 4 of the electronic component 3 is pressurized by a heater block 5 as shown in FIG. 2 to melt the solder 6 and solder the electrode 4 to the land 2.
従来、上記の印刷配線基板１のランド２に予め
半田６を附着するには、第３図に示すようなデツ
プ法が用いられている。すなわち印刷配線基板１
の導箔面側を半田槽の半田噴上げ部７側にして矢
印方向に移動させることによりランド２に半田６
を附着するようにしているが、この場合、複数個
のランド２が近接配置されていると、第３図のａ
に示すように印刷配線基板１を矢印方向に移動さ
せて行つた場合、半田噴上げ部７に突入する各ラ
ンド２には同図ｂ，ｃに示すような現象が生ず
る。 Conventionally, a dip method as shown in FIG. 3 has been used to apply solder 6 to the lands 2 of the printed wiring board 1 in advance. That is, printed wiring board 1
The solder 6 is placed on the land 2 by moving it in the direction of the arrow with the conductive surface side of the solder bath facing the solder spouting part 7.
However, in this case, if a plurality of lands 2 are arranged close to each other, a of FIG.
When the printed wiring board 1 is moved in the direction of the arrow as shown in the figure, the phenomena shown in b and c of the figure occur on each land 2 that enters the solder spouting portion 7.
すなわち、印刷配線基板１の移動で半田噴上げ
部７に突入して行く各ランド２ａ，２ｂ，２ｃ…
…において、先行するランドに続いて半田噴上げ
部７に突入して行くランド２ｂ，２ｃ……はその
先行ランドにより半田が薄く濡れた状態になるた
め、半田噴上げ部７から離脱された状態ではそれ
らのランド２ｂ，２ｃ……には半田６ｂ，６ｃ…
…が薄くかつ均一に附着するが、先行するランド
がないランド２ａにあつては噴上げ半田を薄く引
いて行くものがないため、このランド２ａには非
常に厚く半田６ａが附着される。 That is, the lands 2a, 2b, 2c, . . . rush into the solder spouting portion 7 as the printed wiring board 1 moves.
In ..., the lands 2b, 2c, which rush into the solder spouting part 7 following the preceding land, are in a state where they are separated from the solder spouting part 7 because the solder is thinly wetted by the preceding land. Then solder 6b, 6c... to those lands 2b, 2c...
The solder 6a is thinly and evenly attached to the land 2a, but since there is nothing to pull the spouted solder thinly to the land 2a where there is no preceding land, the solder 6a is attached very thickly to the land 2a.
このようにランド２ａに厚く半田６ａが附着さ
れるとヒータブロツク５で電子部品３の電極４を
半田付けする時、溶融した半田がランド２ｂ方向
に流れ出てランド２ａと２ｂが短絡を起すという
不都合が生ずる。 If the solder 6a is thickly attached to the land 2a in this way, when the electrode 4 of the electronic component 3 is soldered with the heater block 5, the molten solder flows out toward the land 2b, causing a short circuit between the lands 2a and 2b. occurs.
本発明はこのような従来の欠点を解消するよう
にしたものであり、以下その一実施例について第
４図〜第６図を用いて説明する。 The present invention is intended to eliminate such conventional drawbacks, and one embodiment thereof will be described below with reference to FIGS. 4 to 6.
これらの第４図〜第６図において、第１図〜第
３図の従来の印刷配線基板装置と同一構成部分に
は同一番号が附してあり、本発明は印刷配線基板
１に複数個隣接して設けられた電子部品の接続用
ランド２ａ，２ｂ，２ｃ……のうち、最初に半田
噴上げ部７に突入するランド２ａを２a1と２a2の
２つの分割ランドで形成したものである。 4 to 6, the same components as those of the conventional printed wiring board device shown in FIGS. Among the lands 2a, 2b, 2c, etc. for connection of electronic components provided as above, the land 2a that first plunges into the solder spouting part 7 is formed by two divided lands, 2a 1 and 2a 2 . .
このように、半田噴上げ部７に最初に突入する
ランド２ａを分割形成することにより、第５図に
示すように半田附着作業を行なつた場合、分割ラ
ンド２a1，２a2の面積が小さいため、これらに附
着する半田６a1，６a2の量は少なくなる。 By dividing the land 2a that first enters the solder spouting portion 7 in this way, the area of the divided lands 2a 1 and 2a 2 is small when soldering work is performed as shown in FIG. Therefore, the amount of solder 6a 1 and 6a 2 attached to these is reduced.
そして、半田附着がなされた印刷配線基板１に
電子部品３を載せてその電極４を接続するために
第６図に示すようにヒータブロツク５にて各ラン
ドに附着している半田を溶融させた時、特にラン
ド２ａの分割ランド２a1，２a2に附着している半
田６a1，６a2の余り分は分割ランド２a1，２a2間
の空所８ａ，８ｂに流れ出て行き、このためラン
ド２ｂと短絡するようなことがなくなるものであ
る。なお、ランド２ａの分割数は２つに限らず、
さらに多くの数に分割しても同様であり、またソ
ルダーレジストをランド２ａの上に部分的に塗布
し、これによつて分割ランドを形成するようにし
ても同様である。 Then, in order to place the electronic component 3 on the soldered printed wiring board 1 and connect the electrodes 4, the solder attached to each land was melted by the heater block 5, as shown in FIG. In particular, the surplus solder 6a 1 and 6a 2 adhering to the divided lands 2a 1 and 2a 2 of the land 2a flows into the spaces 8a and 8b between the divided lands 2a 1 and 2a 2, and therefore This eliminates short circuits with 2b. Note that the number of divisions of land 2a is not limited to two,
The same effect can be obtained even if the land 2a is divided into a larger number of parts, and the same effect can be obtained even if a solder resist is partially applied onto the land 2a to form divided lands.
本発明は以上のように印刷配線基板に電子部品
の電極を接続するための導箔からなる複数個のラ
ンドを設け、前記複数個のランドのうち半田附着
時に半田噴上げ部に最初に突入するランドを複数
個に分割形成したものであり、これによれば各ラ
ンドに半田を附着させた時、先行するランドを分
割させたことによりそのランドに附着する半田の
量は少なくなり、しかも電子部品の電極接続時に
は分割ランドの余剰半田はその分割ランド間の空
所が吸収部となるため、ランド間の短絡を起すよ
うなことがなくなり、品質の良好な印刷配線基板
装置が得られるもので、その効果は大である。 As described above, the present invention provides a plurality of lands made of conductive foil for connecting electrodes of electronic components to a printed wiring board, and among the plurality of lands, one of the lands enters the solder spouting part first during solder application. A land is formed by dividing it into multiple parts. According to this method, when solder is applied to each land, the amount of solder applied to that land is reduced because the preceding land is divided. When the electrodes are connected, the spaces between the divided lands act as absorbers for excess solder on the divided lands, so short circuits between the lands do not occur, and a printed wiring board device of good quality can be obtained. The effect is huge.
第１図は従来の印刷配線基板への電子部品の取
付け前の状態を示す斜視図、第２図は同電子部品
の電極の接続状態を示す概略図、第３図ａ，ｂ，
ｃは従来の印刷配線基板のランドへの半田附着工
程を示す図、第４図は本発明の一実施例の印刷配
線基板の斜視図、第５図は同ランドへの半田附着
状態を示す図、第６図は同電子部品の接続状態を
示す概略図である。
１……印刷配線基板、２，２ａ，２ｂ，２ｃ…
…ランド、２a1，２a2……分割ランド、３……電
子部品、４……電極、６，６ａ，６a1，６a2，６
ｂ，６ｃ……半田、７……半田噴上げ部、８ａ，
８ｂ……空所。
Fig. 1 is a perspective view showing the state before electronic components are attached to a conventional printed wiring board, Fig. 2 is a schematic diagram showing the connection state of the electrodes of the electronic parts, and Figs. 3 a, b,
FIG. 4 is a perspective view of a printed wiring board according to an embodiment of the present invention, and FIG. 5 is a diagram showing a state of solder being applied to the lands of a conventional printed wiring board. , FIG. 6 is a schematic diagram showing the connection state of the electronic components. 1...Printed wiring board, 2, 2a, 2b, 2c...
... Land, 2a 1 , 2a 2 ... Divided land, 3 ... Electronic component, 4 ... Electrode, 6, 6a, 6a 1 , 6a 2 , 6
b, 6c...Solder, 7...Solder spouting part, 8a,
8b... Blank space.
Claims (1)
めの導箔からなる複数個のランドを設け、前記複
数個のランドのうち半田附着時に半田噴上げ部に
最初に突入するランドを複数個に分割形成したこ
とを特徴とする印刷配線基板装置。1. A printed wiring board is provided with a plurality of lands made of conductive foil for connecting electrodes of electronic components, and among the plurality of lands, the land that first enters the solder spouting part during solder application is divided into a plurality of lands. A printed wiring board device characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13112281A JPS5832486A (en) | 1981-08-20 | 1981-08-20 | Printed circuit board device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13112281A JPS5832486A (en) | 1981-08-20 | 1981-08-20 | Printed circuit board device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5832486A JPS5832486A (en) | 1983-02-25 |
| JPS6252959B2 true JPS6252959B2 (en) | 1987-11-07 |
Family
ID=15050495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13112281A Granted JPS5832486A (en) | 1981-08-20 | 1981-08-20 | Printed circuit board device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5832486A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03148883A (en) * | 1988-09-30 | 1991-06-25 | Rockwell Internatl Corp | Piezoelectric actuator |
-
1981
- 1981-08-20 JP JP13112281A patent/JPS5832486A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03148883A (en) * | 1988-09-30 | 1991-06-25 | Rockwell Internatl Corp | Piezoelectric actuator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5832486A (en) | 1983-02-25 |
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