JPS6252339B2 - - Google Patents

Info

Publication number
JPS6252339B2
JPS6252339B2 JP56019351A JP1935181A JPS6252339B2 JP S6252339 B2 JPS6252339 B2 JP S6252339B2 JP 56019351 A JP56019351 A JP 56019351A JP 1935181 A JP1935181 A JP 1935181A JP S6252339 B2 JPS6252339 B2 JP S6252339B2
Authority
JP
Japan
Prior art keywords
address
register
malfunction
buffer
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56019351A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57133598A (en
Inventor
Akyoshi Kajama
Kazuyuki Shimizu
Hideo Iyota
Kyoshi Oguri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP56019351A priority Critical patent/JPS57133598A/ja
Publication of JPS57133598A publication Critical patent/JPS57133598A/ja
Publication of JPS6252339B2 publication Critical patent/JPS6252339B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP56019351A 1981-02-10 1981-02-10 System for write control of erroneous operation address Granted JPS57133598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56019351A JPS57133598A (en) 1981-02-10 1981-02-10 System for write control of erroneous operation address

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56019351A JPS57133598A (en) 1981-02-10 1981-02-10 System for write control of erroneous operation address

Publications (2)

Publication Number Publication Date
JPS57133598A JPS57133598A (en) 1982-08-18
JPS6252339B2 true JPS6252339B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1987-11-05

Family

ID=11996961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56019351A Granted JPS57133598A (en) 1981-02-10 1981-02-10 System for write control of erroneous operation address

Country Status (1)

Country Link
JP (1) JPS57133598A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3332601A1 (de) * 1983-09-09 1985-03-28 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum registrieren von adressen von einen fehlerhaften speicherinhalt aufweisenden speicherzellen
CN114780283B (zh) * 2022-06-20 2022-11-01 新华三信息技术有限公司 一种故障处理的方法及装置

Also Published As

Publication number Publication date
JPS57133598A (en) 1982-08-18

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