JPS6251314A - Signal detection system - Google Patents

Abstract

PURPOSE:To detect simply and surely the absence of a signal with high reliability by not using a common clock source but using an output clock of a clock extraction circuit corresponding to an output interface circuit. CONSTITUTION:A signal reproducing circuit consists of a clock extraction circuit 9 and a D flip-flop 10, a clock signal CLK is extracted from an input signal DATA having waveform distortion and the clock signal subjected to phase control is obtained by applying phase control to a PLL circuit and the waveform distortion is eliminated by using the D flip-flop 10 to cancel the input signal DATA while using the clock and the result is sent to a post-device. On the other hand, an input signal detection circuit 6 detects the presence of the input signal DATA and when it is present, the input signal DATA from the exchange switch 5 is sent as it is to the signal reproducing circuit via a changeover circuit 7, but when no input signal DATA exists, an idle signal from a common idle source 8 is sent to the signal reproducing circuit via a changeover circuit 7.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a signal detection method that easily detects the presence or absence of an input signal pulse, and is particularly suitable when a signal regeneration circuit is provided for an output line. The present invention relates to a signal detection method.

[Background of the invention]

In a digital communication system, when the communication path of an exchange is open, an idle signal with a certain specific pattern is sent to the downstream device in order to notify the downstream device of this "no connection" status. It looks like this.

In this case, the presence or absence of an input signal is detected, and if there is an input signal, this input signal is transmitted as is to the downstream device, while if there is no input signal, the above-mentioned idle signal is sent to the downstream device. It is necessary to control the switching side.

As a conventional method for detecting the presence or absence of this input signal, a pulse detection circuit disclosed in Japanese Patent Publication No. 59-17893, for example, is known.

FIG. 3 shows the application of the pulse detection circuit to an exchange. According to this, a pulse detection circuit is provided corresponding to the line, and basically consists of a D-type flip-flop 1.2 and an inverter 32. That is, the D-type flip 70 tube 1 always has an H level signal applied to its data terminal, and this H level signal is set at the rising edge of the input signal DATA applied to the clock terminal C, while the clear terminal It is reset when the inverted clock signal CLK applied to R is at L level. In addition, the other D-type flip-flop 70 block 2 has a D-type flip-flop 10 set output Q to the data terminal.
This signal is set at the rising edge of the clock signal CLK applied to the clock terminal C, and is output as the pulse detection signal DET.

Next, the operation will be explained with reference to FIG. 4. When the input signal DATA arrives, the D-type flip-flop 1 is set at the rising edge of the input signal DATA, and its set output signal becomes H level. Thereafter, the D-type flip-flop 2 receives the H level at the rising edge of the clock signal CLK, and its set output signal becomes H level. Furthermore, after this, the set output signal of the D-type flip-flop 1 is cleared and becomes the L level when the inverted clock signal from the inverter 3 delayed by the time td is at the L level. At the next rising edge of the input signal DATA, the D-type flip-flop 1 is set at the rising edge of the input signal DATA in the same manner as before, but after the D-type flip-flop 2 is set at the rising edge of the clock signal CLK, the D-type flip-flop 2 is set at the rising edge of the clock signal CLK. Type clip-flop 1 is the one that is to be reset.

In this way, when the input signal DATA exists, the D-type flip-flop 2 maintains the set state. However, if the input signal DATA ceases to exist, the D-type flip-flop 1 is no longer set and remains in a reset state, and as a result, the D-type flip-flop 2 is also no longer set.

That is, it is known that the input signal DATA does not exist since the D-type flip-flop 2 has been reset.

As described above, the conventional method can easily detect the presence or absence of an input signal, but there is a problem in that a dedicated clock is required for signal detection. In addition, when there are many such detection circuits,

The problem is that the lock is common, and if the clock source fails, the entire detection circuit becomes unusable.

[Purpose of the invention]

An object of the present invention is to solve the drawbacks of the conventional method, and to provide a signal detection method that can easily detect the presence or absence of an input signal without requiring a common lock source when the presence or absence of an input signal is detected for each output line. There is a method to provide.

[Summary of the invention]

For this purpose, the present invention focuses on the fact that when a signal regeneration circuit is provided for an output line, a clock signal can be obtained from the signal regeneration circuit, and the input signal shifts to a specific level, for example, L level. The time during which the input signal remains at L level is measured by counting the clock signal, and the absence of the input signal is detected when the clock signal is counted for a certain period of time or more.

[Embodiments of the invention]

Hereinafter, an example of the case where the present invention is applied to an output interface section in a switching system will be taken as shown in FIG.

This will be explained with reference to FIG.

FIG. 1 mainly shows the output interface section available in the exchange, and the line-compatible output interface section is composed of a signal reproducing circuit, an input signal detection circuit 6, and a switching circuit 7. The signal regeneration circuit is composed of a clock extraction circuit 9 and a D-type flip-flop 10, and receives an input signal with waveform distortion from the exchange switch 5.
□By extracting the clock from DATA and controlling the phase of the PLL circuit, a phase-controlled clock signal CLK is obtained, and with this clock, the input signal DATAft
By resetting the D iJm flip-flop 10, the waveform distortion is removed and the signal is sent to the subsequent device.

On the other hand, the input signal detection circuit 6 detects the presence or absence of the input signal DATA, and if the input signal DATA is present, the switch is replaced.
The input signal DATA from the switch 5 is passed through the switching circuit 7.
: The input signal is transmitted as is to the signal reproducing circuit, but the input signal
In the case of no iDATA, the idle signal from the common idle source 8 is sent to the signal reproducing circuit via the switching circuit 7.

In this way, input signal detection circuit 6C: input signal DATA
The present invention is characterized in that its presence or absence is detected based on the clock signal CLK from the clock extraction circuit 9 in the output interface.

In the following, this input signal detection circuit will be explained in detail. For example, it is configured as a presettable down counter, and when an H level signal is applied to its mode select terminal S, the value specified by equation ~D is set. is the set output Q. ~Q, while its terminal S
When the L level njT is added to the clock extraction circuit 9, the output value thereof is decremented in synchronization with the rise of the clock signal CLK from the clock extraction circuit 9. When the value becomes zero, a borrow signal Bout is output, and this borrow signal Bout causes the switching circuit 7 to send out the idle signal from the idle source 8 to the signal reproducing circuit. In this example, a down counter is used as the input signal detection circuit, but it goes without saying that a normal counter that can be preset may also be used.

Next, the operation of the circuit constructed as described above will be explained with reference to FIG. 2. In this example, it is assumed that the input signal is in the αX code format. For the X code format, if the signal is "0", the level is "J", and if the signal is "1", the level is rHHJ or rLLJ (the signal state is opposite to the previous "1" state (multiplication VLL)). It is a sign. Note that a bit indicating a frame signal is inserted using a frame violation method, but in this case, the above-mentioned conversion rule is broken and the previous "1" state is maintained. In addition, in this example, as the input signal DATA, r 0
The case of IIFOOJ is shown.

When the input signal DATA is at the H level, it is the preset mode, and every time the preset mode is entered, the 8-L,
The value of "6" of D, -H, D, -H, Da-L; started to be taken into the DOW/counter.

Furthermore, since the countdown mode is entered when the input signal DATA is at the L level, the countdown is started with an initial value of 6 each time this mode is entered. By the way, since the input signal DATA in this example is in the αX code format, when the input signal DATA is present, the period in which the signal level is at the L level is always continuous for a maximum of five clocks. Therefore, in the case of signal heat, it is a case where the countdown is over 6 clocks, and even at the 6th clock, ~Q1 is all at L level, and it is determined that there is no input signal by the output of the borrow signal, and the switching circuit 7 is controlled. Accordingly, the idle signal is sent to the signal regeneration circuit.

〔Effect of the invention〕

As described above, according to the present invention, the above-mentioned problem can be solved by using the output clock of the clock extraction circuit corresponding to the output interface circuit without using a common clock source. This has the effect of detecting the absence of a signal.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an example of an output interface section in a switchboard when the present invention is applied to the output interface section, FIG. 2 is a diagram for explaining its operation, and FIG. FIG. 4, which is a diagram showing the configuration of a conventional pulse detection circuit, is a diagram for explaining its operation. 6... Input signal detection circuit, 7... Switching circuit, 9
...Clock extraction circuit, 10...D type flip 70 tube.

Claims (1)

[Claims] 1. A method for detecting the presence or absence of an input signal in a device that is equipped with a circuit that reproduces an input signal using a clock signal extracted from the signal corresponding to the output line, and detects the presence or absence of an input signal whenever the input signal shifts to a specific level. A signal detection method characterized in that the time that the input signal remains at the level is measured by counting a clock signal from a signal reproducing circuit, and the absence of an input signal is detected when the measured time exceeds a certain level.