JPS6249733B2 - - Google Patents

Info

Publication number
JPS6249733B2
JPS6249733B2 JP12722782A JP12722782A JPS6249733B2 JP S6249733 B2 JPS6249733 B2 JP S6249733B2 JP 12722782 A JP12722782 A JP 12722782A JP 12722782 A JP12722782 A JP 12722782A JP S6249733 B2 JPS6249733 B2 JP S6249733B2
Authority
JP
Japan
Prior art keywords
single crystal
nitride film
crystal silicon
silicon
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP12722782A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5918657A (ja
Inventor
Akinobu Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JIDO KEISOKU GIJUTSU KENKYUKUMIAI
Original Assignee
JIDO KEISOKU GIJUTSU KENKYUKUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JIDO KEISOKU GIJUTSU KENKYUKUMIAI filed Critical JIDO KEISOKU GIJUTSU KENKYUKUMIAI
Priority to JP12722782A priority Critical patent/JPS5918657A/ja
Publication of JPS5918657A publication Critical patent/JPS5918657A/ja
Publication of JPS6249733B2 publication Critical patent/JPS6249733B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
JP12722782A 1982-07-21 1982-07-21 集積回路用基板の製造方法 Granted JPS5918657A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12722782A JPS5918657A (ja) 1982-07-21 1982-07-21 集積回路用基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12722782A JPS5918657A (ja) 1982-07-21 1982-07-21 集積回路用基板の製造方法

Publications (2)

Publication Number Publication Date
JPS5918657A JPS5918657A (ja) 1984-01-31
JPS6249733B2 true JPS6249733B2 (enrdf_load_stackoverflow) 1987-10-21

Family

ID=14954873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12722782A Granted JPS5918657A (ja) 1982-07-21 1982-07-21 集積回路用基板の製造方法

Country Status (1)

Country Link
JP (1) JPS5918657A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0553856B1 (en) * 1992-01-31 2002-04-17 Canon Kabushiki Kaisha Method of preparing a semiconductor substrate

Also Published As

Publication number Publication date
JPS5918657A (ja) 1984-01-31

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