JPS6249625A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form highly precise grooves by dividing multilayer semiconductor layers into semiconductor blocks by cleaving the semiconductor layers perpendicularly to the growth surface of the semiconductor layers, by forming a substrate on one cleaved surface and by etching from the other cleaved surface. CONSTITUTION:A multilayer semiconductor layer is formed by alternately growing a GaAs crystal layer 11 and a Ga0.7Al0.3As mixed crystal layer 12 on a GaAs substrate 10 by molecular beam epitaxy, vapor phase epitaxy or liquid phase epitaxy. Then, the semiconductor layer is cleaved perpendicularly to the growth surface an the GaAs substrate 14 for a semiconductor device is grown by vapor phase or liquid phase epitaxy on one cleaved surface 13 of a cleaved semiconductor layer block. Then, a groove construction is obtained by removing the appropriate depth or all of part of the Ga0.7Al0.3As mixed crystal layer 12 by selective etching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device having a groove structure.

[Conventional technology]

Figure 4 (13-(c) is, for example, Yamaguchi
.

T, *tal t Symposium on VL
SI T@chnology Digest of T
This is a diagram for explaining the conventional method of processing a trench structure when trench isolation 1 is used as shown in 26 (1983).
There are ten silicon crystal layers, 2 is a p-type silicon crystal layer, 3 is a silicon oxide film, and 4 is a groove. The process will be explained below.

First, as shown in FIG. 4(a)K, a Kp type silicon crystal layer 2 was formed on the 5Kp ten-type silicon crystal layer 1, and then the p-type silicon crystal layer 2 was thermally oxidized by 1rrt'.

A silicon oxide film 3 with a thickness of 1.2 μm is formed.

Next, the top is covered with photoresist, exposed and developed through a mask, and a 3m pattern is formed on the photoresist (
Ru. By performing chemical etching using the pattern, for example, 2 μm as shown in FIG.
Only the portion of the silicon oxide film 3 where the m-groove is to be dug is removed. Next, reactive ion etching was performed using a mixed gas of KCF4 and oxygen.

A 4ft groove is formed as shown in FIG. 4(c)K. Groove 4
The depth is 6 μm. The silicon oxide film 3, which serves as a mask when performing reactive ion etching, had a thickness of 1.2 μm before ion etching, but the thickness decreased by 0.4 μm after etching.

FIGS. 5(a) to 5(d) are diagrams for explaining the conventional method of processing a groove structure when used as a stepped base contour structure of PBT, in which 5 is an n-type silicon crystal substrate, 6 is an n-type In the silicon crystal layer, 1 is an n-type ion implantation layer, 8 is a groove, 9 is a collector electrode, and 9b is a base electrode. C
,0-Bozler*Proc*IEEE 70.
(1982 and Rathman* I ED
M Tach, Dig, (1982) 650 VC is G
Although there are examples using aAs and St, here we will describe the process using silicon crystal.

First, a Kn type silicon crystal layer 6 is formed on a Vcn+m silicon crystal substrate 5 as shown in FIG.

Next, as shown in @5 (b) K, the nu silicon crystal layer 6
Ion implantation is performed on the upper blade of the n-type ion implantation layer 1.
form. Next, as shown in FIG. 5(c)K, a fine groove structure pattern with a period of 3200A is formed using KX@X-ray phosphorography, and groove portions 81 are formed by reactive ion etching.
Thereafter, as shown in FIG. 5(d), tungsten Yt beam evaporation is performed to form a collector electrode 9a and a base electrode 9b.

As mentioned above, the 1-reactive ion etching method is used as a technique to form a groove structure on a semiconductor crystal.
In this reactive ion etching method, a mask is made of a material that is relatively resistant to etching, such as silicon oxide, and a pattern is formed. The grooves are formed by utilizing the selectivity of the mask material.Photolithography is used to transfer the pattern on the mask material, and ultraviolet light or XIm is used depending on the pattern accuracy. The examples in FIGS. 5(b), 5(e) and 5(d) are cases where optical and X-ray phosphorography are used, respectively.

Figure 4 (illustration, (b), (c) The rsnl1 section 4 shown in K can be used as trench isolation in integrated circuits, grooves for trench capacitors1, and isolation bays for CODs arranged in parallel at high density. Figure 5 (a), (b)
.

(c) and (d) The rsrlj section 8 shown in VC is an example of being used as a stepped base collector structure of PBT.
FIG. 5 (The phantom n-type silicon crystal layer 6 acts as a base region, the n-type silicon crystal substrate 5 is an emitter region, and an emitter electrode (not shown) is made into ohmic contact therebelow. The n-type ion implantation layer 7 formed by impurity implantation shown in FIG. Also, the tungsten thin film shown in FIG. However, the number of electrons that reach the collector region changes depending on the potential change of the base electrode along the way.

[Problem that the invention seeks to solve]

In the conventional semiconductor device manufacturing method using reactive ion etching as described above, when attempting to dig a deep trench of several μm or more, the mask material is also etched due to insufficient etching selectivity. In addition, the etching anisotropy is insufficient, and lateral etching occurs, making it difficult to form grooves with high precision. In addition, phosphorography has limitations in pattern accuracy due to the wavelength of the light or X-rays used, and also has the problem that the precision equipment, resist, and mask must be used during the daytime.

The present invention has been made to solve these problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can form grooves with high precision exceeding the limits of VcXMA lithography without using phosphorography.

Another object of the present invention is to provide a method for manufacturing a semiconductor device, in which, in addition to the above-mentioned objects, it is possible to easily form a groove portion having a complicated shape with high precision.

[Means for solving problems]

A method for manufacturing a semiconductor device according to the present invention includes alternately forming a first semiconductor layer and a second semiconductor layer on a substrate for growing a crystal layer.
) A step of forming a multi-layered semiconductor layer with a length of 7 degrees Celsius, a step of dividing the semiconductor layer by cleaving the multi-layered semiconductor layer perpendicularly to its growth surface, and one of the semiconductor layer blocks. This method includes the steps of forming a substrate for a semiconductor device on the cleavage plane of the second semiconductor layer, and performing V-selective etching only on the second semiconductor layer from the other cleavage plane of the semiconductor layer boot stack.

Further, in a method for manufacturing a semiconductor device according to another aspect of the present invention, a mixed semiconductor layer consisting of a first semiconductor layer and a second semiconductor layer is selected in a predetermined pattern by molecular beam epitaxy on a substrate for crystal layer growth. cleavage of this mixed semiconductor layer perpendicularly to the growth plane to divide it into semiconductor mixed layer blocks; The method includes a step of selectively etching only the semiconductor layer.

[Effect]

In this invention, the first
and a second semiconductor layer from a multilayer semiconductor layer consisting of a second semiconductor layer and a second semiconductor layer.
A trench is formed by selectively etching only the semiconductor layer.

In another aspect of the present invention, the groove portion is formed by selectively etching only the second semiconductor layer from the semiconductor mixed layer consisting of the first semiconductor layer and the second semiconductor layer.

〔Example〕

FIGS. 1(a) to 1(d) are diagrams for explaining the principle of the method for manufacturing a semiconductor device of the present invention, in which 10 is a GaAs substrate for growing a crystal layer, 11 is a GaAs crystal that is a first semiconductor layer. layer, 12 is the second semiconductor layer Ga o,y Al
6. , A s mixed crystal layer, 13 is a cleavage plane, and 14 is a GaAs substrate for a semiconductor device. The steps will be explained below.

First, as shown in Fig. 1(a), s GaAs
K GaAtz crystal layer 11 and Gao4 on substrate 1a
A l 6. .

The A8 mixed crystal layers 12 are grown alternately to form a multilayer semiconductor layer. Next, as shown in FIG. 1(b), it is separated in a plane perpendicular to the growth surface. Then, as shown in Figure 1(c), 5V
c, one cleavage plane 1 of the cleaved semiconductor layer block
3, GaA for semiconductor devices! 1 substrate 14 is grown by vapor phase or liquid phase epitaxy. Next VC Figure 1 (d
), by selective etching, Ga@,7
A trench structure can be obtained by removing a portion of the A l @J Am mixed crystal layer 12 to an excessive depth or completely.

Note that the GaAs substrate 1G was replaced with a silicon single crystal.

A silicon single crystal having a groove structure can also be obtained by selectively etching GaP using a mixed solution of hydrofluoric acid and silver nitrate, etc., using alternately grown semiconductor t-silicon and GaP K refill.

The trench structure obtained by this 5K process is used for trench isolation of semiconductor integrated circuits, trench capacitors, trench isolation of COD, trench portions of PBTQ structures, etc.

FIGS. 2(a) to 2(f) are diagrams for explaining the steps of an embodiment of the method for manufacturing a semiconductor device of the present invention, in which 15 is an n-type GaAs substrate for crystal layer growth, 16 is an n-type GaAs substrate, and 16 is an n-type GaAs substrate for crystal layer growth; The crystal layer 11 is an n-type Gaa, yAlo, xA8 mixed crystal layer.

18 is a cleavage plane, 19 is an n-type GaAa crystal layer, 20 is an n-medium-sized GaAs substrate for semiconductor devices, 21 is an n-base ion implantation layer, 22 is a groove, 23a is a contour electrode, 2
3b is a pace electrode. The steps will be explained below.

First, as shown in FIG. 2(a), a Kn-type GaAg crystal layer 16 and an n''mGaO
, tALo, *As m crystal layers are alternately grown 200 times with a period of 1ryt3zooX to form a multi-j1i semiconductor layer. Next, as shown in FIG. 2(b) K, cleavage is performed in a plane perpendicular to the growth plane. Next, as shown in FIG. 2(C)K, the −1 cleavage plane 1 of the cleaved semiconductor layer block is
8, an n-type GaAm crystal layer 19° and an n-medium-type GaAs substrate 20 for a semiconductor device are successively grown. Next, Figure 2 (
d) Diffusion or ion implantation of tellurium etc. from the t-A plane at 5K as indicated by Vc and heat treatment [nm GaAl crystal layer 16]
Then, an n medium ion implantation layer 21 is formed on the surface of the n type G by A lo, s A@ mixed crystal layer 17 . Next, as shown in FIG. 2(e) VC, 5 selection etching is performed.
The reduced am0.7 Alo,s As mixed crystal layer IT' is completely removed. After forming the continuous groove portion 22 in this way, as shown in FIG. 2(f)K, the tungsten tt
By forming the collector electrode 23a and the pace electrode 23b by electron beam evaporation, a stepped collector/base structure of PBT is obtained.

Note that GaP/Si is used as a substrate for crystal layer growth.

BP/St, S L in case of CaFz/St system
, G&+hdklo, and sAa/GaA1 systems, GaAs is used, and the thickness of the growth when these are mutually grown is determined by the width of the grooves to be formed and the distance between the grooves.

The precision when molecular beam epitaxy is used as the growth method is about 1 OX, and the precision when vapor phase or liquid phase epitaxy such as organometallic CVD method is used is about 0.01μ.

3(a) to 3(c) are diagrams for explaining in detail another invention of the method for manufacturing a semiconductor device according to the present invention, and FIG.
) to (d), the same symbols indicate the same parts.

The steps for forming the intersecting groove structure will be described below.

First, we opened and closed the shank of a full miniwam wire using a molecular beam as shown in Fig. 3(a).
KGaA@crystal layer 11 on substrate 10 and Ga,...yA
A mixed layer of the lanAs mixed crystal layer 12 is grown while being selectively formed in a predetermined pattern. Next, Fig. 3(b) K
As shown in 5, it is formed in a plane perpendicular to the growth plane and separates the rS mixed layer. Then the separated mixed layer block -
Selective etching is performed on the N-face 13 of section 1, and Ga
o,t Alo,3 A! By removing the l mixed crystal layer 12, a groove structure as shown in FIG. 3C can be obtained.

In other words, in this method, even if the Gao, yAlo, and sAs mixed crystal layers 12 are removed together, the GaA1 crystal layer 11 remains at the bottom of the groove, so there is no need to form a substrate for a semiconductor device.

〔Effect of the invention〕

As explained above, this invention provides a crystal growth substrate for crystal growth.
(c) A first semiconductor layer and a second semiconductor layer (t) are grown alternately to form a multilayer semiconductor layer, and this multilayer semiconductor layer is cleaved perpendicularly to the growth surface to divide it into semiconductor layer blocks. After forming a substrate for a semiconductor device on the −1 cleavage plane of this semiconductor layer block, only the second semiconductor layer is selectively ftA selectively formed on the other cleavage plane of the semiconductor layer block.
A groove is formed in the second semiconductor layer by etching, but the width of the groove and the distance between the grooves can be determined by the thickness K of the first and second semiconductor layers, so phosphorography is not used. This has the effect that grooves can be formed at high f# degrees.

Another invention of the present invention is to selectively form a semiconductor mixed layer consisting of a semiconductor layer of a busy molecular beam "'Ca1l" and a second semiconductor layer on a substrate for crystal layer growth in a predetermined pattern. This semiconductor mixed layer is grown perpendicularly to the growth plane and divided into semiconductor mixed layer blocks, and then only the second semiconductor layer is cleaved from the -1 cleavage plane of this semiconductor mixed layer block. By selectively etching, a partial VC groove of m2 is formed in the semiconductor layer, but the pattern and position of this groove can be easily set by molecular beam epitaxy, so even complex-shaped grooves can be easily and precisely set. This has the effect that it can be formed.

[Brief explanation of drawings]

8K1 Figures (a) to (d) are diagrams for explaining the principle of the method of manufacturing a semiconductor device of the present invention, and Figures 2 (1 to (f)) are diagrams of an embodiment of the method of manufacturing a semiconductor device of the present invention. 3(a) to 3(c) are diagrams for explaining the process, and FIGS. 3(a) to 3(c) are diagrams for explaining the details of another invention of the semiconductor device of the present invention, and FIGS. 4(a) to 4(c) are diagrams for explaining the conventional semiconductor device. Figures 5(a) to 5(d) are diagrams for explaining a conventional method for processing a groove structure when used as a stepped base/collector structure of PBT. In the figure, 10 is a GaAs substrate for crystal layer growth, 11
is a GaAs crystal layer, 12 is a Gl&0.7 A16. ,A
Il mixed crystal layer, 13 is a cleavage plane, 14 is a G for semiconductor device
It is an aAs substrate. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 2 Figure 3 Figure 4

Claims (2)

[Claims] (1) A step of forming a multilayer semiconductor layer by alternately growing a first semiconductor layer and a second semiconductor layer on a substrate for crystal layer growth, and a step of forming a multilayer semiconductor layer on the growth surface of the multilayer semiconductor layer. vertically cleaving the semiconductor layer into semiconductor layer blocks;
The steps include forming a substrate for a semiconductor device on one cleavage plane of the semiconductor layer block, and selectively etching only the second semiconductor layer from the other cleavage plane of the semiconductor layer block. A method for manufacturing a semiconductor device, characterized in that: (2) a step of selectively forming and growing a semiconductor mixed layer consisting of a first semiconductor layer and a second semiconductor layer in a predetermined pattern by molecular beam epitaxy on a substrate for crystal layer growth; a step of cleaving the semiconductor mixed layer perpendicularly to its growth plane to divide it into semiconductor mixed layer blocks; and a step of etching only the second semiconductor layer from above one cleavage plane of the semiconductor mixed layer block. A method for manufacturing a semiconductor device, comprising: