JPH0786560A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To form the microstructure without fluctuation in sizes at a specified level readily in excellent reproducibility by cutting a mask material layer with a notch as the starting point with the difference in thermal expansions, selectively exposing the surface of a semiconductor substrate, and performing specified processing on the surface of the semiconductor substrate. CONSTITUTION:Notched parts 9 of SiO2 are provided so as to face each other based on the difference in coefficients of thermal expansions in heating and temperature increase in an SiO2 film 8. Then, a semiconductor substrate 7, wherein the notched parts 9 are provided in SiO2, is inserted and set in a MOCVD chamber. The semiconductor substrate 7 is heated. The SiO2 film is cut along the line connecting the corresponding marker patterns 9 by utilizing the difference in the coefficients of thermal expansions of an InP buffer layer 6 and the SiO2 film 8. Thin linear grooves 10 are formed. The surface of the specified region of the InP buffer layer 6 is linearly exposed. Then, a multiplex quantum well structure 11 containing a well layer and a barrier layer is formed at a level of several tens of mum in each linear groove 10. After the SiO2 film 8 is removed, a multiplex quantum well later is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor element, and more particularly, to a method of manufacturing a semiconductor element in which a semiconductor substrate surface is finely masked and the mask is used to perform a required process to form a semiconductor element. Regarding

[0002]

2. Description of the Related Art As is well known, in the manufacture of, for example, an integrated semiconductor device (integrated semiconductor element), fine patterning is essential. In other words, selective etching of fine areas, selective vapor phase growth of minute areas, and selective doping of impurities into minute areas are essential. Achieved by exposing masking. For fine processing of a semiconductor substrate, for example, for forming an ultrafine structure such as a quantum wire, a so-called resist layer is generally exposed to an electron beam to mask it. 4 (a) to 4 (c) schematically show an embodiment for producing (forming) a quantum wire as an example of forming a fine structure. In this case, first, a semiconductor substrate 1 having a multiple quantum well structure is prepared, and an oxide film 2 is formed on the surface of the semiconductor substrate 1 as shown in a sectional view in FIG. A positive resist for electron beam is applied on the surface, and electron beam exposure is performed to form the resist into a fine pattern 3.

Next, using the resist pattern 3 as a mask, the oxide film 2 is dry-etched using a gas such as CF ₄ , and then the surface of the semiconductor substrate 1 is selected using the resist pattern 3 and the oxide film 2 as a mask. To form quantum wires 4 (FIG. 4 (b)). Here, in order to avoid an adverse effect caused by exposing the side surface of the quantum wire 4 formed by the selective etching, as shown in a sectional view in FIG. May be grown (formed) and the quantum wires 4 may be embedded in the semiconductor crystal.

[0004]

By the way, in order for the quantum wire 4 to exert the required quantum effect, the width of the wire is several.
Since the characteristics of the quantum wire 4 are less than 10 nm and the characteristics of the quantum wire 4 are sensitive to the wire width, it is ideally necessary to suppress the width fluctuation on the atomic order. However, the beam diameter of the electron beam used for forming the resist pattern 3 is limited to several nm, and the minimum line width is about 10 nm due to the characteristic limit of the resist, and the fluctuation of the width is caused by the vibration and the fluctuation of the magnetic field. The same degree exists, and it was technically impossible to form the ideal quantum wire 4. in addition,
The oxide film 2 mask used for the selective etching of the semiconductor crystal progresses receding from the side of the resist 3 (side etching) in the process of masking (mask formation) by using the resist 3 as a mask. Due to this, the quantum wires 4 whose sidewalls are vertical cannot be formed by etching. That is, since the etching shape of the surface of the semiconductor substrate 1 lacks anisotropy reflecting the side wall shape of the oxide film 2 mask, the effective quantum thin line width deviates.

As described above, in the conventional microfabrication method generally used in the method of manufacturing a semiconductor element, for example, a quantum wire structure having no width fluctuation is formed with good reproduction at a level of several tens of nm or less. The reality is that is virtually impossible.

The present invention solves the above-mentioned inconvenient problems, and manufactures a semiconductor device having a process capable of easily and reproducibly forming a fine structure having no fluctuation in size and size at a level of several tens nm or less. The purpose is to provide a method.

[0007]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a mask material layer having a thermal expansion coefficient smaller than that of the semiconductor substrate on a semiconductor substrate surface, and the mask. A step of providing a notch serving as a separation starting point of the mask material layer in a required region of the material layer,
A step of heating the semiconductor substrate provided with a notch in the mask material layer to raise the temperature, cutting the mask material layer from the notch as a starting point by a difference in thermal expansion coefficient, and selectively exposing the semiconductor substrate surface; A step of subjecting the linearly exposed semiconductor substrate surface to a required process.

That is, according to the present invention, when mask patterning is performed on the surface of a semiconductor substrate, a mask layer made of a material having a smaller thermal expansion coefficient than that of the semiconductor substrate is coated and formed, and the difference in thermal expansion coefficient when the temperature is increased by heating is skillfully utilized. , The mask layer is linearly separated at a predetermined position to selectively expose the semiconductor substrate surface with a fine width, and the linear exposed surface is subjected to a required manufacturing process such as etching process, impurity implantation process, or vapor phase. The main idea is to grow a semiconductor element with a fine structure.

Further, to mention, in order to linearly separate the mask layer which is likely to receive thermal stress at a predetermined position and selectively expose the semiconductor substrate surface linearly with a fine width, the mask layer is separated (or cracked). A notch (marker pattern) as a starting point of (formation) is provided correspondingly, and by utilizing the difference in coefficient of thermal expansion when heating and heating, the corresponding notches are linearly separated and slits (grooves) are formed. 2) is formed and the side wall functions as a vertical mask pattern, thereby enabling the formation (fabrication) of a fine structure with good reproducibility. The corresponding notch portions (marker patterns) function more effectively as a starting point of separation (or crack formation) by making the surfaces facing each other sharpened. Further, if a sub cutout portion (sub marker pattern) is set along the region (position) where the linearly separated slits (grooves) are formed,
The width of slits (grooves) formed by separating them linearly can be easily controlled. However, if this sub-marker pattern interferes with the subsequent process, it is masked again after the heating and heating process.

As described above, in the present invention, since the linear slits are formed in the mask material layer by utilizing the difference in the coefficient of thermal expansion, it is necessary to select a material having a coefficient of thermal expansion smaller than that of the semiconductor substrate as the mask material. There is. In addition, the temperature of heating and heating for forming the linear slits in the mask material layer, the time (holding time) of maintaining the temperature, etc. are determined by the material and type of the semiconductor substrate or the mask material, the thickness of the mask material layer. However, if the stress distribution of the semiconductor substrate is measured (or confirmed) in advance, more accurate mask patterning can be performed.

[0011]

According to the present invention, which has as its essence the mask patterning utilizing the difference in coefficient of thermal expansion, it is possible to easily form a mask pattern having a fine line width, which cannot be formed by the conventional use such as electron beam exposure. Therefore, it is possible to fabricate a fine structure with high reproducibility and high precision by combining etching, selective growth and the like. For example, in the formation of quantum wires by selective etching, size fluctuations such as line width can be suppressed to the atomic order, and a semiconductor element using the quantum effect can be provided, and the thickness of the mask layer can be adjusted. Alternatively, the width of the thin line can be controlled to the nm order by adjusting the temperature of the semiconductor substrate when forming (manufacturing) the thin line by vapor phase growth or the like.

More specifically, the width of the groove (slit) formed by separating the mask layer is determined by the difference between the coefficient of thermal expansion of the mask material and the coefficient of thermal expansion of the semiconductor substrate, the difference between the mask layer and the semiconductor substrate. Of the semiconductor substrate, the temperature of the semiconductor substrate, the spacing between the corresponding marker patterns, etc., and the temperature of the semiconductor substrate where the grooves (slits) or cracks occur is mainly determined by the strength of the mask material. For example, when the semiconductor substrate is InP and the mask material is SiO ₂ , it is considered that the difference in processing temperature of the semiconductor substrate corresponds to the tensile force.When the SiO ₂ film thickness is 5000 A, cracks occur at 575 ° C or higher. Occurred. Although there is no distortion with the semiconductor substrate at the SiO ₂ film formation temperature, it is considered that when the temperature is returned to room temperature, the SiO ₂ is compressed and the distortion is relaxed.
Further, the reason for forcibly providing the corresponding marker pattern is to form a groove at a predetermined position, the mask material is SiO ₂ , and its thickness is fixed to 10 nm, and the marker pattern interval is 1 to Heat treatment was performed at 600 ℃, changing to 100 μm, and InP was grown at that temperature to a film thickness of 10 nm.
Fig. 1 shows the result of measuring the width with an AFM (atomic force microscope) after removing the iO ₂ film. Marker pattern interval is 1μ
It is shown that a groove with a width of 1 nm order is formed when the thickness is less than m.

[0013]

EXAMPLES Examples of the present invention will be described below with reference to FIGS. 2 (a) to 2 (g) and 3 (a) to 3 (c).

Example 1 This example is a production example of a laser having a multiple quantum well structure based on InGaAsP / InP.

2 (a) to 2 (g) schematically show an embodiment of a manufacturing process of a multi-quantum well laser. First, as shown in a sectional view in FIG. 2 (a), a semiconductor substrate 7 formed by growing (depositing) an n-type InP buffer layer 6 on the surface of the n-type InP substrate 5 is prepared. On the n-type InP buffer layer 6 surface, as shown in cross section in FIG.
A SiO ₂ film 8 having a thickness of 500 nm was formed by a thermal CVD method at ℃. Then, the on SiO ₂ films 8, as shown in plan view in FIG. 2 (c), based on the coefficient of thermal expansion difference at the time of heating temperature increase to be described later, cut away starting point becomes notched portion of the SiO ₂ film 8 (Marker Pattern 9 is provided correspondingly.

Next, the semiconductor substrate 7 having the notch 9 as a starting point of separation in the SiO ₂ film 8 is inserted and set in a MOCVD chamber (not shown), and the semiconductor substrate 7 is removed.
After heating to 00 ° C., the difference in coefficient of thermal expansion between the InP buffer layer 6 and the SiO ₂ film 8 (comparing in terms of linear expansion coefficient, InP: 4.5 × 10 ⁻⁶ ,
SiO _2: 0.54 × 10 ^-6 using the (K ^-1)), pull the SiO ₂ film 8 by thermal expansion of the InP buffer layer 6, along a line connecting the markers pattern 9 the corresponding SiO ₂ film 8 Tear it apart to create a thin linear groove, as shown in the plan view of Figure 2 (d).
10 is formed, and the predetermined region surface of the InP buffer layer 6 is linearly exposed. Here, linear slits (grooves) having a width of 200 nm were formed at intervals of 100 μm between the tips of the corresponding notches 9.

After that, as it is, by the MOCVD method in the same chamber, as shown in an enlarged cross section in FIG. 2 (e), the PL wavelength is 1.55 in the formed linear groove 10. μ
Well layer of m composition InGaAsP, and PL wavelength is 1.1 μm
A multi-quantum well structure 11 containing a barrier layer InGaAsP having the above composition is selectively grown (deposited). After selective growth (film formation) of the multiple quantum well structure (quantum wire structure) 11, the SiO ₂ film 8 functioning as a mask was removed by etching with a mixed solution of ammonium fluoride and hydrofluoric acid (FIG. 2 (f)). ). Then, as shown in a sectional view in FIG. 2 (g), a p-type cladding layer 12 and a contact layer 13 are sequentially grown (deposited) on the surface where the quantum wire structure 11 is formed, and then electrodes are formed on both sides to form multiple layers. A quantum well laser was obtained.

Although the SiO ₂ film 8 is cracked due to the thermal stress due to the non-separation and cracks, the sidewalls are almost vertical and form a groove (a groove is formed). Was never damaged. Since the SiO ₂ film 8 is weak in strength because it is thinner, cracks are likely to occur, and it can be said that the InP buffer layer 6 is not affected at all.

Example 2 This example is an example of a method for manufacturing a high electron mobility transistor (HEMT), and FIGS. 3 (a) to 3 (c) schematically show an embodiment of this manufacturing process. is there. First, the CVD temperature is set on the surface of the semiconductor substrate 14 for high electron mobility transistor (HEMT).
Set the temperature to 400 ° C and set the thickness as shown in the cross section in Figure 3 (a).
A 100 nm SiO ₂ film 15 is formed by a thermal CVD method. Then, the SiO ₂ film 15, as shown in plan view in FIG. 3 (b), based on the coefficient of thermal expansion difference at the time of heating temperature increase to be described later, the cutout portion to be cut away starting point of the SiO ₂ film 15 (a marker Patterns 16 are provided in correspondence with each other, and a sub marker pattern 17 is provided between the corresponding marker patterns 16 forming the pair. Here, Fig. 3 (c)
As shown in plan view, the sub marker pattern 17 is provided along the line connecting the corresponding marker patterns 16 when the SiO ₂ film 15 is torn and a narrow groove 18 having a predetermined width is formed. The predetermined width D is controlled because the interval L (corresponding to the distance between adjacent gates) and the width of the marker pattern 16 can be easily controlled by the groove width W of the sub marker pattern 17.

When the sub marker pattern 17 is located at the center between the gates, D is D = Δα × (ΔT) × (L−W) where Δα is the line between the semiconductor substrate and the SiO ₂ film. The difference in expansion coefficient (SiO ₂ film is smaller), ΔT: Substrate processing temperature difference is almost given. By providing the sub marker pattern 17, even if the interval L of the marker pattern 16 is fixed,
The width D of the groove 18 can be freely changed. For example, if the spacing L between the marker patterns 16 is 500 μm and the width of the sub-marker pattern 17 is 150 μm, when the heat treatment temperature T _{1 is} 500 ° C., the width D of the groove 18 corresponding to the gate width D is 0.1 μm.
A SiO ₂ film 15 having 18 could be formed. Also, using the SiO ₂ film 15 as a mask, reactive ion beam etching is performed on n-GaAs using a mixed gas of chlorine and argon to stop etching on the surface of the HEMT semiconductor substrate (n-AlGaAs) 14. Then, the surface of the n-AlGaAs layer 14 is exposed.
After that, an electrode was formed in the gate region to produce a Schottky junction. The HEMT semiconductor substrate (n-AlGaAs) 14
The etching shape was vertical because the side wall of the SiO ₂ film 15 forming the mask was vertical, and no dimensional deviation was observed even when the gate width was narrowed.

In the above embodiment, an example in which SiO ₂ is used as the mask material has been described, but since the essence of the present invention is to utilize the difference in coefficient of thermal expansion between the semiconductor substrate and the mask material, the coefficient of thermal expansion of the mask material is used. As long as you choose a combination that is smaller than the expansion coefficient of the semiconductor substrate, regardless of the semiconductor substrate and mask material,
The above actions and effects can be obtained. Further, the process after forming the fine groove in the mask layer and performing the required patterning is not limited to etching and selective growth, and various processes such as ion implantation and anodic oxidation can be performed. .

[0022]

According to the method of manufacturing a semiconductor device according to the present invention, since a fine structure having no fluctuation in size and size of several tens nm level or less can be controlled by atomic order, a semiconductor device utilizing, for example, a quantum effect is used. Higher performance of (semiconductor device) can be realized.

[Brief description of drawings]

FIG. 1 is a characteristic diagram showing an example of a relationship between corresponding marker pattern intervals and a width of a mask groove formed in a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 schematically shows an embodiment of a method for manufacturing a semiconductor device according to the present invention, in which (a) is a cross-sectional view of a semiconductor substrate used and (b) is a cross-section in a state where a mask material layer is provided. Figure, (c)
Is a plan view of a state where a marker pattern is provided on the mask material layer, (d) is a plan view of a state where a linear separation portion (groove) is provided between the corresponding marker patterns, and (e) is a linear exposure Enlarged cross-sectional view of the state in which the multiple quantum well structure is provided on the surface of the semiconductor substrate, (f) is a cross-sectional view of the quantum wire exposed by removing the mask material layer, (g) Embedding the quantum wire with a cladding layer etc. Cross-sectional view in the open state.

FIG. 3 schematically shows an embodiment of another method for manufacturing a semiconductor device according to the present invention, in which (a) is a cross-sectional view of a semiconductor substrate provided with a mask material layer, and (b) is a mask material layer. FIG. 3 is an enlarged plan view showing a state in which a marker pattern and a sub-marker pattern are provided in FIG. 7, and FIG.

FIG. 4 schematically shows an example of an embodiment of a conventional method for manufacturing a semiconductor device, (a) is a cross-sectional view of a state in which a resist mask is provided on the surface of a semiconductor substrate, and (b) is an etching treatment for multiquantum. A cross-sectional view of a state in which a well structure is provided, and (c) is a cross-sectional view of a state in which a quantum wire is embedded with a cladding layer or the like.

[Explanation of symbols]

1 ... Semiconductor substrate having multiple quantum well structure 2, 8, 15
... oxide film 3 positive resist pattern 4 ... quantum wire 5 ... InP substrate 6 ... buffer layer 7 ... semiconductor substrate 9, 16 ... notch (marker pattern)
10, 18… Linear groove (Linear exposed surface of semiconductor substrate) 11…
Multiple quantum well structure 12 ... Cladding layer 13 ... Contact layer 14 ... HEMT semiconductor substrate 17 ... Sub marker pattern

Claims (1)

[Claims] 1. A step of forming a mask material layer having a coefficient of thermal expansion smaller than that of the semiconductor substrate on a surface of the semiconductor substrate, and a starting point of separation of the mask material layer in a required region of the mask material layer. And a step of providing a notch formed by heating the semiconductor substrate provided with the notch in the mask material layer, starting from the notch due to the difference in coefficient of thermal expansion, the mask material layer is cut, the semiconductor substrate surface A method of manufacturing a semiconductor device, comprising: a step of selectively exposing the semiconductor substrate surface; and a step of subjecting the linearly exposed semiconductor substrate surface to a required process.