KR100250460B1 - Method of manufacturing a silicon quantum wire - Google Patents

Method of manufacturing a silicon quantum wire Download PDF

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KR100250460B1
KR100250460B1 KR1019970047170A KR19970047170A KR100250460B1 KR 100250460 B1 KR100250460 B1 KR 100250460B1 KR 1019970047170 A KR1019970047170 A KR 1019970047170A KR 19970047170 A KR19970047170 A KR 19970047170A KR 100250460 B1 KR100250460 B1 KR 100250460B1
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silicon
layer
silicon nitride
quantum
oxide layer
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KR1019970047170A
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KR19990025505A (en
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박문호
오상철
이성재
박경완
신민철
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정선종
한국전자통신연구원
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

PURPOSE: A method for manufacturing a silicon quantum wire is provided to observe a quantum phenomenon in a high temperature by forming a quantum wire surrounded with a silicon oxide layer and a silicon nitride layer. CONSTITUTION: A silicon nitride layer(4) is formed on an upper portion of a SIMOX(Separation by IMplanted Oxygen) substrate laminated with a silicon substrate(1), the first silicon oxide layer(2), and a silicon layer(3). A selected region of the silicon nitride layer(4) is removed. A part of the silicon layer(3) is removed by using the remaining silicon nitride layer(4) as a shielding layer. The second silicon oxide layer(6) is grown on a side face of the silicon layer(3).

Description

실리콘 양자세선 제조 방법Silicon quantum thin wire manufacturing method

본 발명은 실리콘 양자세선(quantum wire) 제조 방법에 관한 것으로, 특히 실리콘산화층과 실리콘질화층으로 둘러싸인 실리콘 양자세선 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing silicon quantum wires, and more particularly, to a method for producing silicon quantum wires surrounded by a silicon oxide layer and a silicon nitride layer.

기존의 전자빔 리소그라피 방법에 의해 제조된 양자세선은 선폭이 수십 ㎚ 이하의 초미세 구조일 경우 직선성이 우수한 양자세선을 재현성 있게 제조하는 것이 쉽지 않았다. 또한 기존의 양자세선 구조에서는 주로 정전기장을 이용하여 전자를 1 차원 구조로 구속하여 전자 이동에 관한 양자 현상을 연구해 왔다. 그러나 정전기장에 의한 전자 구속은 전자가 점유할 수 있는 에너지 준위의 간격이 좁아서 양자 현상을 관측하기 위해 극저온에서 측정이 요구되었다.The quantum thin wire manufactured by the conventional electron beam lithography method is not easy to reproducibly produce quantum thin wire having excellent linearity when the ultra-fine structure having a line width of several tens of nm or less. In addition, the quantum phenomena related to electron movement have been studied in the conventional quantum thin wire structure by constraining electrons to a one-dimensional structure mainly using an electrostatic field. However, the electron confinement caused by the electrostatic field was measured at cryogenic temperature to observe the quantum phenomena due to the narrow gap of the energy levels occupied by the electron.

따라서 본 발명은 전자빔 리소그라피가 재형성이 있고 직선성이 우수하며 높은 온도에서도 양자 현상의 관측이 가능한 실리콘 양자세선 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing silicon quantum thin lines, in which electron beam lithography has reformation, excellent linearity, and observing quantum phenomena even at high temperatures.

상술한 목적을 달성하기 위한 본 발명은 실리콘 기판, 제 1 실리콘산화층 및 실리콘층의 적층 구조인 시목스(SIMOX) 기판 상부에 실리콘질화층을 형성하는 단계와, 상기 실리콘질화층의 선택된 영역을 제거한 후 잔류된 실리콘질화층을 차단막으로 상기 실리콘층의 일부를 제거하는 단계와, 상기 실리콘층 측면에 제 2 실리콘산화층을 성장시키는 단계로 이루어진 것을 특징으로 한다.The present invention for achieving the above object is a step of forming a silicon nitride layer on top of the SIMOX substrate which is a stacked structure of a silicon substrate, a first silicon oxide layer and a silicon layer, and removing the selected region of the silicon nitride layer After the removal of a portion of the silicon layer using the silicon nitride layer as a blocking film, and growing a second silicon oxide layer on the side of the silicon layer.

도 1(a) 내지 도 1(g)는 본 발명에 따른 실리콘 양자세선의 제조 방법을 설명하기 위한 단면도.1 (a) to 1 (g) are cross-sectional views illustrating a method for manufacturing a silicon quantum thin wire according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

1 : 실리콘 기판 2 : 제 1 실리콘산화층1 silicon substrate 2 first silicon oxide layer

3 : 실리콘층 4 : 실리콘질화층3: silicon layer 4: silicon nitride layer

5 : PMMA 6 : 제 2 실리콘산화층5: PMMA 6: Second Silicon Oxide Layer

첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.

도 1(a) 내지 도 1(g)는 본 발명에 따른 실리콘 양자세선 제조 방법을 설명하기 위한 단면도이다.1 (a) to 1 (g) are cross-sectional views illustrating a method for manufacturing a silicon quantum thin wire according to the present invention.

도 1(a)는 본 발명에 사용된 산소 주입에 의해 분리된 기판, 즉 시목스(Seperation by IMplanted OXygen: 이하 SIMOX라 함) 기판의 단면도로서, 실리콘 기판(1), 수백 ㎚ 두께의 제 1 실리콘산화(SiO2)층(2) 및 수십 ㎚ 두께의 실리콘(Si)층(3)의 적층 구조로 이루어져 있다. 본 발명에서 실리콘층(3)은 양자세선으로 작용하고, 제 1 실리콘산화층(2)은 실리콘 기판(1)과 실리콘층(3)을 분리한다.FIG. 1 (a) is a cross-sectional view of a substrate separated by oxygen injection, ie, a SIMOX (hereinafter referred to as SIMOX) substrate used in the present invention, a silicon substrate 1, a first of several hundred nm thick. It consists of a laminated structure of a silicon oxide (SiO 2 ) layer 2 and a silicon (Si) layer 3 having a thickness of several tens of nm. In the present invention, the silicon layer 3 acts as a quantum thin line, and the first silicon oxide layer 2 separates the silicon substrate 1 and the silicon layer 3.

도 1(b)는 SIMOX 기판의 실리콘층(3) 상부에 저압 화학 기상 증착(Low Pressure Chemical Vapor Deposition: 이하 LPCVD라 함) 방법으로 수십 ㎚ 두께의 실리콘질화(Si3N4)층(4)을 성장한 상태의 단면도이다. 이 실리콘질화층(4)은 양자세선을 형성하기 위한 후속 공정으로 실리콘층(3)의 양측면에 제 2 실리콘산화층(6)을 성장할 때 산소가 확산되는 것을 막아주는 역할을 하며, 본 발명의 핵심이 되는 것이다.FIG. 1 (b) shows a silicon nitride (Si 3 N 4 ) layer 4 having a thickness of several tens nm by a low pressure chemical vapor deposition (LPCVD) method on the silicon layer 3 of the SIMOX substrate. This is a cross-sectional view of the state. This silicon nitride layer 4 serves to prevent oxygen from diffusing when the second silicon oxide layer 6 is grown on both sides of the silicon layer 3 as a subsequent process for forming quantum fine lines. It will be.

도 1(c)는 실리콘질화층(4) 상부에 레지스트인 폴리메틸메타크릴레이트(Polymethylmethacrylate: 이하 PMMA라 함)층(5)을 증착한 후 전자빔 리소그리피 공정을 이용하여 수백 ㎚ 폭의 PMMA층(5)을 형성한 단면도이다.FIG. 1 (c) shows a PMMA layer of several hundred nm width using an electron beam lithography process after depositing a polymethylmethacrylate (PMMA) layer 5 as a resist on the silicon nitride layer 4. It is sectional drawing which formed (5).

도 1(d)는 PMMA층(5)을 차단막으로 사용한 반응성 이온 식각 공정에 의해 실리콘질화층(4)을 제거한 단면도로서, 이렇게하여 양자세선의 폭을 설정할 수 있다.FIG. 1 (d) is a cross-sectional view of the silicon nitride layer 4 removed by a reactive ion etching process using the PMMA layer 5 as a barrier film. Thus, the width of the quantum thin line can be set.

도 1(e)는 PMMA층(5)을 제거한 후 실리콘질화층(4)을 차단막으로 이용한 식각 공정으로 양자세선을 형성할 실리콘층(3)을 수직 방향으로 제거한 단면도이다. 이때 SIMOX 기판의 제 1 실리콘산화층(2)은 수직 방향의 실리콘층(3) 제거에 대한 차단막 역할을 한다.FIG. 1E is a cross-sectional view in which the silicon layer 3 to form quantum thin lines is removed in a vertical direction by an etching process using the silicon nitride layer 4 as a blocking film after removing the PMMA layer 5. At this time, the first silicon oxide layer 2 of the SIMOX substrate serves as a barrier for removing the silicon layer 3 in the vertical direction.

도 1(f)는 실리콘층(3)의 측면에 제 2 실리콘산화층(6)을 열적 산화방법으로 성장한 단면도이다. 이때 실리콘질화층(4)은 산소가 확산되는 것을 막아서 제 2 실리콘산화층(6)의 성장을 억제하여 양자세선의 두께를 일정하게 해 준다. 여기서, 열적 산화의 온도와 시간을 조절하여 측면의 제 2 실리콘산화층(6)의 폭을 증가시켜 양자세선 폭을 수십 ㎚까지 조절 할 수 있다.FIG. 1F is a cross-sectional view of the second silicon oxide layer 6 grown on the side surface of the silicon layer 3 by a thermal oxidation method. At this time, the silicon nitride layer 4 prevents the diffusion of oxygen, thereby inhibiting the growth of the second silicon oxide layer 6, thereby making the thickness of the quantum fine lines constant. Here, the width of the second silicon oxide layer 6 on the side surface may be increased by controlling the temperature and time of thermal oxidation to adjust the quantum thin line width to several tens of nm.

본 발명은 두께와 폭이 수십 ㎚의 양자세선을 재현성 있게 제조할 수 있으므로 높은 온도에서도 양자 현상 관측이 가능하다. 또한 양자세선의 단면을 정사각형 또는 직사각형으로 제조할 수 있으므로 전자의 1 차원적 구속에 의한 양자 현상의 규명을 용이하게 할 수 있어 양자세선 구조에 따른 양자 현상의 상관 관계를 체계적으로 연구할 수 있다. 따라서 상온에서 동작하는 고집적 다기능성의 양자 효과 소자를 구현할 수 있다.According to the present invention, quantum fine wires having a thickness and width of several tens of nm can be reproducibly produced, so that quantum phenomena can be observed even at a high temperature. In addition, since the cross section of the quantum thin lines can be manufactured in a square or a rectangle, it is possible to easily identify the quantum phenomena due to the one-dimensional restraint of electrons, thereby systematically studying the correlation of quantum phenomena according to the quantum thin line structures. Therefore, it is possible to implement a highly integrated multifunctional quantum effect element operating at room temperature.

Claims (3)

실리콘 기판, 제 1 실리콘산화층 및 실리콘층이 적층된 시목스 기판 상부에 실리콘질화층을 형성하는 단계와,Forming a silicon nitride layer on the Simok substrate on which the silicon substrate, the first silicon oxide layer, and the silicon layer are stacked; 상기 실리콘질화층의 선택된 영역을 제거한 후 잔류된 실리콘질화층을 차단막으로 상기 실리콘층의 일부를 제거하는 단계와,Removing the selected region of the silicon nitride layer and removing a portion of the silicon layer using the remaining silicon nitride layer as a blocking film; 상기 실리콘층 측면에 제 2 실리콘산화층을 성장시키는 단계로 이루어진 것을 특징으로 하는 실리콘 양자세선 제조 방법.And growing a second silicon oxide layer on the side of the silicon layer. 제 1 항에 있어서, 상기 실리콘질화막의 선택된 영역은 전자빔 리소그라피 방법으로 패터닝된 폴리메틸메타크릴레이트를 차단막으로 사용한 식각 공정으로 제거하는 것을 특징으로 하는 실리콘 양자세선 제조 방법.The method of claim 1, wherein the selected region of the silicon nitride film is removed by an etching process using a polymethyl methacrylate patterned by an electron beam lithography method as a blocking film. 제 1 항에 있어서, 상기 제 2 실리콘산화층은 열적 산화 방법으로 성장시키는 것을 특징으로 하는 실리콘 양자세선 제조 방법.The method of claim 1, wherein the second silicon oxide layer is grown by a thermal oxidation method.
KR1019970047170A 1997-09-12 1997-09-12 Method of manufacturing a silicon quantum wire KR100250460B1 (en)

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