KR100696870B1 - AFM cantilever having a quantum dot transistor and method for manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantum dot transistor atomic force microscope cantilever and a method for manufacturing the same. The present invention relates to a quantum dot transistor atomic force microscope cantilever and a method of manufacturing the same. The present invention relates to a quantum dot transistor atomic force microscopy cantilever that can be used in a tera-bit probe type information storage device and improves the sensing capability of information while lowering the manufacturing cost.

The object of the invention (a) forming a probe on top of the cantilever support; (b) forming a multi-layered film on top of the cantilever support, forming a pattern twice, and forming a cantilever arm so that the probe is positioned in the channel region of the transistor and the source and drain regions are formed on both inclined surfaces of the probe; (c) applying and ashing a photoresist on the substrate to expose the tip of the probe; (d) forming a metal film on top of the photoresist and removing the photoresist to leave only a metal film on the tip of the probe; (f) depositing a metal point on the tip of the probe; And (g) removing a portion of the cantilever arm to float the cantilever arm.

Accordingly, the quantum dot transistor atomic force microscope cantilever of the present invention and a method for manufacturing the same can be fabricated using a micromachining technique and a semiconductor device fabrication process to produce a pointed probe, and a metal quantum dot is formed at the tip of the probe using a lift-off process. By forming it, it can be used for terabit probe type information storage device and it has the effect of lowering the manufacturing cost while improving the sensing ability of information.

Quantum Dots, Atomic Force, Microscope, Cantilever

Description

AFM cantilever having a quantum dot transistor and method for manufacturing the same             

1A to 1H are partial process diagrams of a method of manufacturing a cantilever for an atomic force microscope according to the present invention.

Figure 2a to 2b is a perspective view of a partial process of the atomic force microscope probe manufacturing method according to the present invention.

3 is a plan view of FIG. 2B.

4A-4E are cross-sectional views taken along line AA ′ of FIG. 3, showing some process diagrams for forming the microchannels after FIG. 2B;

5 is a process diagram in which a source and a drain region are formed in a probe region according to the present invention.

6A to 6D are cross-sectional views for forming a quantum dot according to the present invention.

7A to 7D are cross-sectional views of a cantilever shape forming process according to the present invention.

          <Description of the symbols for the main parts of the drawings>

110,130: silicon layer 120,141,142,151,152: insulating film

131a, 204 probe 153 polysilicon layer

145 dot pattern 150 metal film

140,154,900 photoresist film 157,161 mask pattern

171: channel area 203: channel

210: source 220: drain

The present invention relates to a quantum dot transistor atomic force microscope cantilever and a method of manufacturing the same, and more particularly, to a silicon quantum dot transistor atomic force microscope cantilever, which can maximize measurement sensitivity without using expensive equipment such as ion doping, and It relates to a manufacturing method.

The modern electronics industry is becoming more and more dense and highly integrated. Therefore, a single electron transistor (SET) for addressing such high density and high integration has attracted attention. Single-electron transistors are based on quantization phenomena due to miniaturization of device size. That is, when the existing field effect transistor element is extremely small, the charging energy of the charge becomes larger than the thermal fluctuation, and the drain current can be turned on and off by changing the gate voltage corresponding to one electron. .

The single-electron transistor is formed in a structure using single-electron tunneling by a quantum dot instead of channel formation through a conventional metal oxide semiconductor (MOS). In other words, by forming a quantum dot of several nm size between the source and the drain of both sides, it is possible to find out the number of electrons passing through the quantum dots in the form of several or dozens, so the device power consumption is very low and the sensitivity is very high, and the electron beam Lithography techniques are used to implement the two-dimensional plane.

M.J. Yoo et al. Developed a single-electron transistor in the 1997 Science Journal and measured the surface potential using it. In the case of the single-electron transistor cantilever, the source and drain regions are formed by selective metal deposition on a very sharp optical fiber, and the metal quantum dots are formed several ten nm apart between the source and drain. In the case of the above paper, the manufacturing method is very difficult and has a problem that a large number of probes cannot be made. Therefore, reproduction is difficult in the same way. For this reason, no papers using the probes have been published since their publication.

Korean Patent No. 10-0366701 discloses a cantilever probe in which a field effect transistor structure is formed using micromachining technology. When the cantilever with the source and drain formed is vertically attached to the sample having the insulator, and a voltage is applied to the source, the amount of current flowing through the drain changes according to the charge distribution on the surface of the sample. As a result of measuring the characteristics of the fabricated device, the typical MOS field effect transistor device characteristics were shown, but no surface charge distribution was actually read using this.

L.H. In a paper published in 2001 by Applied Physics Letters, Chen et al., Published a field-effect transistor on a GaAs / AlGaAs heterostructure and measured the surface potential at 4.2 K. In the case of this paper, it is shown that the characteristics at room temperature are much lower than the result of 4.2 K temperature. In addition, there is a problem in that a very small area cannot be measured due to problems on the substrate, a problem in the manufacturing process, and a problem without a sharp tip.

Republic of Korea Patent Publication No. 2003-0041725 was able to increase the sensitivity by reducing the effective channel length between the source and drain by applying a semiconductor device fabrication process to the general micromachining technology. In addition, it is possible to configure an array type in which several cantilevers can exist in one body.

In the case of Republic of Korea Patent Publication No. 2003-0041726 has a pointed tip, it was also easy to produce a parallel cantilever. As a result of measuring the charge distribution on the sample surface using this, resolution of 200 ~ 300 nm was possible, but it is still insufficient for use in the terabit probe type information storage device.

In order to use the terabit probe type information storage device, the tip of the tip must be sharp to meet the terabit scale, and the effective channel length between the source and drain regions must be precisely 100 nm to increase the sensitivity and stability of the device. Should be reduced to Basically, you should be able to create parallel structures.

In the prior art, since the amount of current signal detected at the drain is less than nano amperes, even in amplification, the signal-to-noise ratio is poor and thus it is difficult to measure the ultra-fine surface charge distribution.

Accordingly, the present invention is to solve the problems of the prior art as described above, by applying a micro-machining technique and a semiconductor device fabrication process to produce a pointed tip of the probe and a metal quantum dot on the tip of the probe using a lift-off process SUMMARY OF THE INVENTION An object of the present invention is to provide a quantum dot transistor atomic force microscope cantilever which can be used in a terabit probe type information storage device and which reduces production manufacturing cost while improving information sensing capability.

The object of the present invention is a cantilever support; A cantilever arm positioned on the cantilever support object and one side of which is injured; A probe located at the tip of the cantilever arm; A channel formed in the cantilever arm under the probe; Source and drain formed on both sides of the channel, respectively; And a quantum dot transistor atomic force microscope cantilever comprising a metal dot formed at the tip of the probe.

Another object of the present invention is to form a probe on top of (a) the cantilever support; (b) forming a multi-layered film on top of the cantilever support, forming a pattern twice, and forming a cantilever arm so that the probe is positioned in the channel region of the transistor and the source and drain regions are formed on both inclined surfaces of the probe; (c) applying and ashing photoresist over the substrate to expose the tip of the probe; (d) forming a metal film on top of the photoresist and removing the photoresist to leave only a metal film on the tip of the probe; (f) depositing a metal point on the tip of the probe; And (g) removing a portion of the cantilever arm to float the cantilever arm.

Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

1A to 1H are some process diagrams of a method for manufacturing an atomic force microscope probe according to the present invention. First, as shown in FIG. 1A, a silicon on insulator (SOI) substrate in which a first silicon layer 110, a first insulating layer 120, and a second silicon layer 130 are sequentially stacked. The first upper insulating layer 141 and the first lower insulating layer 142 are formed on the upper and lower portions of the substrate. The insulating films 141 and 142 are formed to a thickness of about 1 μm through, for example, a wet oxidation process using water as a silicon oxide film.

Next, as shown in FIG. 1B, a photoresist film 150 is formed on the first upper insulating film 141, and a pattern for forming a probe through photolithography and dry etching is formed.

Next, as illustrated in FIG. 1C, after the pattern for forming the probe is formed, the photoresist layer formed on the first upper insulating layer 141 is removed. The method of removing the photoresist film is preferably heated at 120 ° C. for at least 10 minutes with H ₂ SO ₄ and H ₂ O ₂ in a ratio of 4: 1, and in addition to the above method, when the photoresist film is not removed, ₂ can be removed by burning the photosensitive film by the Oxygen Plasma method.

1D illustrates a dry etching of the second silicon layer 130 using SF ₆ gas. When the second silicon layer 130 is stacked to a thickness of 4.0 ± 0.5 micrometers (μm), it is preferable to form a probe having a height of 3.6 ± 0.5 micrometers.

In FIG. 1E, the upper first upper insulating layer 141 and the lower first lower insulating layer 142 obtained through the photolithography process are etched. Etching is performed using a wet etching method using a mixture of BHF (Buffered HF) and H ₂ O in a volume ratio of 7: 1. At this time, a probe shape is formed and a cone shape is formed.

The probe shape may be formed in a cone shape and a pyramidal type. The length and size of the cone and pyramid shape vary with the degree of etching, but there is no difference between the two types. The cone shape is formed using a plasma etching method, and the pyramid shape is formed using wet etching. The plasma etching method for forming the cone shape is used in the present invention because of the advantage of uniformly appearing throughout the wafer.

1F and 1G form the second upper insulating layer 131 and the second lower insulating layer 132 to remove the second silicon layer 130 around the probe. Third insulating layers 131 and 132 are formed on the second silicon layer 130 by a wet thermal oxidation method. The second silicon layer 130 around the probe is wet-etched by including the formed second upper insulating layer 131 and the second lower insulating layer 132. Wet etching uses a solution in which BHF and H ₂ O are mixed at a volume ratio of 7: 1. Since the density of the first insulating layer 120 constituting the SOI is higher than that of the second upper insulating layer 131, the first insulating layer is hardly etched during etching. This process may be repeated one or more times until the second silicon layer 130 around the probe is completely removed.

Figure 1g (a) is a shape when the probe is in the form of a cone, Figure 1g (b) is a shape when the probe is in the form of a pyramid. In the process of FIG. 1E, there is no significant difference depending on whether plasma etching or wet etching is used.

FIG. 1H illustrates forming a thermal oxide film (SiO ₂ ) 710 on the second silicon layer 130 on which the probe is formed by a dry thermal oxidation method. At this time, the thickness of the thermal oxide film 710 should be greater than or equal to 100 nm, preferably 100-110 nm.

Figure 2a to 2b is a perspective view of a partial process of the atomic force microscope probe manufacturing method according to the present invention. FIG. 2A illustrates a method of sequentially stacking a second insulating film 151, a third insulating film 152, a polysilicon layer 153, and a photoresist film 154 on the probe and the first insulating film 120. The first mask pattern 157 having a pattern for forming a source and a drain is formed on the polysilicon layer 153 by performing the process. The second insulating film 151 and the third insulating film 152 may be formed of a heterogeneous material, and each of the second insulating film 151 and the third insulating film 152 may be formed of one selected from a silicon nitride film and a tetraethoxysilane (TEOS) oxide film. In an embodiment of the present invention, the second insulating film 151 is formed of a silicon nitride film having a low stress, and the third insulating film 152 is formed of a TEOS oxide film.

FIG. 2B is a mask of a first mask pattern of a cantilever for atomic force microscopy made of the photoresist film, and is etched from the polysilicon layer 153 to the second insulating film 151 to form a nuclear power on the first insulating film 120. The cantilever mask pattern 161 of the microscope cantilever is formed. After the etching process is completed, the photoresist film is removed by an oxygen plasma method. The cantilever mask pattern 161 is used as a mask for injecting impurities to form a source and a drain of a cantilever for an atomic force microscope having a quantum dot transistor.

FIG. 3 is a plan view of FIG. 2B, wherein the cantilever arm mask pattern 161 for atomic force microscope is formed on the second silicon layer 130, and the exposed second silicon layer is present.

4A to 4E are cross-sectional views taken along the line A-A 'of FIG. 3 and show some process diagrams for forming the microchannels of the transistor after FIG. 1G, and FIG. 4A is a cross-sectional view of FIG. The cross section of the is shown.

First, as shown in FIG. 4B, a portion of the side surface of the third insulating layer 152 made of the TEOS oxide layer is removed by wet etching. In this case, the wet etching solution uses diluted HF solution.

Next, as shown in FIG. 4C, the polysilicon layer 153 is removed.

Next, as shown in FIG. 4D, a portion of the side surface of the second insulating layer 151 made of the low stress nitride layer is removed by wet etching. Here, H ₃ PO ₄ solution is used as an etching solution to selectively wet etch only the low stress nitride film.

Next, when the third insulating layer 152 is removed, only the second insulating layer to be used as a channel mask pattern for forming a channel on the second silicon layer 130 remains as shown in FIG. 4E.

5 is a process diagram in which a source 210 and a drain 220 region are formed in a probe region according to the present invention. As shown in FIG. 5, a thermal oxide layer 710 is formed on the second silicon layer 130. In addition, a nitride film, which is the second insulating film 151, is formed at the probe portion, and SiO ₂ is preferably used as the thermal oxide film 710.

6A to 6D are cross-sectional views of a process for forming a quantum dot according to the present invention. First, as shown in FIG. 6A, a metal film 800 is deposited on the thermal oxide film 710. For example, the metal film 800 may be formed of gold (Au), iron, nickel, chromium, or the like, through sputtering, vacuum deposition, or a sol-gel process. Thereafter, the second insulating film is removed to expose the tip of the probe. The second insulating film is removed by, for example, immersing in a 160 ° C. H ₃ PO ₄ solution.

Next, as shown in FIG. 6B, after the photoresist film 900 is applied, a portion of the photoresist film 900 is removed to expose only the tip of the probe. The photoresist layer 900 may be removed through oxygen plasma ashing using an oxygen asher (O ₂ Asher) of PE (Plasma Enhanced) type.

Next, as shown in FIG. 6C, after the metal film is formed on the photoresist film, the metal quantum dot 820 is formed by lifting off the photoresist film to leave the metal film only at the tip of the probe.

6D is an enlarged view of the peak region of FIG. 6C. An interval 810 between the metal quantum dot 820 and the source and drain electrodes is preferably several nm to several tens nm. In addition, according to the quantum mechanical concept, the number of electrons may be adjusted according to the size of the metal quantum dot 820.

7A to 7D are cross-sectional views of a cantilever shape forming process according to the present invention.

FIG. 7A illustrates a stacked AZ 4620 photoresist film 900 on a semiconductor substrate. The photoresist film 900 serves as a protective film to sufficiently protect the device formed thereon when the first silicon layer 110 is etched. The photoresist film 900 may be used at 110 ° C. for 20 minutes and at 130 ° C. for 10 minutes. Heat treatment for minutes.

7B illustrates a dry etching of the first silicon layer. After forming and patterning the photoresist layer 910 on the lower surface of the first silicon layer 110, the first silicon layer 110 is dry etched. If the first silicon layer 110 is wet etched, the photoresist film 910 must be formed to sufficiently endure the solution used for the wet etch. There is a problem in removing the film later. In addition, the wet etching method uses a dry etching method because the cantilever arm that is weakly attached to the body may be easily broken when the cantilever chip is handled. FIG. 7C is a side view of the state after the process of FIG. 7A is completed. FIG.

FIG. 7D illustrates etching the first insulating film and removing the photoresist film after the process of FIG. 7B is completed. The first insulating layer 120 is wet-etched by using a solution in which BHF and ultrapure water is mixed at a volume ratio of 7: 1 to float the cantilever arm, and then an upper portion of the first silicon layer 110 using an oxygen plasma method. The photoresist film formed on the substrate is burned.

The completed atomic force microscope cantilever is a cantilever support consisting of a first silicon layer 110 and a first insulating film 120 on the first silicon layer, a cantilever arm formed of a thermal oxide film 710, a metal quantum dot 820, Probes and the like.

Although the present invention has been shown and described with reference to preferred embodiments as described above, it is not limited to the above-described embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

Accordingly, the quantum dot transistor atomic force microscope cantilever of the present invention and a method of manufacturing the same are provided in a terabit probe type information storage device by providing a cantilever including a probe having a quantum dot cultured exactly vertically in the channel region of the field effect transistor through a batch process. It can be used to reduce production and manufacturing costs while improving the sensing capability of information.

Claims (16)

Cantilever support; A cantilever arm positioned on the cantilever support object and one side of which is injured; A probe including a silicon located above the tip of the cantilever arm, a thermal oxide film located above the silicon, and a metal film located above the thermal oxide film except for a peak; A channel located in the cantilever arm below the probe; Source and drain, respectively located on both sides of the channel; And A metal quantum dot located at the tip of the probe Quantum dot transistor atomic force microscope cantilever characterized in that it comprises a. The method of claim 1, The cantilever support is a quantum dot transistor atomic force microscope cantilever comprising a first silicon layer and a first insulating layer on the first silicon layer. The method of claim 1, The cantilever arm is composed of first and second arms extending in parallel with a constant width while maintaining a constant distance from each other, and the first and second arms are connected in a V shape at their distal ends. Force microscope cantilever. The method of claim 1, And the probe has a cone or pyramidal shape. The method of claim 1, The quantum dot transistor atomic force microscope cantilever, characterized in that the metal quantum dot is composed of gold. The method of claim 1, A quantum dot transistor atomic force microscope cantilever characterized in that the interval between the metal quantum dot and the source, drain electrodes are several nm ~ several tens nm. The method of claim 1, The probe has a height of 3.6 ± 0.5 micrometers quantum dot transistor atomic force microscope cantilever. The method of claim 1, A quantum dot transistor atomic force microscope cantilever, characterized in that the thickness of the thermal oxide film formed on the silicon layer is 100 nm to 110 nm. In the quantum dot transistor atomic force microscope cantilever manufacturing method, (a) forming a probe on top of the cantilever support; (b) forming a multi-layered film on top of the cantilever support, and then forming a cantilever arm so that the pattern is formed twice and the probe is positioned in the channel region of the transistor and the source and drain regions are formed on both inclined surfaces of the probe; (c) applying and ashing a photoresist on the substrate to expose the tip of the probe; (d) forming a metal film on top of the photoresist and removing the photoresist to leave quantum dots only at the tip of the probe; (e) removing a portion of the cantilever arm to float the cantilever arm Quantum dot transistor atomic force microscope cantilever manufacturing method characterized in that it comprises a. The method of claim 9, Step (a) is Forming a mask pattern for forming a probe on the second silicon layer of the SOI substrate in which the first silicon layer, the first insulating film, and the second silicon layer are sequentially stacked; Masking the mask pattern to etch a portion of the second silicon layer to form a probe shape formed of a silicon layer; Removing the mask pattern; And Forming a thermally oxidized film on the second silicon layer and forming a pointed probe on the second silicon layer by removing the thermal oxidized film by a wet etching process. Quantum dot transistor atomic force microscope cantilever manufacturing method characterized in that it comprises a. The method of claim 10, In step (a), a thermal oxide film is formed on the second silicon layer, and a nitride film, which is a second insulating film, is formed on the tip of the probe. The method of claim 10, The method of manufacturing the quantum dot transistor atomic force microscope cantilever characterized in that the thermal oxide film formed on the second silicon layer is SiO ₂ . The method of claim 9, Step (b) is Sequentially stacking a second insulating film, a third insulating film, a polysilicon layer, and a photoresist on the cantilever support including the probe, and etching the polysilicon layer to the second insulating film to form a cantilever arm mask pattern; Masking with the cantilever arm mask pattern to inject a first impurity into the cantilever support and heat treatment; Etching a portion of the cantilever arm mask pattern to form a channel mask pattern; Masking with the channel mask pattern to inject a second impurity and heat treatment; And Forming a cantilever arm having a shape including the probe, regions implanted with a first impurity and a second impurity Quantum dot transistor atomic force microscope cantilever manufacturing method characterized in that it comprises a. The method of claim 9, The ashing of step (c) is carried out using a PE-type asher, quantum dot transistor atomic force microscope cantilever manufacturing method. The method of claim 9, The metal film of step (d) is quantum dot transistor atomic force microscope cantilever manufacturing method, characterized in that consisting of any one of gold, iron, nickel, chromium. The method of claim 9, The photoresist removal of step (d) is performed by a lift-off process quantum dot transistor atomic force microscope cantilever manufacturing method.

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