JPH07142703A - Quantum thin wire containing branch structure and its manufacture - Google Patents

Abstract

PURPOSE:To provide a structure which, its structure itself, is smaller than de Broglie wavelength by, while utilizing an upper silicon layer an an SOI substrate, making it a quantum thin wire with a branch whose profile is rectangular and the width and height of base are specified. CONSTITUTION:On the surface of SOI substrate 20 a silicon nitride film of 0.05-0.5mum in thickness which is to be used as a mask 2 is film-formed, and then by resist coating, photolithography with ordinary light exposure, and dry etching such as RIE for patterning, the mask 2 with a square window open is formed. Then the SOI substrate 20 an which the mask 2 was formed is etched with anisotropic etching liquid, so that the first surface 3 which is to be a surface of quantum thin wire whose profile is rectangular (width of base is 2-50nm, height is 4-70.6nm) exposes itself. At that time, relating to the first surface 3, the silicon substrate surface is covered with a mask and stopped with a mask end part due to etching anisotropy, it does not advance in the direction of first surface 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantum wire used in electronic devices, optical devices, etc., and more particularly to a quantum wire having a branched structure.

[0002]

2. Description of the Related Art In recent years, semiconductor ultrafine processing technology has been remarkably developed, and a structure having a size of several nm has been formed. A quantum wire is a structure formed by this ultra-fine processing technology. It confines an electron in a minute region of the same size as the de Broglie wavelength, and uses quantum mechanical wave nature to make the electron a single mode (or 1 By increasing the dimensionality and the dimensionality of 0), attention has been paid to the dramatic improvement in performance of electronic devices and optical devices such as high mobility transistors and semiconductor quantum well lasers, and the possibility of creating new devices with new concepts. ing.

The structure of quantum wires includes a superlattice structure, a structure for forming a two-dimensional electron gas at the interface, a structure for confining electrons at a hetero interface, and a structure for controlling a conductive channel by a gate electrode. In order to form such a structure to an ultrafine size, that is, a size of several nm to several tens nm, a fine pattern is formed on a mask material by an electron beam drawing method or an X-ray drawing method, and etching is performed. Various methods have been attempted, such as lithography by which a hetero interface is formed by performing crystal embedding followed by crystal embedding, and a method of controlling crystal growth at the atomic layer level.

Most of such quantum wires have a straight shape, and thus they are not practical devices due to their narrow range of use, but they are experimental devices for confirming the quantum effect. Only. Therefore, it is necessary to form a quantum wire having a branched structure that can be freely routed while maintaining the quantum effect.

As a quantum wire having a conventional branched structure, after forming a superlattice structure of AlAs / GaAs, this is cleaved, and the cleaved surface is subjected to selective thermal etching,
A T-shaped quantum wire structure formed by regrowth of GaAs ("Atomic Dimension Device Research Report I", Japan Electronic Industry Development Association, March 1993, page 18), and MOS As the structure for controlling the conduction channel of the structure, the MOS type channel width of 25n is obtained by the high resolution lithography by the electron beam.
A one-dimensional conduction channel having a branch structure of m is formed, and an electric field is concentrated on the one-dimensional conduction channel to make it function as a quantum wire having a branch structure (J. Vac. Scl. Technol. B. , VOL. 4, NO. 1, Jan / Feb
1986, pp.134-380).

[0006]

However, in the case where the above-mentioned conventional T-shaped quantum wires are formed by cleaving and regrowing after forming the superlattice structure, AlAs /
The GaAs superlattice structure itself can be formed with good reproducibility because it is possible to grow crystals at the atomic layer level using a MOCVD device or the like by the recent ultrafine processing technology, but the subsequent cleavage or GaAs Re-growth and the like cannot be performed with good reproducibility. In particular, the work such as cleaving causes a large variation in the product, and it is difficult to mass-produce a reliable product by such a manufacturing method. It is difficult.

Since the MOS structure uses lithography, the channel width of about 25 nm is the limit as described above due to the limit of the resolution, and a thinner one is required to obtain the quantum effect. Is desired.

[0008] Therefore, an object of the present invention is to provide a quantum wire having a branched structure (not a MOS type) having a size equal to or smaller than the Debye length of electrons,
In addition, a quantum wire with such a branched structure can be reproducibly
It is to provide a manufacturing method that can be easily mass-produced.

[0009]

The present invention for solving the above-mentioned problems provides a quantum wire having a branch formed by an upper silicon layer of an SOI substrate, the quantum wire having a triangular cross section, A quantum wire having a branched structure, characterized in that the base has a width of 2 to 50 nm and a height of 1.4 to 70.6 nm.

Further, the present invention for solving the above object is
A step of forming a mask on the surface of the upper silicon layer of the SOI substrate having an upper silicon layer having a plane orientation (100) and a thickness of 1 nm to 1 μm, and removing a part of the mask to form a rectangular first window. And a step of opening the first window.
Immersing the OI substrate in anisotropic etching to anisotropically etch the silicon surface exposed from the first window to expose the first (111) surface in the upper silicon layer; Forming a first insulating film on the (111) plane of
Forming in the mask a second window having one side intersecting at least one side of the first window; immersing the SOI substrate having the second window opened in anisotropic etching; Anisotropically etching the silicon surface exposed from the second window to expose the second (111) surface in the upper silicon layer, and forming a second insulating film on the second (111) surface And a step of removing at least a part of a portion of the mask that is in contact with the first insulating film and the second insulating film, and anisotropically removing the SOI substrate from which a part of the mask is removed by the above step. And exposing the exposed silicon surface to anisotropic etching of the exposed silicon surface to expose the third (111) surface in the upper silicon layer. Is.

[0011]

The quantum wire having the branched structure of the present invention constructed as described above utilizes the upper silicon layer of the SOI substrate and has a triangular cross section and a base width of 2 to 50 n.
m is a quantum wire with a branch having a size of 1.4 to 70.6 nm, which is a sufficient size to obtain a quantum effect, and the branch allows free placement of the wire. .

The method of manufacturing a quantum wire having a branched structure according to the present invention has a plane orientation (100) and a thickness of 1 nm to 1 μm.
m, a step of forming a mask on the surface of the upper silicon layer of the SOI substrate having an upper silicon layer, a step of removing a part of the mask to open a rectangular first window, and a step of opening the first window. Immersing the opened SOI substrate in anisotropic etching to anisotropically etch the silicon surface exposed from the first window to expose the first (111) surface in the upper silicon layer. , One surface of a branch having a triangular cross section is formed.

The formation of the first (111) plane is performed by anisotropically etching the upper silicon layer of the SOI substrate from the rectangular window opening formed in the mask so that the anisotropic etching is performed from the end of the mask. As the silicon is etched by, the (111) plane is gradually exposed and the first (1)
11) A surface is formed. This anisotropic etching is (11
Since the etching rate of the (1) plane is extremely slow, the etching of the (111) plane exposed from the mask edge does not proceed, so that one side of the quantum wire having a triangular cross section is formed.

Next, a step of forming a first insulating film on the first (111) plane and a second window having one side intersecting at least one side of the first window are formed on the mask. And a step of anisotropically etching the silicon surface exposed from the second window by immersing the SOI substrate having the second window opened in anisotropic etching. 111) exposing the first surface
Forming a second insulating film on the second (111) surface and a surface of the other branch of the branched structure facing the (111) surface, and at least the mask. A step of removing a part of a portion in contact with the first insulating film and the second insulating film, and immersing the SOI substrate from which a part of the mask has been removed in the above step in anisotropic etching to expose Anisotropically etching the exposed silicon surface to expose the third (111) surface in the upper silicon layer, thereby forming a surface facing the second (111) surface and a first (111) surface. Form facing surfaces.

When forming this second (111) plane, the first
When the (111) plane of is the third (111) plane is formed,
Since the first and second (111) planes are protected by the insulating film, it is sufficient if the silicon surface is exposed at the time of immersion of the anisotropic etching solution in this portion, and the range for removing the mask is strict. Since it does not need to be specified, it is not necessary to perform special fine mask patterning. In addition, since the (111) plane facing the already formed (111) plane is formed by anisotropic etching similarly to the first (111) plane, when the (111) plane is exposed, The etching is almost stopped.

As described above, in the method of manufacturing a quantum wire having a branched structure of the present invention, the quantum wire is exposed through the mask window opening patterning step, the anisotropic etching solution immersion step, and the anisotropic etching solution immersion step. By repeating the step of forming the insulating film on the (111) plane, a branched quantum wire is formed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

In the method for manufacturing a quantum wire of the present invention, as shown in FIGS. 1 and 2a, first, an SOI substrate 20 having an upper single crystal silicon layer 23 having a plane orientation (100) and a thickness of about 1 nm to 1 μm is prepared. 0.05-0.5 μm thickness on the surface
A silicon nitride film (SiN) to be the mask 2 of
Mask 2 with a rectangular window opened by patterning this with resist coating, photolithography by ordinary light exposure and dry etching such as RIE or CDE
To form. In addition, the window of the mask 2 has at least one side of the square in the (110) direction as shown in FIG. Here, appendix 21 is a lower silicon layer. 1 is a plan view showing the shape of the mask 2, and FIG.
2A to 2C are cross-sectional views taken along the line AA in FIG.

Next, as shown in FIG. 2B, the SOI substrate 20 on which the mask 2 is formed is treated with an anisotropic etching solution such as K.
The first (111) plane 3 which is one side of the quantum wire having a triangular cross section, is etched by using an anisotropic etching solution such as an OH aqueous solution, a hydrazine aqueous solution, and an ethylenediaminepyrocatechol solution in which only the (111) plane is not etched.
To expose. At this time, the etching of silicon by anisotropic etching progresses gradually from the end of the mask 2 in the depth direction of the SOI substrate 20 while exposing the (111) plane. Since the surface of the silicon substrate is covered with and is stopped by the end of the mask 2 due to the anisotropy of etching, it does not proceed in the (111) plane direction. Further, in the etching in the depth direction, the upper silicon layer 23 is etched and the SiO 2 of the SOI substrate is etched.
₂ Etch until layer 22 is exposed.

Therefore, in controlling etching, it is not necessary to strictly control the surface, and etching time and etching conditions may be set so that the SiO ₂ layer 22 is exposed. For example, when a KOH etching solution is used as the etching solution, the etching solution temperature is set to 60 ° C., and the etching temperature may be changed to some extent depending on changes in the surrounding conditions, and the etching time is set to about 1 to 5 minutes. A slightly wide time control is sufficient.

Next, as shown in FIG. 2c, the exposed silicon surface including the first (111) surface 3 is thermally oxidized,
An insulating film 4a of SiO _{2 having} a thickness of about 0.01 to 0.1 μm is formed. At this time, the surface of the upper silicon layer 23 is not oxidized because there is the mask 2 made of SiN (oxidation resistant film).

Next, as shown in FIG. 3, the window 1 of the mask 2 is shown.
A window 11 having one side that is orthogonal to one side of 0 is formed. For this, resist coating, resist patterning by photolithography by ordinary light exposure as described above, CF
Etching is performed by RIE under SiN etching conditions using ₄ gases. At this time, the insulating film 4a is not removed, and the window 11 is opened to expose the silicon surface. At the time of opening this window, a photomask alignment margin (L in the figure) at the time of photolithography is taken, and this alignment margin is the insulating film 4 at a portion which becomes one branch of the quantum thin wire.
It is for removing the portion of the mask 2 in contact with a and is not particularly specified. Note that FIG. 3 is a plan view showing the shape of the mask 2.

Next, after removing the resist when opening the window 11, as shown in FIGS. 4d and 5d, the mask 2 is removed.
Is removed and the exposed silicon surface is anisotropically etched to expose the second (111) surface 5. This step is the same as when the first (111) plane 3 described above is exposed and does not require strict control of etching. Etching in the (111) plane direction is stopped by the appearance of the second (111) plane 5 so that the second (111) plane 5 is just in contact with the first (111) plane 3 described above. As for the etching amount in the depth direction, the upper silicon layer 21 is etched to expose the SiO ₂ layer 22 of the SOI substrate. 4d to f are sectional views taken along the line AA in FIG. 3, and FIGS. 5d to f are sectional views taken along the line BB in FIG.

The first (111) plane 3 and the second (11) plane 3
1) As shown in FIG. 4d, the portion where the face 5 is in contact becomes the apex of the triangular cross section, and one branch 1a of a quantum wire having a branched structure.
Becomes The second (111) plane becomes one surface of the branch 1b portion of another quantum wire, as shown in FIG. 5a.

Next, as shown in FIGS. 4e and 5e,
The silicon surface exposed by the etching is thermally oxidized to form an insulating film 4b of SiO ₂ , and all the mask 2
(SIN film) is removed. The mask 2 is removed by RIE using CF ₄ gas or CDE under SiN etching conditions as described above. At this time, the insulating films 4a and 4b remain. The mask 2 is removed by
It is not always necessary to remove all of the mask 2, and the removed portion may be only the length of the portion to be the quantum thin line of each branch. For example, a square window 12 may be opened as shown in FIG. The length of each branch of the quantum wire can be changed.
In this example, all the masks 2 were removed as described above. FIG. 6 is a plan view showing the shape of the mask 2.

Next, as shown in FIGS. 4f and 5f,
The exposed silicon surface after removing the mask 2 is anisotropically etched to expose the third (111) surface 6. This step is the same as when the first and second (111) planes described above are exposed, and does not require strict control of etching. This third (111) plane 6 appears just in contact with the above-mentioned first (111) plane 3 and second (111), so that etching in the (111) plane direction is stopped. Further, in the depth direction, the upper silicon layer 21
Are etched to expose the SiO ₂ layer 22 of the SOI substrate.

Thereafter, an unnecessary insulating film is removed, and if necessary, thermal oxidation is performed, so that a finer quantum wire can be obtained. Thereby, as shown in FIG. 7, the quantum wire 1 having a branched structure is completed. The branched structure portion (inside the circle of the one-dot chain line shown in the figure) becomes a quantum wire having a T-type stub structure. Note that FIG. 7 is a perspective view of the quantum thin wire portion.

The quantum thin wire having a branched structure produced as described above has a triangular cross-section, a size of 2 to 50 nm at the base and a height of 1.4 to 70.6 nm at the branched portion. Because of this size also in, the structure is small enough to confine electrons to obtain the quantum effect.

[0029]

As described above, the quantum wire having the branched structure of the present invention utilizes the upper silicon layer of the SOI substrate and has a triangular cross section with a base of 2 to 50 nm and a height of 1.4 to 70.6 nm. Since it is a branched quantum wire, the structure itself is smaller than the de Broglie wavelength of an electron. Therefore, unlike a hetero interface or a MOS structure, an electrode for confining carriers in the vertical direction is not required, and the cross-sectional shape does not change even at a branch point, so that the quantum state of carriers does not change. , The quantum effect is likely to appear.

Further, since the quantum wire having a branched structure of the present invention is formed by anisotropic etching, it can be easily and reproducibly and uniformly formed, and mass production becomes possible.

[Brief description of drawings]

FIG. 1 is a plan view of a mask shape in an embodiment of a method for manufacturing a quantum wire having a branched structure according to the present invention.

2 is a drawing for explaining the manufacturing method of one embodiment according to the present invention in the order of steps, and is a cross-sectional view taken along the line AA in FIG. 1. FIG.

FIG. 3 is a plan view of a mask shape in an example of a method for manufacturing a quantum wire having a branched structure according to the present invention.

4A to 4C are cross-sectional views in order of the steps, continuing from FIG.

5 is a drawing for explaining the manufacturing method of the embodiment according to the present invention in the order of steps, and is a cross-sectional view taken along the line BB in FIG. 3. FIG.

FIG. 6 is a plan view of another mask shape in an embodiment of the method for manufacturing a quantum wire having a branched structure according to the present invention.

FIG. 7 is a perspective view of a quantum wire having a branched structure formed by an embodiment of a method of manufacturing a quantum wire having a branched structure according to the present invention.

[Explanation of symbols]

1. Quantum wire having a branched structure, 1a, 1b
… Quantum wire, 2… Mask,
3, 5, 6 ... (111) plane, 4a, 4b ... Insulating film, 1
0, 11, 12 ... Window formed in mask, 20 ... SOI
Substrate, 21 ... Lower silicon layer, 22
... SiO ₂ layer of SOI substrate, 23 ... upper silicon layer.

Claims (2)

[Claims] 1. A quantum wire having a branch formed by an upper silicon layer of an SOI substrate, wherein the quantum wire has a triangular cross section, a bottom width of 2 to 50 nm, and a height of 1.4 to. A quantum wire having a branched structure, which is 70.6 nm. 2. A plane orientation (100) and a thickness of 1 nm to 1 μm.
m, a mask is formed on the surface of the upper silicon layer of the SOI substrate having the upper silicon layer; a step of removing a part of the mask to open a rectangular first window; The SOI substrate having the window opened is anisotropically etched, and the silicon surface exposed from the first window is anisotropically etched to expose the first (111) surface to the upper silicon layer. A step of forming a first insulating film on the first (111) plane, and a step of forming a second window having one side intersecting at least one side of the first window in the mask. The SOI substrate having the second window opened in the mask is immersed in anisotropic etching, and the silicon surface exposed from the second window is anisotropically etched to form a second layer in the upper silicon layer. Exposing the (111) plane and the second (1 1) a step of forming a second insulating film on the surface; a step of removing at least a part of a portion of the mask in contact with the first insulating film and the second insulating film; The SOI with a part removed
Immersing the substrate in anisotropic etching to anisotropically etch the exposed silicon surface to expose the third (111) surface in the upper silicon layer. A method for manufacturing thin wires.