JPS6245130A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the generation of slip lines by tranmitting heat in an annealing process over an element forming section by the heat transfer of a semi-insulating substrate for dummy and relaxing a sudden temperature change. CONSTITUTION:An impurity forming semiconductor regions 2, 3 are introduced to an element forming surface in a semi-insulating substrate 1, and a protective film 6 is shaped onto the element forming surface. Semi-insulating substrates 7 for dummy are shaped to the upper section of the film 6 and a non-element forming surface oppositely faced to the element forming surface. The substrate 7 is constituted of the same material as the substrate 1. An annealing process is executed under the state in which the substrates 7 are shaped, thus activating the impurity.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a semi-insulating substrate.

[Background Art] Semiconductor integrated circuit devices tend to use semi-insulating gallium arsenide (GaAs) substrates instead of single-crystal silicon (Si) semiconductor substrates. This is because the carrier mobility is faster in the latter than in the former, so the operation speed can be increased.

However, as a result of the inventor's experiments and studies regarding this technology, it has become clear that the use of a semi-insulating substrate causes the following problem.

In an annealing (heat treatment) step for activating the source and drain regions, the wafer (semi-insulating substrate) undergoes rapid temperature changes due to radiant heat when inserted into and pulled out of the heat treatment furnace. This rapid temperature change causes slip lines (M defects) to occur in the wafer, which has weaker mechanical strength than the semiconductor substrate, at the periphery where the internal stress is greatest.
cause

As a result, activation failure occurs and device characteristics deteriorate, resulting in the first problem of lowering the electrical reliability of the semiconductor integrated circuit device.

In addition, the wafer is made of arsenic (As) in the annealing process.
) is easily evaporated, causing deviations in the stoichiometry of the element forming surface. For this reason, an annealing process is performed after a silicon oxide film formed by CVD technology is formed on the element formation surface.

Since the quality of the silicon oxide film is rough, evaporation of arsenic cannot be sufficiently prevented. Therefore, a known technique is to perform an annealing process while applying arsenic pressure in an arsine (As113)'B atmosphere after forming the silicon oxide film (
1985 Spring 32nd Japan Society of Applied Physics 31P -X -
9). However, since arsine, which forms arsenic pressure, is extremely dangerous, a second problem arises in that safety cannot be ensured in the manufacturing process of semiconductor integrated circuit devices.

[Object of the Invention] An object of the present invention is to provide a technique that can reduce the occurrence of slip lines in a semi-insulating substrate and improve electrical reliability.

Another object of the present invention is to provide a technique capable of reducing stoichiometry deviations of a semi-insulating substrate and improving electrical reliability.

Another object of the present invention is to provide a technique that can ensure safety in the manufacturing process of a semiconductor integrated circuit device having a semi-insulating substrate.

Another object of the present invention is to provide a technique that can improve the electrical reliability of a semiconductor integrated circuit device having a semi-insulating substrate and ensure safety in the manufacturing process.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief outline of one typical invention disclosed in this application is as follows.

That is, in a method for manufacturing a semiconductor integrated circuit device having a semi-insulating substrate, a dummy semi-insulating substrate made of the same material is formed on the element forming surface of the semi-insulating substrate, and then,
A heat treatment is performed on the element forming portion of the semi-insulating substrate via the dummy semi-insulating substrate.

29, the heat of the annealing process is transferred to the element forming part by thermal conduction of the dummy semi-insulating substrate, and rapid temperature changes can be alleviated, reducing the occurrence of slip lines. I!
Improves emotional reliability. Further, since the arsenic pressure of the dummy semi-insulating substrate can maintain the stoichiometry of the element formation surface of the semi-insulating substrate, the FFI reliability can be improved. Furthermore, since arsenic pressure can be formed without using arsine, safety in the manufacturing process can be ensured.

The configuration of the present invention will be described below along with one embodiment.

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example] FIG. 1 shows a schematic cross section of a wafer after an annealing process of a semiconductor integrated circuit device according to an example of the present invention, and FIG. 2 shows an enlarged cross section of the main part of FIG. 1.

In Figures 1 and 2, 1 is gallium arsenide (Ci
It is a semi-insulating substrate (wafer) made of aAs), and is configured to constitute a plurality of chip-shaped semiconductor integrated circuit devices.

As shown in FIG. 2, a Schottky gate field effect transistor (
MESFET) Q is configured.

MESFETQ is composed of an i-type semiconductor region 2 as a channel formation region, a pair of n-type semiconductor regions 3 as source or drain regions, and a gate electrode (Schottky junction metal, for example, WSi2) 4. 5 is semiconductor region 3
For example, Ni/Au
- It is composed of Ga.

In the semi-insulating substrate 1 on which the semiconductor elements are formed in this manner, activation of the semiconductor regions 2 and 3 is performed by a primary manufacturing method.

First, a semi-insulating substrate (wafer) 1 is prepared.

This semi-insulating substrate 1 has a thickness of, for example, about 600 [μm] in consideration of mechanical strength and the like.

Next, a semiconductor region 2,
After introducing the impurity forming the element 3, a protective film 6 is formed on this element formation surface. This protective film 6 covers the semi-insulating substrate 1
For example, the depth of the element forming part is 1000 to 2000 mm.
This is to reduce the evaporation of arsenic in the annealing process in the portion [A], thereby reducing the deviation in stoichiometry. The protective film 6 is made of, for example, a silicon oxide film or a silicon nitride film formed by CVD technology.
Formed with a film thickness of about 0 [λ].

Thereafter, a dummy semi-insulating substrate 7 is formed on the protective film 6 and on the non-element forming surface (back side of the wafer) opposite to the element forming surface. This dummy semi-insulating substrate 7 is made of the same material as the semi-insulating substrate 1, and is, for example, formed to have approximately the same thickness as the semi-insulating substrate 1 and a length larger than that. .

In this way, by forming the dummy semi-insulating substrate 7 with a larger size than the semi-insulating substrate 1, the area of the dummy semi-insulating substrate 7 can be maintained even if one misalignment occurs in the process of overlapping the two. A semi-insulating substrate 1 can be present within the structure.

Next, with the dummy semi-insulating substrate 7 formed, an annealing step is performed to activate the impurities, thereby forming semiconductor regions 2 and 3 as shown in FIG. The annealing process is performed at a temperature of, for example, 800 to 850 ['C].

In this way, by forming the dummy semi-insulating substrate 7 on the element formation surface of the semi-insulating substrate 1 and then performing an annealing process, the heat of the annealing process is transferred to the dummy semi-insulating substrate 7. Since the temperature is transmitted to the element forming part, rapid temperature changes in the element forming part can be alleviated. As a result, it is possible to reduce the occurrence of slip lines on the semi-insulating substrate 1, thereby suppressing deterioration of device characteristics and improving electrical reliability.

Furthermore, arsenic is evaporated from the dummy semi-insulating substrate 7 during the annealing process, and this arsenic pressure can suppress the evaporation of arsenic in the element forming portion of the semi-insulating substrate 1, so that the stoichiometry can be maintained. As a result.

It is possible to suppress deterioration of device characteristics and improve electrical reliability.

In addition, by configuring the dummy semi-insulating substrate 7 with a larger size than the semi-insulating substrate 1, the dummy semi-insulating substrate 7 is made semi-insulating! Since stoichiometry can be maintained at all times even at the temporary end, electrical reliability can be improved.

In addition, by maintaining the stoichiometry of the semi-insulating substrate 1 with the arsenic pressure of the dummy semi-insulating substrate 7, it is possible to avoid the use of extremely dangerous arsine, etc., thereby ensuring safety in the manufacturing process. It is possible to ensure sex.

Furthermore, by forming the protective film 6 on the element formation surface, evaporation of arsenic can be further suppressed and stoichiometry can be maintained. In addition, the protective film 6 is particularly suitable for the dummy semi-insulating substrate 7.
The stoichiometry at the edge of the semi-insulating substrate 1 which is not provided with the stoichiometry can be maintained, or the stoichiometry can be maintained even after a long annealing process is performed. Furthermore, the protective film 6 can improve the adhesion between the element formation surface of the semi-insulating substrate 1 and the dummy semi-insulating substrate 7.

After the annealing process is completed, the dummy semi-insulating substrate 7 is removed.

In the above embodiment, the dummy semi-insulating substrate 7 was provided on the element forming surface and the non-element forming surface of the semi-insulating substrate 1, but the present invention provides a semi-insulating j! The dummy semi-insulating substrate 1 may be provided only on the temporary element formation surface.

Furthermore, the present invention does not require the provision of the bactericidal protection v6.

Further, the present invention is not limited to an annealing process for activating the semiconductor regions 2 and 3, but may be applied to, for example, an annealing process for activating a gate cell.

[Effects] As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.

(L) In a method for manufacturing a semiconductor integrated circuit device having a semi-insulating substrate, a dummy semi-insulating substrate made of the same material is formed on the element forming surface of the semi-insulating substrate, and then the dummy semi-insulating substrate By applying heat treatment to the element forming part of the semi-insulating substrate through the dummy semi-insulating substrate, the heat of the annealing process is transferred to the element forming part by thermal conduction of the dummy semi-insulating substrate, thereby mitigating sudden temperature changes. Therefore, the occurrence of slip lines can be reduced and electrical reliability can be improved.

(2) According to (1) above, the stoichiometry of the element forming part of the semi-insulating substrate is determined by the arsenic pressure of the dummy semi-insulating substrate.
can be maintained, so electrical reliability can be improved.

(3) According to the above (2), since the arsenic pressure can be formed using the dummy semi-insulating substrate, there is no need to use extremely dangerous arsine.

(4) According to (3) above, safety in the manufacturing process can be ensured.

(5) According to (1) to (4) above, it is possible to improve the electrical reliability of a semiconductor integrated circuit device having a semi-insulating substrate and ensure safety in the manufacturing process.

Although the invention made by the present inventor has been specifically explained above based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and can be modified in various ways without departing from the gist thereof. Of course, it can be modified.

The present invention is effective not only when a GaAs substrate is used as the substrate, but also when a wide range of substrates made of compound semiconductors are used. That is, in the present invention, the IL-insulating substrate includes Garr+As, InAs, I
It includes a substrate made of a compound semiconductor such as nSb, GaSb, or GaP.

[Brief explanation of drawings]

FIG. 1 is a schematic cross-sectional view of a wafer after an annealing process of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is an enlarged sectional view of the main part of FIG. 1. In the figure, 1... Semi-insulating substrate (wafer), 6... Protective film, 7... Insulating substrate for dummy, Q... ME
It is an SFET. Figure 1 Figure 2

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor integrated circuit device having a semi-insulating substrate, a dummy semi-insulating substrate made of the same material as the semi-insulating substrate is provided on the element formation surface of the semi-insulating substrate. After that, through the dummy semi-insulating substrate,
A method for manufacturing a semiconductor integrated circuit device, comprising the step of applying heat treatment to an element forming portion of the semi-insulating substrate. 2. The dummy semi-insulating substrate is formed after forming a protective film on the element forming surface of the semi-insulating substrate to prevent deviation of the stoichiometry of the semi-insulating substrate in the element forming portion. Claim 1 characterized in that
A method for manufacturing a semiconductor integrated circuit device according to paragraph 1. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the dummy semi-insulating substrate is formed in a larger size than the semi-insulating substrate. 4. The semiconductor integrated device according to claim 1, wherein the dummy semi-insulating substrate is formed on an element-forming surface of the semi-insulating substrate and a non-device-forming surface opposite thereto. A method of manufacturing a circuit device.