JPS6245072A - Semiconductor memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To assure a sufficient withstand voltage between the diffusion regions by forming a low concentration impurity diffusion region between high concentration impurity diffusion regions, and providing a tri-gate structure to the gate thereabove. CONSTITUTION:On the pattern on a p<-> substrate 1 divided by an element isolation region 2, an insulating film 31 which is a very thin oxide film, and subsequently an insulating film 4 consisting of a nitride film are formed respectively. Phosphorus P or the like is implanted onto the insulating film 4 to form an n<-> region and subsequently a pattern 8 of photoresist, with the resist of the pattern 8 as a mask the insulating films 31 and 4 are etched, and the photoresist 8 is removed. Then, an insulating film 9 is formed, and thereon a polysilicon layer 5 which is to become an electrode is applied, with the photoresist pattern as a mask the polysilicon layer 5 and the insulating layer 9 are etched, and thereafter the photoresist is removed. As or the like is implanted to form n<+> diffusion regions 61, 62, and an n<-> region is provided therebetween and formed into a tri-gate structure. With this, the withstand voltage between the diffusion regions 61, 62 are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device that performs a memory operation by accumulating charge in a memory gate portion, and a method of manufacturing the same.

[Conventional technology]

FIG. 3 is a cross-sectional view showing the structure of a conventional memory gate transistor. This transistor has an element area (2
) is separated from adjacent transistors. Then, a voltage is applied to the gate electrode (5), which causes the insulating film (31
) through which the insulating film (4) captures electrons and holes, thereby varying Vth.
It is a memory transistor that determines “lo”. For example,
In the transistor shown in FIG. 3 above, the gate electrode (5)
When a positive voltage is applied to the insulating film (4), electrons are captured by the insulating film (4) through the insulating film (3I), and the Vth of this transistor increases. In addition, the gate electrode (
When a negative voltage is applied to 5), the Vth of this transistor becomes low. This difference is the logical value of 11+1,11
A 0+1 determination is made.

[Problem that the invention seeks to solve]

In the structure shown in FIG. 3 above, the n" diffusion region (61) and (
If a high voltage is applied between 62) and 62), current leaks and circuit problems occur, so it was necessary to prevent this phenomenon. So this diffusion area (Eil).

In order to increase the withstand voltage between (62) and 62, there has been a demand for the development of a transistor with a new structure and a method for manufacturing the same.

The present invention was made in order to satisfy the above-mentioned needs, and an object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same that can provide a sufficient breakdown voltage between diffusion regions.

[Means for solving problems]

The present invention is characterized in that a low concentration impurity diffusion region is formed between the high concentration impurity diffusion regions, and the gate above the region has a tri-gate structure.

[Effect]

Due to the diffusion of low concentration impurities and the tri-gate structure, current leakage is reduced and drain breakdown voltage is improved.

[Embodiments of the invention]

Hereinafter, a description will be given of FIG. 1 and FIG. 2 (λ) to h) showing a cross-sectional view of a memory gate structure according to an embodiment of the present invention and each cross-sectional view according to its manufacturing process. In these figures, parts that are the same as or corresponding to those in FIG. 3 are designated by the same reference numerals.

First, as shown in FIG. 2(a), an extremely thin oxide insulating film (31) is formed on a p-substrate (1) separated by an element isolation region (2) on a t-substrate (31). is about 500A
An insulating film (4) made of a nitride film of about 100% is formed.

In this state, phosphorus (
A material such as Pl is injected to form an n- region. Next, a photoresist pattern (8) is formed as shown in the same figure (C).
)), using the resist pattern (8) as a mask, the insulating films (3]) and (4) are etched, and then the photoresist +-f81 is removed (FIG. 4(d)). Next, from the state shown in B, an insulating film (9) made of an oxide film with a thickness of about 600 A is formed (Fig. 2(e)), and then a polysilicon layer (5) which will become an electrode is coated on top of it (Fig. 3(e)). f)),
Next, the polysilicon layer (5) and the insulating layer (9) are etched using the photoresist pattern as a mask, and then the first resist is removed (FIG. 1(g)).

From this state, As or the like is implanted to form n'' diffusion regions (61J, (62)) (FIG. 1(h) and FIG. 1).

The structure formed by this manufacturing process has an n1 region between the n+ diffusion regions (61) and (62), and a structure (tri-gate structure) with gate insulation M(9). Region (61), (62)rI
This is aimed at improving the breakdown voltage of II.

In the above embodiment, a p-type substrate is used and an n" type diffusion region is formed on it, but the present invention is not limited to this in any way. You may try to use something.

〔Effect of the invention〕

As explained above, according to the present invention, the memory gate has double diffusion regions with different impurity concentrations and has a tri-gate structure, so that the breakdown voltage between the diffusion regions (
This has the effect of improving drain breakdown voltage).

[Brief explanation of drawings]

FIG. 1 is an rFr surface structure diagram according to an embodiment of the present invention, FIGS. 2(a) to (h) are process diagrams showing an embodiment of the method for structuring a semiconductor memory device according to the present invention, and FIG. 3 is a conventional FIG. 3 is a cross-sectional view showing the structure of a memory gate of FIG. In the figure, (1) is a semiconductor substrate, (2) is an element isolation region, (
31) , +41 , (91 is an insulating film, (5) is a gate electrode, (61). (62) is a wave number domain. The same reference numerals in each figure indicate the same or equivalent parts. Agent Patent attorney Masaru Sato Figure 1 Figure 8 Figure 2 Figure 2

Claims (2)

[Claims] (1) In a semiconductor memory device in which a gate electrode is formed with an insulating film interposed between first and second diffusion regions in which high concentration impurities are diffused, between the first and second diffusion regions: A semiconductor memory device, wherein a low concentration impurity having the same conductivity type is diffused into the diffusion region, and the gate electrode has a tri-gate structure. (2) A method for manufacturing a semiconductor memory device that performs a memory operation by accumulating charges in a transistor section composed of a semiconductor substrate, an insulating film, and an electrode, including the step of forming a thin oxide film on the surface of the semiconductor substrate; A step of generating a nitride film on the generated oxide film, a step of implanting ions onto the generated nitride film, and a step of applying a photoresist on the generated nitride film and patterning it by photolithography. a step of etching the formed oxide film and nitride film using the formed photoresist pattern as a mask; a step of forming an oxide film with the formed pattern; and a step of etching the oxide film with the formed pattern. a step of forming a polysilicon layer on the formed oxide film; a step of applying a photoresist on the formed polysilicon layer and patterning it by photolithography; A method for manufacturing a semiconductor memory device, comprising the step of etching the polysilicon layer and the oxide film using a photoresist pattern as a mask to form a tri-gate structure.