JPS6245050A - Substrate for semiconductor device - Google Patents
Substrate for semiconductor deviceInfo
- Publication number
- JPS6245050A JPS6245050A JP18489185A JP18489185A JPS6245050A JP S6245050 A JPS6245050 A JP S6245050A JP 18489185 A JP18489185 A JP 18489185A JP 18489185 A JP18489185 A JP 18489185A JP S6245050 A JPS6245050 A JP S6245050A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- conductive substrate
- semiconductor device
- thermally conductive
- coating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
3、発明の37:1[1な説明
〈産業上の利用分野〉
この発明は半導体装置用基板に関し、特にIC搭載用の
放熱用基板として好適な半導体装置用基板に関する。Detailed Description of the Invention 3. 37:1 [1 Description (Field of Industrial Application)] This invention relates to a substrate for a semiconductor device, and particularly to a substrate for a semiconductor device suitable as a heat dissipation substrate for mounting an IC. .
〈背景及び従来技術〉
従来より、半導体装置用基板として、熱伝導性の良好な
金属からなる放熱用基板が提供されている。上記放熱用
基板は、集積回路の高密度化が進むにつれて、半導体素
子からの発熱量が増大する点に鑑み、放熱を効果的に行
なわける目的で使用されており、設計上絶縁性が必要と
される場合には、熱伝導性の良好な金属製基板に対して
、絶縁性シートを貼り合せるか、或いは気相法によって
絶縁性MPMを形成することが行なわれている。<Background and Prior Art> Conventionally, heat dissipation substrates made of metals with good thermal conductivity have been provided as substrates for semiconductor devices. The above-mentioned heat dissipation substrate is used for the purpose of dissipating heat effectively, in view of the fact that the amount of heat generated from semiconductor elements increases as the density of integrated circuits increases, and insulation is required in the design. In this case, an insulating MPM is formed by bonding an insulating sheet to a metal substrate having good thermal conductivity or by a vapor phase method.
〈発明が解決しようとする問題点〉
ところが、絶縁性シートを貼り合せた場合には、全屈製
基板と絶縁性シートとの間に接着剤を介在させる必要が
あり、かつ、絶縁性シート自体の薄肉化が困難であるか
ら、高い熱伝導率が得られないという問題がある。また
、製造工程が複雑化し、コス]・が高くつくという問題
もある。<Problems to be solved by the invention> However, when the insulating sheets are bonded together, it is necessary to interpose an adhesive between the fully bent substrate and the insulating sheet, and the insulating sheet itself There is a problem in that high thermal conductivity cannot be obtained because it is difficult to make the wall thin. There is also the problem that the manufacturing process is complicated and the cost is high.
一方、気相法にて薄膜を形成した場合には、高温領域に
おいて、薄膜の相転移、再結晶化、熱膨張係数の差によ
る熱応力等に起因して薄膜にミクロ的な破壊を生じ、絶
縁性が低下したり、耐薬品性を発揮し得なくなるという
問題がある。On the other hand, when a thin film is formed by a vapor phase method, micro-destruction occurs in the thin film due to phase transition, recrystallization, thermal stress due to a difference in thermal expansion coefficient, etc. in the thin film in a high temperature region. There are problems in that insulation properties deteriorate and chemical resistance cannot be exhibited.
この発明は上記問題点に鑑みてなされたらのであり、熱
伝導性に優れるとともに、高温領域においても良好な絶
縁性、耐薬品性を発揮し得る半導体装置用基板を提供す
ることを目的とする。The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a substrate for a semiconductor device that has excellent thermal conductivity and can exhibit good insulation and chemical resistance even in a high temperature range.
く問題点を解決するための手段〉
上記目的を達成するためのこの発明の半導体装置用基板
としては、熱膨張係数がlX10−6〜11 X 10
’cm/dcgt’、カッ熱伝導率力、0.1cat
/Cm−Sec −k以上の金属からなる高熱伝導性
基板に、軟化点が600℃以上で、かつ厚みが3〜30
μ鳳の高融点ガラスからなる絶縁性被膜を形成しである
。Means for Solving the Problems> The substrate for a semiconductor device of the present invention for achieving the above object has a thermal expansion coefficient of lX10-6 to 11X10.
'cm/dcgt', thermal conductivity force, 0.1cat
/Cm-Sec -k or higher, a highly thermally conductive substrate made of a metal with a softening point of 600°C or higher and a thickness of 3 to 30°C.
An insulating film made of high melting point glass is formed.
但し、上記絶縁性被膜としては、高熱伝導性基板に対し
て直接被覆形成するほか、金B層を介して間接的に被覆
形成することもできる。また、熱伝導性基板としては、
Cu−W合金、Cu−M。However, the above-mentioned insulating film can be formed not only directly on the highly thermally conductive substrate but also indirectly through the gold B layer. In addition, as a thermally conductive substrate,
Cu-W alloy, Cu-M.
合金、△1−Si合金等にて形成することが考えられる
。It is conceivable to form it with an alloy, Δ1-Si alloy, or the like.
く作用〉
上記半導体装置用基板によれば、半導体素子が発する熱
を、高熱伝導性基板および高融点ガラスからなる絶縁性
被膜を介して効率良く放散させることができる。また、
高温領域における絶縁性被膜の絶縁性および耐薬品性を
、高融点ガラスにて安定的に確保することができる。Effects> According to the semiconductor device substrate, heat generated by the semiconductor element can be efficiently dissipated through the highly thermally conductive substrate and the insulating film made of high melting point glass. Also,
The insulation and chemical resistance of the insulating film in a high temperature region can be stably ensured using high melting point glass.
〈実施例〉 以下実施例を示す添付図面によって詳細に説明する。<Example> Embodiments will be described in detail below with reference to the accompanying drawings showing examples.
第1図は、高熱伝導性基板(1)の片面に対して、高融
点ガラスからなる絶縁性被膜(2)を直接被覆した半導
体装置用基板を示す断面図である。FIG. 1 is a sectional view showing a semiconductor device substrate in which one side of a highly thermally conductive substrate (1) is directly coated with an insulating film (2) made of high melting point glass.
上記高熱伝導性基板(1)としては、熱膨張係数が1×
10〜11×10−60m/degで、かつ熱伝導率が
0 、 I Cat /ca+−sec −k以上の金
属、例えばCu−W合金、Cu−MO合金、A I −
Si合金等により形成されている。熱膨張係数を上記範
囲に規制することにより、熱8服係数の差に起因する絶
縁性被膜(2のミクロ的な破壊を防止することができる
。また、熱伝導率を0.1Cal /cm・5ec・k
以上とすることにより、高熱伝導性基板(1)上に取付
けられた半導体素子(3)が発する熱を、率良く伝熱す
ることができる。The high thermal conductive substrate (1) has a thermal expansion coefficient of 1×
10 to 11 x 10-60 m/deg and a metal with a thermal conductivity of 0, I Cat /ca+-sec-k or more, such as Cu-W alloy, Cu-MO alloy, AI-
It is made of Si alloy or the like. By regulating the thermal expansion coefficient within the above range, it is possible to prevent microscopic destruction of the insulating film (2) caused by differences in thermal coefficients.Also, the thermal conductivity can be reduced to 0.1 Cal/cm. 5ec・k
By doing so, the heat generated by the semiconductor element (3) mounted on the highly thermally conductive substrate (1) can be efficiently transferred.
マタ、絶縁性被膜(′2Jは、接続端子としてのセラミ
ック(4)を高熱伝導性基板(1)に対してロウ付けす
る際において溶融しないことが必要であり、このため、
高融点ガラスとして、軟化点が600℃以のものが使用
されている。さらに、絶縁性波Ill (21の被覆厚
みとしては、3〜30μmの範囲に設定されており、安
定した絶縁性と熱放散性が得られるようになっている。The insulating coating ('2J) must not melt when the ceramic (4) serving as the connection terminal is brazed to the highly thermally conductive substrate (1).
As the high melting point glass, glass having a softening point of 600° C. or higher is used. Furthermore, the coating thickness of the insulating wave Ill (21) is set in the range of 3 to 30 μm, so that stable insulation and heat dissipation properties can be obtained.
即ち、絶縁性被膜(2)の被覆厚みが3μa米>liで
あると、絶縁不良を生じるおそれがあり、また、30#
l友應えるへと、高熱伝導性基板(1)からの伝導熱の
放散を阻害することとなる。That is, if the coating thickness of the insulating coating (2) is 3 μa > li, there is a risk of insulation failure;
Otherwise, the dissipation of conductive heat from the highly thermally conductive substrate (1) will be inhibited.
以上の構成であれば、絶縁性被膜(2)は、少なくとも
600℃Jf−tの温麿領域において、安定した絶縁性
を発揮することができる。また、絶縁性被膜(2)とし
ての高融点ガラスは、耐アルカリ性、耐酸性等の耐薬品
性を有することから、Siチップボンディングおよび耐
酸化性向上のためのAuメッキ等が可能となる。With the above configuration, the insulating film (2) can exhibit stable insulation in the temperature range of at least 600° C.Jf-t. Furthermore, since the high melting point glass used as the insulating coating (2) has chemical resistance such as alkali resistance and acid resistance, Si chip bonding and Au plating for improving oxidation resistance are possible.
なお、この発明は、上記実施例に限定されるものでなく
、例えば第2図に示すように、絶縁性被膜(2)を、高
熱伝導性基板(1)に被覆したニッケル等の金属層(9
を介して被覆する等゛、この発明の要旨を変更しない範
囲で種々の設計変更をtAずことができる。Note that the present invention is not limited to the above-mentioned embodiments, and for example, as shown in FIG. 9
Various design changes can be made without changing the gist of the present invention, such as coating the material through a wire.
く比較例〉
高熱伝導性基板(1)を、Cu−W合金(10〜15重
量%Cu)、およびCu−MO合金(10〜15i1d
%MO>で形成し、これら高熱伝導性基板(1)に対し
、絶縁性被膜(Zを2〜28μ麿の厚みで直接被覆した
半導体装置用基板の性能試験結果を次表に示す。ただし
、絶縁性波M(21としては、ガラスペースト(軟化点
850℃)をスクリーン印刷して950℃で焼成したも
のである。Comparative Example> A highly thermally conductive substrate (1) was prepared using a Cu-W alloy (10 to 15% by weight Cu) and a Cu-MO alloy (10 to 15% by weight).
The following table shows the performance test results of substrates for semiconductor devices in which these highly thermally conductive substrates (1) were directly coated with an insulating coating (Z) with a thickness of 2 to 28 μm. The insulating wave M (21) was made by screen printing glass paste (softening point: 850°C) and firing it at 950°C.
表
上記比較例より、絶縁性被膜(2)の被覆厚みが3〜3
077mの範囲において、良好な絶縁性および熱伝導率
を得られることが推察できる。From the comparative example above in the table, the coating thickness of the insulating coating (2) is 3 to 3.
It can be inferred that good insulation and thermal conductivity can be obtained in the range of 0.077 m.
〈発明の効果〉
以上のように、この発明の半導体装置用基板は、熱伝導
性、熱放散性に優れるとともに、高温領域においても良
好な絶縁性、耐薬品性を発揮し得るという特有の効果を
奏する。<Effects of the Invention> As described above, the semiconductor device substrate of the present invention has the unique effects of being excellent in thermal conductivity and heat dissipation, and also exhibiting good insulation and chemical resistance even in high-temperature areas. play.
第1図は半導体装置用基板を示す断面図、第2図は他の
実流例を示す断面図。
(1)・・・高熱伝導性基板 (2)・・・絶縁性
被膜(5)・・・金属層FIG. 1 is a sectional view showing a substrate for a semiconductor device, and FIG. 2 is a sectional view showing another example of actual flow. (1)...High thermal conductivity substrate (2)...Insulating coating (5)...Metal layer
Claims (1)
6cm/degで、熱伝導率が0.1Cal/cm・s
ec・k以上の金属からなる高熱伝導性基板に、軟 化点が600℃以上で、かつ厚みが3〜 30μmの高融点ガラスからなる絶縁性被膜を形成して
あることを特徴とする半導体装 置用基板。 2、絶縁性被膜が、高熱伝導性基板に対して直接被覆形
成されている上記特許請求の範 囲第1項記載の半導体装置用基板。 3、絶縁性被膜が、高熱伝導性基板に対して金属層を介
して間接的に被覆形成されてい る上記特許請求の範囲第1項記載の半導体 装置用基板。 4、高熱伝導性基板が、Cu−W合金である上記特許請
求の範囲第1項記載の半導体装 置用基板。 5、高熱伝導性基板が、Cu−Mo合金である上記特許
請求の範囲第1項記載の半導体 装置用基板。 6、高熱伝導性基板が、Al−Si合金である上記特許
請求の範囲第1項記載の半導体 装置用基板。[Claims] 1. Coefficient of thermal expansion is 1×10^-^6 to 11×10^-^
At 6cm/deg, the thermal conductivity is 0.1Cal/cm・s
For semiconductor devices, characterized in that an insulating film made of high melting point glass having a softening point of 600° C. or more and a thickness of 3 to 30 μm is formed on a highly thermally conductive substrate made of a metal of ec・k or more. substrate. 2. The semiconductor device substrate according to claim 1, wherein the insulating film is formed directly on the highly thermally conductive substrate. 3. The semiconductor device substrate according to claim 1, wherein the insulating film is indirectly formed on the highly thermally conductive substrate via a metal layer. 4. The substrate for a semiconductor device according to claim 1, wherein the highly thermally conductive substrate is a Cu-W alloy. 5. The substrate for a semiconductor device according to claim 1, wherein the highly thermally conductive substrate is a Cu-Mo alloy. 6. The substrate for a semiconductor device according to claim 1, wherein the highly thermally conductive substrate is an Al-Si alloy.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18489185A JPS6245050A (en) | 1985-08-22 | 1985-08-22 | Substrate for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18489185A JPS6245050A (en) | 1985-08-22 | 1985-08-22 | Substrate for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6245050A true JPS6245050A (en) | 1987-02-27 |
Family
ID=16161121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18489185A Pending JPS6245050A (en) | 1985-08-22 | 1985-08-22 | Substrate for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6245050A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59184586A (en) * | 1983-04-01 | 1984-10-19 | 住友電気工業株式会社 | Circuit board for placing semiconductor element |
JPS6042247A (en) * | 1983-08-16 | 1985-03-06 | Asahi Glass Co Ltd | Low expansion glass |
-
1985
- 1985-08-22 JP JP18489185A patent/JPS6245050A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59184586A (en) * | 1983-04-01 | 1984-10-19 | 住友電気工業株式会社 | Circuit board for placing semiconductor element |
JPS6042247A (en) * | 1983-08-16 | 1985-03-06 | Asahi Glass Co Ltd | Low expansion glass |
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