JPS624371A - Manufacture of vlsi circuit using heat resistant metal silicide - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to the fabrication of large scale integration (VLSI) metal oxide semiconductor field effect transistor (MOSFET) circuits.

High performance V
In manufacturing LSI MO8FET circuits, polycrystalline silicon (polysilicon) is commonly used for gate and interconnect regions. However, the high resistivity of polysilicon results in a 10 hour delay that limits device performance.

Also, MOSFET is 1 micron or less (submicron)
Because the shallow source and drain junctions are reduced in size during the process, their shallow source and drain junctions have high sheet resistance
stance).

To reduce delays due to high area resistance of polysilicon gates and interconnects, refractory metal silicides or composite refractory metal silicide/polysilicon compositions have been proposed for gates and interconnects (181MO8FET VL
SI technology: Part ■ - Golden horse silicide interconnection technology - Unexpected prospects,” American Institute of Electrical and Electronics Engineers, Solid State Circuit Journal (IEEE % Journal of
5olid 5tate (ircaits
)), 5C-14, p. 291, 1971, Crowder et al.), ) Additionally, silicification of the source, drain, and gate of silicon to reduce the sheet resistance of shallow source and drain junctions sil
icidation) has been attempted in the US, and as a result the so-called 5ALICIDE structure is known ("Optimum Design Process for Submicron MO3FETs").
, IEDM, Technology Digest (Tachniaa
Shibata et al., p. 647, 1981). In this 5ALICIDE fujutsu, MOSFET
The source, drain and polysilicon gate are formed with the same silicide layer. (The oxide area of the III wall is used to separate the source and drain from the gate. In this silicidation step, a noble or refractory metal is deposited on the entire surface and then deposited on the source, drain and polysilicon gate. After this reaction, the unreacted metal is selectively etched away by a chemical etching agent.In practice, however, a thin layer of metal is Firstly, during the silicification process, silicon is consumed as the metal silicide is formed. The thickness of the silicon to be consumed depends on the phase of the silicide formed. and must be equal to or greater than the thickness of the deposited metal.For example, titanium silicide (T
is iz), the thickness of the polysilicon is twice the thickness of the metal.6 To avoid the formation of a shot also with significant junction leakage, the thickness of the metal is twice that of the source and junction depth. It should be smaller than ×. Another reason for using a thin metal layer is the fi! used to insulate the gate from the source and drain. ! ! The goal is to avoid the formation of silicides on top of oxides. Any silicide on this region will electrically short the source and drain to the gate.

Thus, for VLSI MO8FET circuits with source and drain junctions close to 0.1 microns deep, the metal thickness used must be no more than 200 Angstroms (2X10-'e rings), approximately 0 ．．
For a 3 micron thick polysilicon puto, 200 angstroms (2X 1
500 angstroms (5X 10-'csi) that can be formed from metal in units of 0"" c-rings
A thin layer of silicide has a sheet resistance of about 1 ohm/sq.
(ohm/5 square), in fact the minimum resistivity of silicide is 20μ
Polysilicon (20
00 angstroms (2X 10-So-5a silicide (500 angstroms (5X 10''''cs
e) The sheet resistance of) is greater than 4 ohms/square. Therefore, 5 ALICIDE technology does not provide optimal areal resistance gates and interconnects for devices smaller than 1 micron. 6 Means for Solving the Problems To overcome these problems, in accordance with one aspect of the present invention, refractory metal Create a VLSI MO8FET circuit using a heat-resistant metal silicide! A method has been proposed for fabricating a conductive gate layer having a refractory metal or refractory metal silicide portion on a silicon substrate, the method comprising: forming a gate oxide layer on a silicon substrate; Forming on; gate 1 in the conductive gate layer! forming source and drain regions in the substrate; and forming a thin refractory metal or silicide bonding layer over the gate, source and drain regions.

The conduction gate layer can be formed by first depositing a layer of polysilicon and then a layer of refractory metal or metal silicide. The conduction gate layer is alternatively deposited as a single layer of a refractory metal or refractory metal silicide, such as molybdenum or tungsten.

The refractory metal silicide can be deposited directly by one of several techniques such as co-evaporation, co-sputtering, composite tarded sputtering, or chemical vapor deposition (CVD).

The refractory metal ends up being deposited by evaporation, sputtering, or CVD.

After gate formation, the gate region within the gate conductive layer must be annealed, although the heat of the subsequent oxidation and diffusion steps can act to reduce the gate area resistance. - Can be defined by etching. The source and drain regions can be produced by annealing followed by ion implantation. A surface insulating oxide region for electrically isolating the gate from the source and drain regions is formed by depositing an oxide layer on the wafer and etching away the oxide by reactive ion etching. be able to. The oxide is completely removed over the gate, source and drain regions, but not completely removed in the gate sidewall regions where the oxide is initially relatively thick.

The thin junction silicide layer formed over the source, drain and gate regions can be deposited as a refractory metal such as titanium, and then form a metal silicide when this metal is present on the silicon. It can be sintered for. Other metals such as cobalt, nickel, platinum, and paranoum can also be used. The unreacted metal on this field and the insulating oxide region is then melted. Alternatively, refractory metals such as tungsten and molybdenum can be selectively deposited over the source, drain and gate regions to shunt the sheet resistance of underlying layers.

The refractory metal used to form the gate conductive layer may be one of a group of metals including titanium, tantalum, tungsten and molybdenum. If the subsequent processing is not performed at high temperatures above 900° C., the noble metals platinum and palladium can be used instead for the gate conductive layer. The thickness of the refractory metal or refractory metal silicide layer in the gate conductive layer is 1500 to 2500 angstroms (1
The thickness of the refractory metal or silicide bonding layer is preferably in the range of 300 to 1600 Angstroms (3XIO-').
It is preferably in the range of ~lXl0-'c).

The g&socket interconnect can be formed simultaneously with the gate conductive layer.

Embodiments of the invention will now be described by way of example with reference to the accompanying drawings.

EXAMPLE FIG. 1 shows in detail a metal-oxide-semiconductor field effect transistor (MOSFET) formed on a p-type silicon substrate. Beneath the insulating field oxide region 12 is a p-medium region 14. N+ type source and drain regions 1 (3, 18 are in the substrate).

A gate oxide layer 22 extends between the source and drain and overlies the channel region 20 in the substrate 10.

2500 angstrom (2.5 x 10'' ga theory)
A polysilicon bottom layer 24 thick and a titanium silicide top layer 26 12,500 angstroms thick overlie the gate oxide layer. Insulating oxide regions 28 are at the side edges of the gate. 300 angstroms (300 angstroms) over the source and drain regions 1B, 18
A titanium silicide layer 30 having a thickness of X10-'C is present laterally adjacent the oxide area 28. A corresponding thin titanium silicide layer 32 also overlies the gate.

Referring to FIG. 2, to fabricate the device, boron ions are implanted at location 4 to establish a channel stop or isolation region, and the W.
17 ac L i wear areas are defined by thermally oxidizing regions of the silicon substrate 10 to 1000° C. using the well-known partial silicon oxidation (LOGO3) technique! , ff13, polysilicon Ji124 was then deposited by low pressure chemical vapor deposition (LP) at 625°C.
G V D ) and 40 ohms/
A titanium silicide layer 26, doped with phosphorus from a POC13 gas source to give a square sheet resistance, is then deposited by DC magnetron sputtering at ambient temperature using a composite (eoposiLe) target. Ru.

After annealing in argon at 900° C. for 30 minutes, the titanium silicide/polysilicon composite layer yields a sheet resistance of 1 ohm/square. If MoSi2 and WSi are used instead of titanium silicide, a temperature of 1000° C. for 30 minutes is required. The resulting stractures are unique in that the functionality of polysilicon on oxide is very well known and a smooth interface can be obtained with good oxide layer integrity. Maintains the properties of polysilicon/silicon dioxide interlayer. The struf- tures are compatible with other high temperature processing steps used in the manufacture of integrated circuits.

The silicide/polysilicon composite gate layer 24,26 is then
The device gates are patterned in a reactive ion etching (RIE) system using a chlorine-based gaseous etchant to define the device gates. This gate pattern can also be performed before annealing.

Referring to FIG. 4, the shallow junction source and drain regions 16.18 are made of As.
+ ions with an energy of 50 keV and V 5 X 1
Implantation with radiation #1lfi of 0''/0m2 followed by a subsequent annealing step at 925°C for 30 minutes.

Sidewall oxide regions 28 are formed using reactive ion etching in a 7-wire based plasma followed by low pressure chemical vapor deposition to deposit a 0.5 micron layer of silicon dioxide over the sources, drains and gates. made by corroding and removing. Because the oxide is thicker on the gate walls, and because the material is etched vertically by reactive etching, even if the oxide is completely removed from above the gate, the sides! ! l! The oxide portion remains.

A thin titanium silicide layer 32 is then formed by sputter depositing 300 angstroms of titanium/le and then sintering the titanium layer at 600C. A thin layer of titanium silicide is formed where titanium is present over silicon in the gate, source and drain regions. The titanium above the field and I-walled areas remains unreacted and is removed by etching with a solution consisting of H,O, :NH,OH:H,O in a volume ratio of 1:1:5. Ru.

After removing the unreacted titanium, the titanium silicide is sintered again at 800° C. to further reduce the sheet resistance.

Although in the particular embodiment described above the silicide present in the gate and on the source and drain is titanium silicide, other silicides such as silicides of tungsten, molybdenum, and tantalum can also be used; And in addition to these refractory metals, some noble metals such as platinum and palladium can also make effective bonded silicides.

When titanium is used to form the thin bond silicide layer, unreacted titanium must be removed from the insulating oxide, but this metal removal step may be unnecessary when other metals are used.

Thus, for example, tungsten (W) can be extracted from WF, atmosphere to source, drain and ? -) can be selectively chemical vapor deposited on the surface. No etching is necessary because no metal deposition occurs on the oxide regions.

In yet another method, the silicide layer on the source and drain is formed by first depositing a refractory metal layer and then irradiating the region on the source and drain with ions of a selected conductivity type at high temperature (bosbardiB). , formed simultaneously with and over a region in exact vertical alignment with the source and drain regions.

The ions, such as As+ ions in n-channel devices and ions in BF2F2 for p-channel devices, also penetrate into the silicon to form a doped source or doped region, and the refractory metal and the underlying It has sufficient energy to promote interface mixing (mtxing) with some silicon, resulting in the formation of silicide.

In certain embodiments of the description, the gate conductive layer is formed by deposition of a polysilicon layer and doping of its scraps, followed by deposition of gold R-silicide, but instead the gate conductive layer is formed of a uniform composition. can be deposited as a single layer of refractory metal silicide.

Although the thin collar of metal in the junction silicide layer is consumed by silicide formation on the source and drain, the metal deposited on the gate merely provides a metal-rich upper layer of the gate. be.

Therefore, if a deposition/etching method is used,
The metal-rich portion on top of the gate layer can be removed when the metal overlying the oxide layer is etched away. The refractory or noble metal used in the gate silicide formation may be different from the metal used in the gate conduction layer.

[Brief explanation of the drawing]

Figure 1 shows the present invention G: VLS I MOSFET
and FIGS. 2-4 illustrate successive steps in fabricating the transistor of FIG. 1 using manufacturing techniques according to the present invention. DESCRIPTION OF SYMBOLS 10...p-type physical substrate, 12...insulating field oxide region, 14...p+
Type region 16.18...11+ type drain and its large region, 20...Channel region, 22...Gate oxide layer, 24...Polysilicon scrap, 26.30.32... Titanium silicide layer, 28... insulating oxide region.

Claims (1)

Claims: 1. forming a region of field oxide on a semiconductor substrate; forming a gate oxide within a device wall defined by the field oxide; forming a conductive gate layer overlying and defining a gate region therein, the conductive gate layer having a refractory metal or refractory metal silicide content; In a method of manufacturing a VLSI circuit using a refractory metal silicide, the method includes the steps of: forming source and drain regions in the semiconductor; forming a thin junction silicide layer over the source, drain and gate regions; A method characterized by forming. 2. The method of claim 1, further comprising forming the gate layer by depositing a first layer of polysilicon and a second layer of refractory metal silicide. 3. The method of claim 1, further comprising forming the gate layer by depositing a refractory metal silicide. 4. The method of claim 1, further comprising forming the gate layer by depositing a layer of a refractory metal, one of the group of refractory metals consisting of molybdenum and tungsten, over the gate. 5. The method of claim 1 further comprising depositing a first layer of polysilicon and a second layer of a refractory metal from the group of metals consisting of titanium, tantalum, tungsten and molybdenum. . 6. Further depositing a layer of refractory metal and polysilicon;
The method of claim 1, wherein the silicide of the conductive gate layer is formed by reacting the refractory metal with the polysilicon. 7. A method as claimed in any one of claims 1 to 3, further comprising depositing the gate silicide layer by direct current magnetron sputtering followed by annealing. 8. Claims 1-6 further comprising defining the gate region in the gate layer by reactive ion etching.
The method described in any one of Sections. 9. The method of claim 1 further comprising forming an insulating oxide region between the gate region and the source and drain regions before forming the thin junction silicide layer. The method described in section. 10. further depositing a layer of oxide on the wafer to completely remove the oxide over the gate, the source, and the drain and leaving the insulating oxide region adjacent the sidewalls; 10. The method of claim 9, wherein the insulating oxide region is formed between the gate region and the source and drain regions by etching away the oxide. 11. A thin metal layer is further deposited over the source, drain, gate and oxide (28) regions, forming a silicide where the metal is present over the source, drain and gate. 11. The method of claim 10, wherein a bonded metal silicide layer is formed by sintering a thin metal layer and melting unreacted metal over the insulating oxide region. 12. The method of claim 10, further comprising forming the thin junction silicide layer by selectively depositing a tungsten layer only on the source, drain and gate and sintering. . 13. Claims 1-12 further comprising forming the source and drain junctions by implanting ions prior to forming the thin junction silicide layer and then sintering the ion implanted regions. The method described in any one of Sections. 14. Further, the metal of the thin bonding silicide layer is molybdenum,
Claims 1 to 1 are one of the group consisting of titanium, tantalum, tungsten, platinum and palladium.
14. The method according to any one of clauses 13. 15. Further, any one of claims 1 to 14, wherein the thickness of the gate layer is in the range of 1000 angstroms (1 x 10^-^5 cm) to 3000 angstroms (3 x 10^-^5 cm). The method described in one section. 16. Claims 1 to 15 further characterized in that the thickness of the bonded silicide layer is in the range of 100 angstroms (1 x 10^-^6 cm) to 2000 angstroms (2 x 10^-^5 cm). A method as described in any one section. 17. a silicon substrate, a source and a drain formed in the substrate with a channel region extending therebetween, overlying the channel region and separated therefrom by an insulating layer; at least a portion of the gate is a refractory metal or metal silicide layer, and the gate, source, and drain have a top junction refractory metal or silicide layer. MOSFET
wherein the gate refractory metal or silicide layer has a greater thickness than the junction refractory metal or refractory metal silicide layer.