JPS6239917A - Phase locked loop oscillation circuit - Google Patents

Abstract

PURPOSE:To reduce the time required for re-locking by keeping a control voltage of a voltage controlled oscillator to a constant value when a reference signal input is lost for a short period. CONSTITUTION:A digital frequency divider 5 generates a forecast gate signal 23 covering the existing position of a reference signal input 1. A supervisory circuit 19 uses the reference signal input 1 and a gate signal 23 to output a reference signal input detection output 24 and a reference signal input undetected output 25. When the output 24 is not inputted for a predetermined time or over, a lock-on detector 20 outputs logic '0' of the output 26. A sample-and-hold control gate generator 21 generates a pulse of logic '1' from the output 25 up to the time constant. A sample-and-hold circuit 18 is operated as the sample mode when an output signal 28 is logic '0' and and as the hold mode when logic '1', that is, the circuit 18 holds an output voltage 8a and moment the logic '0' is changed into logic '1' and output a control voltage 8b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that accelerates the pull-in time in a frame phase synchronized oscillator circuit used in a time division multiplexer or the like.

[Conventional technology]

FIG. 3 is a block configuration diagram showing a conventional phase-locked oscillator circuit, and FIGS. 4 to 11 are detailed in the technical data regarding MC4044 of Motorola, USA, etc.
FIG. 2 is a circuit configuration diagram of each part in a conventional phase-locked oscillation circuit, and a diagram for explaining its operation. In FIG. 3, 1 is the reference signal input of the phase synchronized oscillation circuit, 2 is the phase detector, 3 is the integrator, 4 is the voltage controlled oscillator (VCO), 5 is the digital frequency divider, and 6 is the digital frequency divider 5. This output 6 is applied to the other input (comparison input) of the phase detector 2. FIG. 4 shows a specific configuration example of the phase detector 2, where 17 is a functional block which is a circuit that performs the operations shown in FIGS. 6 and 7, R1 is a load resistance of the functional block 17, Resistor R8 and capacitor C3 constitute a low pass filter. Figure 5 shows a specific example of the configuration of the integrator 3. In Figure 5, each resistor R, R, and capacitor C1 are constants that determine the integration time constant, and 11 is an operational amplifier with a very large DC gain. It is. 8 shows the phase comparison characteristic of the phase detector 2, and FIG. 9 shows the phase comparison characteristic of the phase detector 2 and the integrator 3 combined. Figure 1O shows the operation when the phase synchronized oscillation circuit is locked on (synchronized pull-in), and Figure 11 shows the reference signal 1 when the phase synchronized oscillation circuit is locked on.
This shows the situation when one is missing.

Next, the operation of the above-described conventional phase-locked oscillation circuit will be explained. The output of the VCO 4 is frequency-divided by n by a digital divider 5 and applied to the comparison input (input V in FIG. 4) of the phase detector 2. On the other hand, the reference signal 1 is applied to the other input of the phase detector 2 (input R in FIG. 4) at approximately the same period. The phase detector 2 operates as follows. In FIG. 4, if various phase relationships of each input JV are considered, the result will be as shown in FIGS. 6 and 7. That is, when the input R is ahead of the input V in phase as shown in FIG. 6, the point 10 (
As shown in the figure, a positive pulse is obtained at the output U) from the fall of the human power ratio pulse to the fall of the input V pulse. Conversely, if the input V is ahead of the input R in phase, a negative pulse will be obtained as the output U from the fall of the input ■ to the fall of the human power ratio, as shown in Figure 7. . When this is passed through a low-pass filter consisting of a resistor R2 and a capacitor C8, a DC voltage 7 corresponding to the phase difference between the input R and the input V is obtained. As can be seen from this explanation, since the width of the positive or negative pulse obtained at the output U is proportional to the phase difference between the input R and the input V, the phase comparison characteristic of the phase detector 2 is shown in FIG. 8. get.

By passing the output of the phase detector 2 obtained in this way through an integrator 3 called a loop filter, vC0
Appropriate negative feedback is applied to 4, and phase synchronization is applied so that the phase difference between input R and input V becomes almost zero for the entire circuit shown in FIG. Figure 9 shows phase detector 2.
Integrator 3. It shows the overall characteristics of the three elements of VCO4 connected continuously, and the output frequency of VCO4 is controlled in the range of 1+ and [- according to the phase difference between the input V and the human power ratio, and generally the output frequency of VCO4 is In addition, since the DC gain of the integrator 3 is very large, the output frequency of the VCO 4 corresponding to the phase difference y or y, which is considerably smaller than the phase difference 2π, is 1+ and ``-''.
4 shows that the change in output frequency is saturated.

Next, in this phase-locked loop,
The operation when the input R is temporarily cut off will be explained. FIG. 1O shows a case where phase synchronization pull-in is performed regularly. The falling edges of the input R and input V pulses are drawn in so that they are almost the same, and depending on the slight phase error associated with this drawing, a thin pulse on the positive or negative side is generated, and the positive two pages are balanced. The synchronous pull-in is kept stable. FIG. 11 shows a case where one input R is missing. In this case, a negative polarity is output when the input V falls, but this is reset and returned to the GND potential only when the input R is obtained next.

A wide negative pulse corresponding to this will be stored as is in the integrator 3.

The control voltage 8 of the VCO 4 changes greatly, making it impossible to maintain one-phase synchronization.

If the input R recovers in such a state, the initial phase difference between the input R and the input ■ is generally not controlled, so the 9th
There is almost no possibility that the input/output characteristics shown in the figure fall into a linear region, and generally the pull-in operation is started from a state in which the output frequency of vC04 is saturated. In this pulling operation, the phase difference between the input R and the input V changes at a speed corresponding to the frequency difference between the frequency of the pulse of the human power ratio and the pulse of the input V created by dividing the output frequency of the VCO4. When the phase difference falls within Da+ or Go, a lock-in operation is performed due to the so-called pull-in operation characteristic of the phase-locked loop.

Here, assuming that Da+ or Go is almost 0, the maximum time required for the retracting operation will be as shown below.

(Example) Center frequency of VCO4 'o = 10 MHz
Maximum frequency of VCO4 f+= 10.001 Mkl
zVCO4 minimum frequency f-=9.999M1 (
Pulse frequency of z input = 500 Hz Number of divisions n of digital frequency divider 5 = 20000 In this case, the pull-in operation time TL is given by the following equation.

Or, therefore, in the above example, TL=20 (seconds).

[Problem that the invention seeks to solve]

Since the conventional phase-locked oscillator circuit described above is configured as described above, there is a problem that it takes a long time for re-pulling operation each time when the reference signal 1 is intermittently lost. there were.

The present invention was made to solve this problem, and an object of the present invention is to provide a phase-locked oscillator circuit that can shorten the time required for the re-pulling operation even if the reference signal input is lost for a short period of time. shall be.

[Means for solving problems]

The phase synchronized oscillator circuit according to the present invention maintains the control voltage of the voltage controlled oscillator constant so that when the reference signal input is lost for a short period of time, the phase of the branch output signal does not fluctuate during that time. This is intended to shorten the time required for the retraction operation when signal input is again obtained.

[Effect]

The phase synchronized oscillation circuit of the present invention detects intermittent or temporary line disconnection and fixes the phase of the phase synchronized oscillation circuit, thereby preventing the phase synchronized oscillation circuit from locking off.

〔Example〕

FIG. 1 is a block diagram showing a phase synchronized oscillation circuit according to an embodiment of the present invention, and reference numerals 1 to 6 are the same as those in the conventional example shown in FIG. 3 above. In the figure, 18 is a sample/hold circuit, 19 is a monitoring circuit for monitoring the presence or absence of the reference signal 1, 20 is a lock-on detector, 21 is a sample/hold control gate generator, and 22 is an AND circuit.

FIG. 2 is a diagram showing the operation timing of each part in the phase synchronized oscillation circuit of FIG. 1.

Next, the operation of the phase-locked oscillator circuit, which is an embodiment of the invention described above, will be explained. When the digital branching unit 5 shown in FIG. 1 is in steady operation after synchronization pull-in, the position of the reference signal human power 1 can be predicted, so it generates a predicted gate signal that covers the position of the reference signal human power 1. . The gate signal 23 shown in FIG. 2 shows this aspect. The monitoring circuit 19 shown in FIG. 1 uses the reference signal input 1 and the gate signal 23, and outputs a reference signal input detection output and a reference signal input non-detection output 25. This aspect is
= Shown in the figure. In FIG. 2, a, d, and e are reference signals that were actually input (shown by solid lines), and b and c are reference signals that were not input (shown by dotted lines).

The lock-on detector 20 operates in response to a reference signal input detection output 24, and when this reference signal input detection output 24 is not input for a predetermined period of time or more, its output 26 becomes a logic rOJ. Operate. The example shown in Figure 2 shows a case where two reference signals are missing,
At this level of defect, the output 26 of the lock-on detector 20
is assumed to hold logic "1". Note that this predetermined period of time should be determined based on the requirements of the system in which this phase-locked oscillation circuit is used. The sample/hold control gate generator 21 is composed of a monostable multivibrator etc. that is triggered by the reference signal input non-detection output 25, and the sample/hold control gate generator 21 is composed of a monostable multivibrator etc. that is triggered by the reference signal input non-detection output 25. generates a logic ``1'' pulse.

As a result, as the output signal path of the AND circuit 22, -1
〇- Obtain what is shown in Figure 2. The sample/hold circuit I8 shown in FIG. 1 operates in a sample mode when the output signal 28 is logic "o", that is, in a mode in which the voltage applied to the output voltage 8a of the integrator 3 is directly obtained as the control voltage 8b of the VCO 4. When the logic is "1", it is in hold mode, that is, the output voltage is 8 at the moment the logic changes from "o" to "1".
It operates in a mode in which it holds the voltage a and outputs it to the control voltage 8b. In this way, the problem with the conventional example described above is that when the reference signal 1 is missing, the control voltage 8b of the VCO 4 changes suddenly, and therefore the output frequency of the VCO 4 changes significantly, causing phase synchronization to be lost. This problem can be solved.

Note that the magnitude of the time constant TH is determined by considering the time constant of the integrator 3 so that the loop pull-in operation can be performed smoothly when the reference signal human power 1 is restored. Since this determination method is not the purpose of this invention, its explanation will be omitted.

〔Effect of the invention〕

As explained above, this invention is configured so that the control voltage of the voltage controlled oscillator does not suddenly change even if the reference signal input is lost for a short time in the phase synchronized oscillator circuit. , the difference between the phase of the reference signal input and the phase of the branch output signal is suppressed to a sufficiently small value, and the re-pulling operation is significantly shortened.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing a phase-locked oscillation circuit which is an embodiment of the present invention, FIG. 2 is a diagram showing the operation timing of each part in the phase-locked oscillation circuit of FIG. 1, and FIG. FIGS. 4 to 11, which are block diagrams showing a phase synchronization oscillation circuit, are circuit diagrams of each part in a conventional phase synchronization excavation circuit and diagrams for explaining its operation. In the figure, 1... Reference signal input, 2... Phase detector, 3... Integrator, 4... Voltage controlled oscillator (VCO).
), 5... Digital frequency divider, 6... Output of digital frequency divider 5, 18... Sample/hold circuit,
19... Monitoring circuit, 20... Lock-on detector, 21... Sample/hold control gate generator, 2
2... It is an AND circuit. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a phase synchronized oscillation circuit that divides the output frequency of a voltage controlled oscillator by n (an integer) and synchronizes the phase of the divided output signal with another periodic reference signal input applied from the outside, the reference signal input is predicted. The monitoring system includes a circuit that detects whether or not the reference signal exists at the predicted position and generates a detection pulse and a non-detection pulse of the reference signal input at the predicted position, and a monitoring circuit that monitors the synchronization state of the phase-locked loop. In a state determined by the circuit to be a synchronous pull-in state, the reference signal input is lost and the voltage at the time when the non-detection pulse is generated is held, thereby changing the position of the frequency-divided output signal and the A phase-locked oscillator circuit characterized in that it prevents the occurrence of a phase difference at a corresponding position of a reference signal input, and resumes normal phase-locked loop operation after a certain period of time has elapsed.