JPS6239919A - Phase locked loop oscillation circuit - Google Patents

Abstract

PURPOSE:To reduce remarkably the time required for re-locking operation by applying initial setting of a phase locked loop and holding of a control voltage of a voltage controlled oscillator when a reference signal input is missing temporarily or consecutively and then restored again. CONSTITUTION:When the reference signal input 1 is lost for a short time in the phase locked oscillation circuit, the control voltage 8b of the voltage controlled oscillator 4 is kept constant so that the phase of the output of the frequency divider 5 is not fluctuated for the time. If the reference signal input 1 is lost over a long time and the reference signal input is obtained again, the operating point of the frequency divider 5 is set initially to obtain quick re-locking operation for the phase of the output of the frequency divider. Thus, the time required for re-locking of the phase locked loop is reduced remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that accelerates the pull-in time in a frame phase synchronized oscillator circuit used in a one-time division multiplexer or the like.

[Conventional technology]

FIG. 6 is a block configuration diagram showing a conventional phase-locked oscillator circuit, and FIGS. 7 to 14 are detailed in technical data regarding MC4044 of Motorola, USA, etc.
FIG. 2 is a circuit configuration diagram of each part in a conventional phase-locked oscillation circuit, and a diagram for explaining its operation. In FIG. 6, 1 is the reference signal input of the phase synchronized oscillation circuit, 2 is the phase detector, 3 is the integrator, 4 is the voltage controlled oscillator (VCO), 5 is the digital frequency divider, and 6 is the digital frequency divider 5. This output 6 is applied to the other input (comparison input) of the phase detector 2. FIG. 7 shows a specific configuration example of the phase detector 2, where 17 is a functional block which is a circuit that performs the operations shown in FIGS. 9 and 10, RI is a load resistance of the functional block 17, Resistor R8 and capacitor C1 constitute a low pass filter. Figure 8 shows a specific example of the configuration of the integrator 3. The resistors Rs, R, and capacitor C8 in Figure 1 are constants that determine the integration time constant, and 11 is an operational amplifier with a very large DC gain. be. FIG. 11 shows the phase comparison characteristics of the phase detector 2.

FIG. 12 shows the combined phase comparison characteristics of the phase detector 2 and integrator 3. Figure 13 shows the operation when the phase synchronized oscillation circuit is locked on (synchronous pull-in), and Figure 14 shows the operation when the phase synchronized oscillation circuit is locked on and one reference signal 1 is missing. This shows the aspect of

Next, the operation of the above-mentioned conventional interphase Ju4@oscillator circuit will be explained. The output of VCO4 is digitally divided by a5
The frequency is divided by n and applied to the comparison input of the phase detector 2 (input V in FIG. 7). on the other hand.

At almost the same period as this, the reference signal 1 is output to the phase detector 2.
is applied to the other input (input R in FIG. 7). The phase detector 2 operates as follows. In Fig. 7, considering various phase relationships of each human power R and V,
As shown in FIGS. 9 and 10. That is, the ninth
As shown in the figure, if the input R is ahead of the input V in phase, then J.

At point 10 (output U) shown in FIG. 7, a positive pulse is obtained from the falling edge of the input R pulse to the falling edge of the input V pulse, as shown in the figure. Conversely, if the input V leads the input R in phase, the output U
As shown in FIG. 10, a negative pulse is obtained from the fall of the input V to the fall of the human power R. When this is passed through a low-pass filter consisting of a resistor R8 and a capacitor C1, a DC voltage 7 corresponding to the phase difference between the input R and the input V is obtained. As can be seen from this explanation, the width of the positive or negative pulse obtained at the output U is proportional to the phase difference between the input R and the input V, so the phase comparison characteristic of the single-phase detector 2 is shown in FIG. 11. get.

By passing the output of the phase detector 2 obtained in this way through an integrator 3 called a loop filter, the VCO
4 is subjected to appropriate negative feedback, and the entire circuit shown in FIG. 6 is phase synchronized so that the phase difference between input R and input V becomes almost zero. Figure 12 shows phase detector 2.
．． Integrator 3. The output frequency of VCO4 is controlled in the range of f+ and f- according to the phase difference between input V and input R, and generally the output frequency of VCO4 is It can change infinitely, and since the direct current gain of integrator 3 is very large, 1
At the output frequencies f+ and f- of the VCO 4 corresponding to a phase difference ψ or φ- which is considerably smaller than the phase difference 2π, V
This shows that the change in the output frequency of CO4 is saturated.

Next, in this phase-locked loop,
The operation when the human power R is temporarily cut off will be explained. FIG. 13 shows a case where phase synchronization pull-in is performed regularly. The falling edges of the input R and input V pulses are drawn in so that they are almost the same, and the slight phase difference that accompanies this drawing generates thin pulses on the positive or negative side. Balanced and synchronous pull-in is kept stable. In Figure 14, the input R is 1
This shows the case where one part is missing. In this case, a negative polarity is output at the falling edge of the input V, which is then caused by the input R
Only after this is obtained, a reset is performed and the potential is returned to GND. A wide negative pulse corresponding to this will be stored as it is in the integrator 3, and the control voltage 8 of the VCO 4 will change greatly, and the phase synchronization pull-in will be held and IA will disappear.

When the input R recovers in such a state, the initial phase difference between the input R and the input V is generally not controlled, so the first
There is almost no possibility that the input/output characteristics shown in FIG. 2 fall into the linear region, and generally the pull-in operation is started from a state in which the output frequency of vC04 is saturated. In this pull-in operation, the phase difference between input R and input V is equal to the frequency of the input R pulse.

It changes at a speed corresponding to the frequency difference between the input V pulses created by dividing the output frequency of VCO4, and the phase difference is ψ
1 or ψ-, a lock-in operation is performed due to the so-called pull-in characteristic of the phase-locked loop.

Here, assuming that ψ1 or ψ- is almost 0, the maximum time required for the retracting operation is as shown below.

(Example) Center frequency of VCO4 fo -10MH
zVCO4 maximum frequency f+=10.001MHz
Minimum frequency of VCO 4 f-=9.999 MHz Pulse frequency of human power R 500 Hz Number of divisions of digital frequency divider 5 n = 20000 In this case, the pull-in operation time TL is given by the following equation.

Or, therefore, in the above example, TL=20 (seconds).

[Problem that the invention seeks to solve]

The conventional phase-locked oscillator circuit described above is configured as described above, so that after the reference signal input is temporarily or continuously lost due to a disconnection of the line, the reference signal input is recovered again. case.

There was a problem in that the retraction operation took a long time.

The present invention was made in order to solve such problems, and is a phase synchronization system that can significantly reduce the time required for re-pulling operation when the reference signal input is restored after being temporarily or continuously lost. The purpose is to obtain an oscillation circuit.

[Means for solving problems]

The phase-locked oscillator circuit according to the present invention performs re-pulling operation by initializing one phase-locked loop and holding the control voltage of the voltage-controlled oscillator when the reference signal input is restored after being temporarily or continuously lost. The aim is to shorten the time required.

[Effect]

In the phase-locked oscillator circuit of the present invention, if the reference signal power is lost for a short period of time.

By keeping the control voltage of the voltage controlled oscillator constant so that the phase of the output of the frequency divider does not vary during that time,
If the reference signal input is lost for an extended period of time, the operating point of the divider can be initialized so that the phase of the divider output can be quickly re-pulsed when the reference signal input is regained. By setting this, the time required for the re-pulling operation of the 1-phase locked loop can be significantly shortened.

〔Example〕

FIG. 1 is a block diagram showing a phase-locked oscillator circuit according to an embodiment of the present invention, and reference numerals 1 to 6 are the same as those in the conventional example shown in FIG. 6 above. In the figure, 11 is a reference signal human power 1 detector to which the reference signal human power 1 is applied;
12 is an aperture gate generator, 13 is an AND circuit, 1
6 is a reset pulse for initializing the digital frequency divider 5, 18 is a sample/hold circuit, 19 is a monitoring circuit that monitors the presence or absence of the reference signal 1, 20 is a lock-on detector, and 21 is a sample/hold control. gate generator,
22 indicates an AND circuit, and 29 indicates a NOT circuit.

2 to 5 are diagrams showing the operation timing of each part in the phase-locked oscillation circuit of FIG. 1.

Next, the operation of the phase-locked oscillator circuit, which is an embodiment of the invention described above, will be explained. When the digital frequency divider 5 shown in FIG. 1 is in steady operation after synchronization pull-in, the position of the reference signal human power 1 can be predicted, so it generates a predictive gate signal that covers the position of the reference signal human power l. do. The gate signal 23 shown in FIG. 2 shows this aspect. The monitoring circuit 19 shown in FIG. 1 uses the reference signal input 1 and the gate -10- signal 23, and outputs a reference signal input detection output 24 and a reference signal input non-detection output 25. This aspect is illustrated in FIG. a and b shown in FIG.

C is the actually input reference signal (shown as a solid line).

b and c are reference signals (indicated by dotted lines) that were not input. The lock-on detector 20 has a reference signal input detection output 24
This reference signal input detection output 24
When the input signal is not input for a predetermined period of time ('rn), the output 26 becomes logic "0". The example shown in FIG. 2 shows a case where two reference signals are missing, and it is assumed that in this level of loss, the output 26 of the lock-on detector 20 holds logic "1".

Note that this predetermined fixed time (TB) should be determined based on the requirements of the system in which this phase-locked oscillation circuit is used. sample/
The hold control gate generator 21 is composed of a monostable multivibrator or the like that is triggered by the reference signal input non-detection output 25, and is logic during the time constant Tc from the reference signal input non-detection output 25 detected after JI. "1" t
Generates 4J response.

As a result, the output signal 28 of the AND circuit 22 shown in FIG. 2 is obtained. The sample/hold circuit 18 shown in FIG. 1 is in a sample mode when the output signal 28 is logic "0", that is, a mode in which the voltage applied to the output voltage 8a of the integrator 3 is directly obtained as the control voltage 8b of vC04. When the logic is "1", the output voltage 8a is held and the control voltage 8bl is output at the moment the logic changes from "0" to "1". In this way, there are problems with the conventional series mentioned above.

That is, to solve the problem that when the reference signal 1 is missing, the control voltage 8b of the VCO 4 changes suddenly, and the output frequency of the VCO 4 changes greatly, causing the phase synchronization to be lost. I can do it.

Note that the magnitude of the time constant Tc is determined in consideration of the time constant of the integrator 3 so that the loop pull-in operation can be performed smoothly when the reference signal human power 1 is restored.
The determination method is not the purpose of this invention, so its explanation will be omitted.

The foregoing discussion has described the operation of a short loss of the reference signal 1 such that the output 26 of the lock-on detector 20 is a logic "1", ie, the phase-locked loop is determined to be in lock-on. If the reference signal 1 is continuously lost for a certain length of time, the characteristics of the sample/hold circuit 18 are not ideal, so the control voltage 8b of V2O3, which is its output voltage, gradually changes.
The phase difference between the phase of the pulse output from the digital frequency divider 5 and the timing at which the reference signal 1 was present gradually becomes larger. Therefore, if the reference signal 1 is missing for more than a certain period of time, the sample/hold circuit 18
Therefore, there is no reason to maintain the voltage. The time corresponding to this time is defined as lock-off time (TB),
When the reference signal input non-detection output 25 continues for 15 times or more, the lock-on detector 20 returns its output 26 to logic "0",
As a result, the sample/hold circuit 18 enters the sample mode and returns to normal phase synchronization.

Next, the operation when the reference signal human power 1 is applied again after the lock-off determination is made in this manner will be described. FIG. 3 shows the output signal 14 of the reference signal human power 1° detector 11. The operation of a short single gate pulse 15 and a reset pulse 16 of the aperture gate generator 12 is shown.

In the figure, reference signal human power 1 is a pulse indicated by f, which is the first pulse applied. It is assumed that the subsequent pulses of 1 or less are input periodically. The detector 11 is composed of a monostable multivibrator that is repeatedly triggered at the rising edge of the reference signal 1, and the output signal 14 of the detector 11 is generated at the beginning of the reference signal 1 as shown in FIG. It turns on at the rising edge of f. In response to the rise of this output signal 14, the aperture gate generator 12 generates a short single gate pulse 15. By applying this gate pulse 15 and the reference signal 1 to the AND circuit 13, a reset pulse 16 as shown in FIG. 1 is obtained as its output.

On the other hand, FIG. 4 shows the operation of the digital frequency divider 5. The digital frequency divider 5 can be considered as an example of a counter that counts up at the output frequency of the VCO 4, and the counter repeats the operation of counting up from 0 to (n-1) and returning to O again. The output 6 of the digital frequency divider 5, ie the input V, is created when the counter value changes to 1, for example to 0. The reference signal input 1 and reset pulse 16 shown in FIG. 5 are the same as those shown in FIG. The output 6 of the digital frequency divider 5 is the above-mentioned V
The CO4 output is frequency-divided by n and runs on its own, but when the reference signal 1 is first applied, the reset pulse 1 is applied.
6 initializes the counter value, and as a result, the phase of the output 6 with respect to the reference signal 1 is forced to the distance T+ shown in FIG. It goes without saying that it is desirable that the value of this distance T1 be smaller than 1ψ+1 or 1ψ-1 explained in FIG. 12.

For each distance T, ,T, the pull-in is performed by a phase-locked loop, and the reference signal 1 and the output 6. That is, it conceptually shows that the phase difference between input R and input V becomes smaller. In the above initial setting operation, the output signal 30 of the NOT circuit 29 is logic "1".

In other words, this is performed only when a lock-off determination is being made. This lock-off determination is performed by quickly re-engaging the phase-locked loop through the above initial setting operation.
When the reference signal input detection output 24 continues for a predetermined time T or more, it is reset and a lock-on determination is made. The operation when the reference signal human power 1 is lost after lock-on is achieved is as described above.

〔Effect of the invention〕

As explained above, the present invention is designed to prevent the control voltage of the VCO from suddenly changing when the reference signal input is lost for a short time in the phase synchronized oscillation circuit.

In addition, if the reference signal input 1 is lost for a long time, the initial pull-in phase of the phase synchronized oscillation circuit is set appropriately, so when the reference signal input is obtained again, the phase of the reference signal input is The phase difference between the output signal of the frequency divider and the output signal of the frequency divider is kept sufficiently small, and the time required for the re-pulling operation can be significantly shortened, which is an excellent effect.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing a phase-locked oscillation circuit which is an embodiment of the present invention, FIGS. 2 to 5 are diagrams showing the operation timing of each part in the phase-locked oscillation circuit of FIG. The figure is a block diagram showing a conventional phase-locked oscillation circuit, and FIGS. 7 to 14 are diagrams for explaining the circuit configuration of each part in the conventional phase-locked oscillation circuit and its operation. In the figure, 1... reference signal input, 2... phase detector, 3... integrator, 4... voltage controlled oscillator (CVO
). 5... Digital frequency divider, 6... Output of digital frequency divider 5, 11... Detector, 12... Aperture gate generator, 13.22... AND circuit, 16...・
Reset pulse, 18...sample/hold circuit,
19... Monitoring circuit, 20... Lock-on detector, 2
1... Sample/hold control gate generator, 29.
...It is a negative circuit. In each figure, the same reference numerals indicate the same or similar parts. Figure 8 Figure 9 Figure 10 Figure 11 Figure 12

Claims (1)

[Claims] In a phase synchronized oscillation circuit that divides the output frequency of a voltage controlled oscillator by n (an integer) and synchronizes the phase of the divided output signal with another periodic reference signal input applied from the outside, the reference signal input is predicted. monitors the synchronization state of the phase-locked loop and the circuit that detects whether or not the detected pulse exists at the predicted position and generates the detected pulse and non-detected pulse of the reference signal input at the predicted position, and the detected pulse is constant. a synchronization determination circuit that determines lock-off when the undetected pulse is not detected for a certain period of time or more, and determines lock-on when the undetected pulse is not detected for a certain period of time;
When the reference signal input is missing and the non-detection pulse is generated, the voltage that controls the voltage controlled oscillator is maintained at the level at which the non-detection pulse was generated for a certain period of time from the time when the last non-detection pulse was generated. On the other hand, if it is in the lock-on state, and after a certain period of time has passed, the holding operation is stopped and normal phase-locked loop operation is resumed, and furthermore, if it is determined that the lock-off state is , the normal phase-locked loop operation is performed unconditionally, and the phase difference between the output signal of the frequency divider and the reference signal input is zero when the reference signal input is first obtained after becoming a lock-off device. A phase synchronized oscillation circuit characterized in that the initial setting of the frequency divider is performed so that the frequency divider is set as follows.